11#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_ICSR_H_
12#define ZEPHYR_INCLUDE_ARCH_RISCV_ICSR_H_
17#ifdef CONFIG_RISCV_ISA_EXT_SMCSRIND
24static inline unsigned long micsr_read(
unsigned int index)
40static inline void micsr_write(
unsigned int index,
unsigned long value)
55static inline void micsr_set(
unsigned int index,
unsigned long mask)
70static inline void micsr_clear(
unsigned int index,
unsigned long mask)
86static inline unsigned long micsr_read_set(
unsigned int index,
unsigned long mask)
103static inline unsigned long micsr_read_clear(
unsigned int index,
unsigned long mask)
119static inline unsigned long micsr2_read(
unsigned int index)
124 unsigned long val =
csr_read(MIREG2);
135static inline void micsr2_write(
unsigned int index,
unsigned long value)
150static inline void micsr2_set(
unsigned int index,
unsigned long mask)
165static inline void micsr2_clear(
unsigned int index,
unsigned long mask)
181static inline unsigned long micsr2_read_set(
unsigned int index,
unsigned long mask)
198static inline unsigned long micsr2_read_clear(
unsigned int index,
unsigned long mask)
#define csr_read(csr)
Definition csr.h:210
#define csr_clear(csr, val)
Definition csr.h:255
#define csr_set(csr, val)
Definition csr.h:237
#define csr_read_clear(csr, val)
Definition csr.h:246
#define csr_read_set(csr, val)
Definition csr.h:228
#define csr_write(csr, val)
Definition csr.h:218
#define irq_lock()
Lock interrupts.
Definition irq.h:259
#define irq_unlock(key)
Unlock interrupts.
Definition irq.h:287
Public interface for configuring interrupts.