intc_esp32.h

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/*
 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32_H_
#define ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32_H_
 
#include <stdint.h>
#include <stdbool.h>
 
/* number of possible interrupts per core */
#define ESP_INTC_INTS_NUM               (32)
 
/*
 * Interrupt allocation flags - These flags can be used to specify
 * which interrupt qualities the code calling esp_intr_alloc* needs.
 *
 */
 
/* Keep the LEVELx values as they are here; they match up with (1<<level) */
#define ESP_INTR_FLAG_LEVEL1            (1<<1)  /* Accept a Level 1 int vector, lowest priority */
#define ESP_INTR_FLAG_LEVEL2            (1<<2)  /* Accept a Level 2 int vector */
#define ESP_INTR_FLAG_LEVEL3            (1<<3)  /* Accept a Level 3 int vector */
#define ESP_INTR_FLAG_LEVEL4            (1<<4)  /* Accept a Level 4 int vector */
#define ESP_INTR_FLAG_LEVEL5            (1<<5)  /* Accept a Level 5 int vector */
#define ESP_INTR_FLAG_LEVEL6            (1<<6)  /* Accept a Level 6 int vector */
#define ESP_INTR_FLAG_NMI               (1<<7)  /* Accept a Level 7 int vector, highest priority */
#define ESP_INTR_FLAG_SHARED            (1<<8)  /* Interrupt can be shared between ISRs */
#define ESP_INTR_FLAG_EDGE              (1<<9)  /* Edge-triggered interrupt */
#define ESP_INTR_FLAG_IRAM              (1<<10) /* ISR can be called if cache is disabled */
#define ESP_INTR_FLAG_INTRDISABLED      (1<<11) /* Return with this interrupt disabled */
 
/* Low and medium prio interrupts. These can be handled in C. */
#define ESP_INTR_FLAG_LOWMED    (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3)
 
/* High level interrupts. Need to be handled in assembly. */
#define ESP_INTR_FLAG_HIGH      (ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \
                                 ESP_INTR_FLAG_NMI)
 
/* Mask for all level flags */
#define ESP_INTR_FLAG_LEVELMASK (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3| \
                                 ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \
                                 ESP_INTR_FLAG_NMI)
 
/*
 * Get the interrupt flags from the supplied priority.
 */
#define ESP_PRIO_TO_FLAGS(priority) \
        ((priority) > 0 ? ((1 << (priority)) & ESP_INTR_FLAG_LEVELMASK) : 0)
 
/*
 * Check interrupt flags from input and filter unallowed values.
 */
#define ESP_INT_FLAGS_CHECK(int_flags) ((int_flags) & ESP_INTR_FLAG_SHARED)
 
/*
 * The esp_intr_alloc* functions can allocate an int for all *_INTR_SOURCE int sources that
 * are routed through the interrupt mux. Apart from these sources, each core also has some internal
 * sources that do not pass through the interrupt mux. To allocate an interrupt for these sources,
 * pass these pseudo-sources to the functions.
 */
#define ETS_INTERNAL_TIMER0_INTR_SOURCE         -1 /* Xtensa timer 0 interrupt source */
#define ETS_INTERNAL_TIMER1_INTR_SOURCE         -2 /* Xtensa timer 1 interrupt source */
#define ETS_INTERNAL_TIMER2_INTR_SOURCE         -3 /* Xtensa timer 2 interrupt source */
#define ETS_INTERNAL_SW0_INTR_SOURCE            -4 /* Software int source 1 */
#define ETS_INTERNAL_SW1_INTR_SOURCE            -5 /* Software int source 2 */
#define ETS_INTERNAL_PROFILING_INTR_SOURCE      -6 /* Int source for profiling */
 
/* Function prototype for interrupt handler function */
typedef void (*intr_handler_t)(void *arg);
 
struct shared_vector_desc_t {
        int disabled : 1;
        int source : 8;
        volatile uint32_t *statusreg;
        uint32_t statusmask;
        intr_handler_t isr;
        void *arg;
        struct shared_vector_desc_t *next;
};
 
/* Pack using bitfields for better memory use */
struct vector_desc_t {
        int flags : 16;                                 /* OR of VECDESC_FLAG_* defines */
        unsigned int cpu : 1;
        unsigned int intno : 5;
        int source : 8;                                 /* Int mux flags, used when not shared */
        struct shared_vector_desc_t *shared_vec_info;   /* used when VECDESC_FL_SHARED */
        struct vector_desc_t *next;
};
 
struct intr_handle_data_t {
        struct vector_desc_t *vector_desc;
        struct shared_vector_desc_t *shared_vector_desc;
};
 
void esp_intr_initialize(void);
 
int esp_intr_mark_shared(int intno, int cpu, bool is_in_iram);
 
int esp_intr_reserve(int intno, int cpu);
 
int esp_intr_alloc(int source,
                int flags,
                intr_handler_t handler,
                void *arg,
                struct intr_handle_data_t **ret_handle);
 
 
int esp_intr_alloc_intrstatus(int source,
                int flags,
                uint32_t intrstatusreg,
                uint32_t intrstatusmask,
                intr_handler_t handler,
                void *arg,
                struct intr_handle_data_t **ret_handle);
 
 
int esp_intr_free(struct intr_handle_data_t *handle);
 
 
int esp_intr_get_cpu(struct intr_handle_data_t *handle);
 
int esp_intr_get_intno(struct intr_handle_data_t *handle);
 
int esp_intr_disable(struct intr_handle_data_t *handle);
 
int esp_intr_enable(struct intr_handle_data_t *handle);
 
int esp_intr_set_in_iram(struct intr_handle_data_t *handle, bool is_in_iram);
 
void esp_intr_noniram_disable(void);
 
void esp_intr_noniram_enable(void);
 
#endif /* ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32_H_ */