13#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_MICROCHIP_SAM_PMC_H_
14#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_MICROCHIP_SAM_PMC_H_
59#define SAM_DT_CLOCK_PMC_CFG(clock, node_id) { \
60 .clock_type = DT_CLOCKS_CELL_BY_IDX(node_id, \
63 .clock_id = DT_CLOCKS_CELL_BY_IDX(node_id, \
73#define SAM_DT_INST_CLOCK_PMC_CFG(inst) SAM_DT_CLOCK_PMC_CFG(0, DT_DRV_INST(inst))
80#define SAM_DT_CLOCKS_PMC_CFG(node_id) { \
81 LISTIFY(DT_NUM_CLOCKS(node_id), \
82 SAM_DT_CLOCK_PMC_CFG, (,), node_id) \
90#define SAM_DT_INST_CLOCKS_PMC_CFG(inst) SAM_DT_CLOCKS_PMC_CFG(DT_DRV_INST(inst))
Main header file for clock control driver API.
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
Runtime device structure (in ROM) per driver instance.
Definition device.h:513
PMC clock configuration for a single peripheral clock.
Definition mchp_sam_pmc.h:33
uint32_t clock_type
Clock type (see microchip_sam_pmc.h DT bindings).
Definition mchp_sam_pmc.h:34
uint32_t clock_id
Peripheral identifier within the PMC.
Definition mchp_sam_pmc.h:35
PMC device constant configuration parameters.
Definition mchp_sam_pmc.h:39
const struct device * td_slck
Timing-domain slow clock device.
Definition mchp_sam_pmc.h:41
const struct sam_sckc_config md_slck_cfg
Main-domain slow clock configuration.
Definition mchp_sam_pmc.h:45
const struct sam_sckc_config td_slck_cfg
Timing-domain slow clock configuration.
Definition mchp_sam_pmc.h:44
const struct device * main_xtal
Main crystal oscillator device.
Definition mchp_sam_pmc.h:43
uint32_t *const reg
PMC register base address.
Definition mchp_sam_pmc.h:40
const struct device * md_slck
Main-domain slow clock device.
Definition mchp_sam_pmc.h:42
PMC device run-time data.
Definition mchp_sam_pmc.h:49
struct pmc_data * pmc
Backend PMC instance data.
Definition mchp_sam_pmc.h:50
Slow Clock Controller (SCKC) configuration.
Definition mchp_sam_pmc.h:27
uint32_t crystal_osc
Use the external crystal oscillator instead of the RC.
Definition mchp_sam_pmc.h:28
uint32_t reserved
Reserved.
Definition mchp_sam_pmc.h:29