Zephyr API Documentation 4.3.99
A Scalable Open Source RTOS
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pinctrl-rcar-common.h
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1/*
2 * Copyright (c) 2021-2023 IoT.bzh
3 * Copyright (c) 2025 Renesas Electronics Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
13
14#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_
15#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_
16
33#define IPSR(bank, shift, func) (((bank) << 10U) | ((shift) << 4U) | (func))
34
35/* Arbitrary number to encode non capable gpio pin */
36#define PIN_NOGPSR_START 1024U
37
44#define RCAR_GP_PIN(bank, pin) (((bank) * 32U) + (pin))
45
51#define RCAR_NOGP_PIN(pin) (PIN_NOGPSR_START + pin)
52
53/* Renesas Gen4 has IPSR registers at different base address
54 * reg is here an index for the base address.
55 * Each base address has 4 IPSR banks.
56 */
57#define IPnSR(bank, reg, shift, func) \
58 IPSR(((reg) << 5U) | (bank), shift, func)
59
60#define IP0SR0(shift, func) IPnSR(0, 0, shift, func)
61#define IP1SR0(shift, func) IPnSR(1, 0, shift, func)
62#define IP2SR0(shift, func) IPnSR(2, 0, shift, func)
63#define IP3SR0(shift, func) IPnSR(3, 0, shift, func)
64#define IP0SR1(shift, func) IPnSR(0, 1, shift, func)
65#define IP1SR1(shift, func) IPnSR(1, 1, shift, func)
66#define IP2SR1(shift, func) IPnSR(2, 1, shift, func)
67#define IP3SR1(shift, func) IPnSR(3, 1, shift, func)
68#define IP0SR2(shift, func) IPnSR(0, 2, shift, func)
69#define IP1SR2(shift, func) IPnSR(1, 2, shift, func)
70#define IP2SR2(shift, func) IPnSR(2, 2, shift, func)
71#define IP3SR2(shift, func) IPnSR(3, 2, shift, func)
72#define IP0SR3(shift, func) IPnSR(0, 3, shift, func)
73#define IP1SR3(shift, func) IPnSR(1, 3, shift, func)
74#define IP2SR3(shift, func) IPnSR(2, 3, shift, func)
75#define IP3SR3(shift, func) IPnSR(3, 3, shift, func)
76#define IP0SR4(shift, func) IPnSR(0, 4, shift, func)
77#define IP1SR4(shift, func) IPnSR(1, 4, shift, func)
78#define IP2SR4(shift, func) IPnSR(2, 4, shift, func)
79#define IP3SR4(shift, func) IPnSR(3, 4, shift, func)
80#define IP0SR5(shift, func) IPnSR(0, 5, shift, func)
81#define IP1SR5(shift, func) IPnSR(1, 5, shift, func)
82#define IP2SR5(shift, func) IPnSR(2, 5, shift, func)
83#define IP3SR5(shift, func) IPnSR(3, 5, shift, func)
84#define IP0SR6(shift, func) IPnSR(0, 6, shift, func)
85#define IP1SR6(shift, func) IPnSR(1, 6, shift, func)
86#define IP2SR6(shift, func) IPnSR(2, 6, shift, func)
87#define IP3SR6(shift, func) IPnSR(3, 6, shift, func)
88#define IP0SR7(shift, func) IPnSR(0, 7, shift, func)
89#define IP1SR7(shift, func) IPnSR(1, 7, shift, func)
90#define IP2SR7(shift, func) IPnSR(2, 7, shift, func)
91#define IP3SR7(shift, func) IPnSR(3, 7, shift, func)
92#define IP0SR8(shift, func) IPnSR(0, 8, shift, func)
93#define IP1SR8(shift, func) IPnSR(1, 8, shift, func)
94#define IP2SR8(shift, func) IPnSR(2, 8, shift, func)
95#define IP3SR8(shift, func) IPnSR(3, 8, shift, func)
96
107#define IPSR_DUMMY IPnSR(0x1f, 7, 0x1f, 0xf)
108
109#define PIN_VOLTAGE_NONE 0
110#define PIN_VOLTAGE_1P8V 1
111#define PIN_VOLTAGE_3P3V 2
112
114#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_ */