renesas_rcar_generic.h

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/*
 * Copyright (c) 2026 BayLibre, SAS
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 
#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RCAR_GENERIC_H_
#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RCAR_GENERIC_H_

 
/* Gen 5 boards deal with clocks through SCMI. */
#ifdef CONFIG_CLOCK_CONTROL_ARM_SCMI
 
#include <zephyr/drivers/clock_control.h>

#define RCAR_DT_INST_CLOCKS_CELL_BY_IDX(inst, idx)                                      \
{                                                                                       \
        .subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_IDX(inst, idx, name)   \
}

#define RCAR_CLOCK_SUBSYS(clk) (clk).subsys

struct rcar_generic_clk {
        clock_control_subsys_t subsys;
};

typedef struct rcar_generic_clk rcar_generic_clk_t;
 
/* Gen 3 and gen 4 boards directly access the clock controller module. */
#else
 
#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>

#define RCAR_DT_INST_CLOCKS_CELL_BY_IDX(inst, idx)                      \
{                                                                       \
        .module = DT_INST_CLOCKS_CELL_BY_IDX(inst, idx, module),        \
        .domain = DT_INST_CLOCKS_CELL_BY_IDX(inst, idx, domain)         \
}

#define RCAR_CLOCK_SUBSYS(clk) (clock_control_subsys_t)&(clk)

typedef struct rcar_cpg_clk rcar_generic_clk_t;
 
#endif /* CONFIG_CLOCK_CONTROL_ARM_SCMI */

 
#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RCAR_GENERIC_H_ */