Zephyr API Documentation 4.3.99
A Scalable Open Source RTOS
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rtl87x2g-pinctrl.h
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1/*
2 * Copyright (c) 2026, Realtek Semiconductor Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
14
15#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RTL87X2G_PINCTRL_H_
16#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RTL87X2G_PINCTRL_H_
17
18#include "bee-pinctrl.h"
19
24#define BEE_IDLE_MODE 0
25#define BEE_UART0_TX 1
26#define BEE_UART0_RX 2
27#define BEE_UART0_CTS 3
28#define BEE_UART0_RTS 4
29#define BEE_UART1_TX 5
30#define BEE_UART1_RX 6
31#define BEE_UART1_CTS 7
32#define BEE_UART1_RTS 8
33#define BEE_UART2_TX 9
34#define BEE_UART2_RX 10
35#define BEE_UART2_CTS 11
36#define BEE_UART2_RTS 12
37#define BEE_UART3_TX 13
38#define BEE_UART3_RX 14
39#define BEE_UART3_CTS 15
40#define BEE_UART3_RTS 16
41#define BEE_UART4_TX 17
42#define BEE_UART4_RX 18
43#define BEE_UART4_CTS 19
44#define BEE_UART4_RTS 20
45#define BEE_UART5_TX 21
46#define BEE_UART5_RX 22
47#define BEE_UART5_CTS 23
48#define BEE_UART5_RTS 24
49#define BEE_I2C0_CLK 29
50#define BEE_I2C0_DAT 30
51#define BEE_I2C1_CLK 31
52#define BEE_I2C1_DAT 32
53#define BEE_I2C2_CLK 33
54#define BEE_I2C2_DAT 34
55#define BEE_I2C3_CLK 35
56#define BEE_I2C3_DAT 36
57#define BEE_SPI0_CLK_MASTER 37
58#define BEE_SPI0_MO_MASTER 38
59#define BEE_SPI0_MI_MASTER 39
60#define BEE_SPI0_CSN_0_MASTER 40
61#define BEE_SPI0_CSN_1_MASTER 41
62#define BEE_SPI0_CSN_2_MASTER 42
63#define BEE_SPI0_CSN_0_SLAVE 43
64#define BEE_SPI0_CLK_SLAVE 44
65#define BEE_SPI0_SO_SLAVE 45
66#define BEE_SPI0_SI_SLAVE 46
67#define BEE_SPI1_CLK_MASTER 47
68#define BEE_SPI1_MO_MASTER 48
69#define BEE_SPI1_MI_MASTER 49
70#define BEE_SPI1_CSN_0_MASTER 50
71#define BEE_SPI1_CSN_1_MASTER 51
72#define BEE_SPI1_CSN_2_MASTER 52
73#define BEE_SPI2W_DATA 53
74#define BEE_SPI2W_CLK 54
75#define BEE_SPI2W_CS 55
76#define BEE_ENPWM0_P 65
77#define BEE_ENPWM0_N 66
78#define BEE_ENPWM1_P 67
79#define BEE_ENPWM1_N 68
80#define BEE_ENPWM2_P 69
81#define BEE_ENPWM2_N 70
82#define BEE_ENPWM3_P 71
83#define BEE_ENPWM3_N 72
84#define BEE_TIMER_PWM2 83
85#define BEE_TIMER_PWM3 84
86#define BEE_ISO7816_RST 85
87#define BEE_ISO7816_CLK 86
88#define BEE_ISO7816_IO 87
89#define BEE_ISO7816_VCC_EN 88
90#define BEE_DWGPIO 89
91#define BEE_IRDA_TX 90
92#define BEE_IRDA_RX 91
93#define BEE_TIMER_PWM4 92
94#define BEE_TIMER_PWM5 93
95#define BEE_TIMER_PWM6 94
96#define BEE_TIMER_PWM7 95
97#define BEE_TIMER_PWM2_P 96
98#define BEE_TIMER_PWM2_N 97
99#define BEE_TIMER_PWM3_P 98
100#define BEE_TIMER_PWM3_N 99
101#define BEE_KEY_COL_0 100
102#define BEE_KEY_COL_1 101
103#define BEE_KEY_COL_2 102
104#define BEE_KEY_COL_3 103
105#define BEE_KEY_COL_4 104
106#define BEE_KEY_COL_5 105
107#define BEE_KEY_COL_6 106
108#define BEE_KEY_COL_7 107
109#define BEE_KEY_COL_8 108
110#define BEE_KEY_COL_9 109
111#define BEE_KEY_COL_10 110
112#define BEE_KEY_COL_11 111
113#define BEE_KEY_COL_12 112
114#define BEE_KEY_COL_13 113
115#define BEE_KEY_COL_14 114
116#define BEE_KEY_COL_15 115
117#define BEE_KEY_COL_16 116
118#define BEE_KEY_COL_17 117
119#define BEE_KEY_COL_18 118
120#define BEE_KEY_COL_19 119
121#define BEE_KEY_ROW_0 120
122#define BEE_KEY_ROW_1 121
123#define BEE_KEY_ROW_2 122
124#define BEE_KEY_ROW_3 123
125#define BEE_KEY_ROW_4 124
126#define BEE_KEY_ROW_5 125
127#define BEE_KEY_ROW_6 126
128#define BEE_KEY_ROW_7 127
129#define BEE_KEY_ROW_8 128
130#define BEE_KEY_ROW_9 129
131#define BEE_KEY_ROW_10 130
132#define BEE_KEY_ROW_11 131
133#define BEE_KM4_CLK_DIV_4 138
134#define BEE_CARD_DETECT_N_0 147
135#define BEE_BIU_VOLT_REG_0 148
136#define BEE_BACK_END_POWER_0 149
137#define BEE_CARD_INT_N_SDHC_0 150
138#define BEE_A2C_TX 155
139#define BEE_A2C_RX 156
140#define BEE_LRC_SPORT1 157
141#define BEE_BCLK_SPORT1 158
142#define BEE_ADCDAT_SPORT1 159
143#define BEE_DACDAT_SPORT1 160
144#define BEE_DMIC1_CLK 162
145#define BEE_DMIC1_DAT 163
146#define BEE_LRC_I_CODEC_SLAVE 164
147#define BEE_BCLK_I_CODEC_SLAVE 165
148#define BEE_SDI_CODEC_SLAVE 166
149#define BEE_SDO_CODEC_SLAVE 167
150#define BEE_LRC_SPORT0 172
151#define BEE_BCLK_SPORT0 173
152#define BEE_ADCDAT_SPORT0 174
153#define BEE_DACDAT_SPORT0 175
154#define BEE_MCLK_OUT 176
155#define BEE_MCLK_IN 189
156#define BEE_LRC_RX_CODEC_SLAVE 190
157#define BEE_LRC_RX_SPORT0 191
158#define BEE_LRC_RX_SPORT1 192
159#define BEE_PDM_DATA 196
160#define BEE_PDM_CLK 197
161#define BEE_I2S1_LRC_TX_SLAVE 198
162#define BEE_I2S1_BCLK_SLAVE 199
163#define BEE_I2S1_SDI_SLAVE 200
164#define BEE_I2S1_SDO_SLAVE 201
165#define BEE_I2S1_LRC_RX_SLAVE 202
166#define BEE_BT_COEX_I_0 216
167#define BEE_BT_COEX_I_1 217
168#define BEE_BT_COEX_I_2 218
169#define BEE_BT_COEX_I_3 219
170#define BEE_BT_COEX_O_0 220
171#define BEE_BT_COEX_O_1 221
172#define BEE_BT_COEX_O_2 222
173#define BEE_BT_COEX_O_3 223
174#define BEE_PTA_I2C_CLK_SLAVE 224
175#define BEE_PTA_I2C_DAT_SLAVE 225
176#define BEE_PTA_I2C_INT_OUT 226
177#define BEE_EN_EXPA 227
178#define BEE_EN_EXLNA 228
179#define BEE_SEL_TPM_SW 229
180#define BEE_SEL_TPM_N_SW 230
181#define BEE_ANT_SW0 231
182#define BEE_ANT_SW1 232
183#define BEE_ANT_SW2 233
184#define BEE_ANT_SW3 234
185#define BEE_ANT_SW4 235
186#define BEE_ANT_SW5 236
187#define BEE_PHY_GPIO_1 237
188#define BEE_PHY_GPIO_2 238
189#define BEE_SLOW_DEBUG_MUX_1 239
190#define BEE_SLOW_DEBUG_MUX_2 240
191#define BEE_TEST_MODE 246
192#define BEE_SWD_CLK 253
193#define BEE_SWD_DIO 254
194#define BEE_DIG_DEBUG 255
195#define BEE_PINMUX_MAX (BEE_DIG_DEBUG + 1)
196#define BEE_SW_MODE (BEE_PINMUX_MAX + 1)
197#define BEE_PWR_OFF (BEE_PINMUX_MAX + 2)
198#define BEE_SDHC0_CLK_P9_4 (BEE_PWR_OFF + 1)
199#define BEE_SDHC0_CMD_P9_3 (BEE_PWR_OFF + 2)
200#define BEE_SDHC0_D0_P10_0 (BEE_PWR_OFF + 3)
201#define BEE_SDHC0_D1_P9_7 (BEE_PWR_OFF + 4)
202#define BEE_SDHC0_D2_P9_6 (BEE_PWR_OFF + 5)
203#define BEE_SDHC0_D3_P9_5 (BEE_PWR_OFF + 6)
204#define BEE_SDHC0_D4_P4_4 (BEE_PWR_OFF + 7)
205#define BEE_SDHC0_D5_P4_5 (BEE_PWR_OFF + 8)
206#define BEE_SDHC0_D6_P4_6 (BEE_PWR_OFF + 9)
207#define BEE_SDHC0_D7_P4_7 (BEE_PWR_OFF + 10)
208#define BEE_SDHC1_CLK_P9_4 (BEE_PWR_OFF + 11)
209#define BEE_SDHC1_CMD_P9_3 (BEE_PWR_OFF + 12)
210#define BEE_SDHC1_D0_P10_0 (BEE_PWR_OFF + 13)
211#define BEE_SDHC1_D1_P9_7 (BEE_PWR_OFF + 14)
212#define BEE_SDHC1_D2_P9_6 (BEE_PWR_OFF + 15)
213#define BEE_SDHC1_D3_P9_5 (BEE_PWR_OFF + 16)
214#define BEE_SDHC1_D4_P4_4 (BEE_PWR_OFF + 17)
215#define BEE_SDHC1_D5_P4_5 (BEE_PWR_OFF + 18)
216#define BEE_SDHC1_D6_P4_6 (BEE_PWR_OFF + 19)
217#define BEE_SDHC1_D7_P4_7 (BEE_PWR_OFF + 20)
218#define BEE_QDPH0_IN_NONE 0x0F00
219#define BEE_QDPH0_IN_P1_3_P1_4 0x0F01
220#define BEE_QDPH0_IN_P5_6_P5_7 0x0F02
221#define BEE_QDPH0_IN_P9_0_P9_1 0x0F03
222#define BEE_PIN_DISCONNECTED BEE_PIN_MSK
224
229#define P0_0 0
230#define P0_1 1
231#define P0_2 2
232/* Note: P0_3 defaults to outputting the Realtek internal log for rtl87x2g. */
233#define P0_3 3
234#define P0_4 4
235#define P0_5 5
236#define P0_6 6
237#define P0_7 7
238/* Note: P0_0/P0_1 default to SWD function for rtl87x2g. */
239#define P1_0 8
240#define P1_1 9
241#define P1_2 10
242#define P1_3 11
243#define P1_4 12
244#define P1_5 13
245#define P1_6 14
246#define P1_7 15
247#define P2_0 16
248#define P2_1 17
249#define P2_2 18
250#define P2_3 19
251#define P2_4 20
252#define P2_5 21
253#define P2_6 22
254#define P2_7 23
255#define P3_0 24
256#define P3_1 25
257#define P3_2 26
258#define P3_3 27
259#define P3_4 28
260#define P3_5 29
261#define P3_6 30
262#define P3_7 31
263#define P4_0 32
264#define P4_1 33
265#define P4_2 34
266#define P4_3 35
267#define P4_4 36
268#define P4_5 37
269#define P4_6 38
270#define P4_7 39
271#define P5_0 40
272#define P5_1 41
273#define P5_2 42
274#define P5_3 43
275#define P5_4 44
276#define P5_5 45
277#define P5_6 46
278#define P5_7 47
279#define P6_0 48
280#define P6_1 49
281#define P6_2 50
282#define P6_3 51
283#define P6_4 52
284#define P6_5 53
285#define P6_6 54
286#define P6_7 55
287#define P7_0 56
288#define P7_1 57
289#define P7_2 58
290#define P7_3 59
291#define P7_4 60
292#define MICBIAS 64
293#define XI32K 65
294#define XO32K 66
295#define DACP 67
296#define DACN 68
297#define P9_0 72
298#define P9_1 73
299#define P9_2 74
300#define P9_3 75
301#define P9_4 76
302#define P9_5 77
303#define P9_6 78
304#define P9_7 79
305#define P10_0 80
306#define P10_1 81
307#define P10_2 82
308#define ADC_0 P2_0
309#define ADC_1 P2_1
310#define ADC_2 P2_2
311#define ADC_3 P2_3
312#define ADC_4 P2_4
313#define ADC_5 P2_5
314#define ADC_6 P2_6
315#define ADC_7 P2_7
317
322/* Port 0 */
323#define BEE_PSEL_GPIOA_0_P0_0 BEE_PSEL(DWGPIO, P0_0)
324#define BEE_PSEL_GPIOA_1_P0_1 BEE_PSEL(DWGPIO, P0_1)
325#define BEE_PSEL_GPIOA_2_P0_2 BEE_PSEL(DWGPIO, P0_2)
326/* Note: P0_3 defaults to outputting the Realtek internal log for rtl87x2g. */
327#define BEE_PSEL_GPIOA_3_P0_3 BEE_PSEL(DWGPIO, P0_3)
328#define BEE_PSEL_GPIOA_4_P0_4 BEE_PSEL(DWGPIO, P0_4)
329#define BEE_PSEL_GPIOA_5_P0_5 BEE_PSEL(DWGPIO, P0_5)
330#define BEE_PSEL_GPIOA_6_P0_6 BEE_PSEL(DWGPIO, P0_6)
331#define BEE_PSEL_GPIOA_7_P0_7 BEE_PSEL(DWGPIO, P0_7)
332
333/* Port 1 */
334/* Note: P0_0/P0_1 default to SWD function for rtl87x2g. */
335#define BEE_PSEL_GPIOA_8_P1_0 BEE_PSEL(DWGPIO, P1_0)
336#define BEE_PSEL_GPIOA_9_P1_1 BEE_PSEL(DWGPIO, P1_1)
337#define BEE_PSEL_GPIOA_10_P1_2 BEE_PSEL(DWGPIO, P1_2)
338#define BEE_PSEL_GPIOA_11_P1_3 BEE_PSEL(DWGPIO, P1_3)
339#define BEE_PSEL_GPIOA_12_P1_4 BEE_PSEL(DWGPIO, P1_4)
340#define BEE_PSEL_GPIOA_13_P1_5 BEE_PSEL(DWGPIO, P1_5)
341#define BEE_PSEL_GPIOA_14_P1_6 BEE_PSEL(DWGPIO, P1_6)
342#define BEE_PSEL_GPIOA_15_P1_7 BEE_PSEL(DWGPIO, P1_7)
343
344/* Port 2 */
345#define BEE_PSEL_GPIOA_21_P2_0 BEE_PSEL(DWGPIO, P2_0)
346#define BEE_PSEL_GPIOA_22_P2_1 BEE_PSEL(DWGPIO, P2_1)
347#define BEE_PSEL_GPIOA_23_P2_2 BEE_PSEL(DWGPIO, P2_2)
348#define BEE_PSEL_GPIOA_24_P2_3 BEE_PSEL(DWGPIO, P2_3)
349#define BEE_PSEL_GPIOA_25_P2_4 BEE_PSEL(DWGPIO, P2_4)
350#define BEE_PSEL_GPIOA_26_P2_5 BEE_PSEL(DWGPIO, P2_5)
351#define BEE_PSEL_GPIOA_27_P2_6 BEE_PSEL(DWGPIO, P2_6)
352#define BEE_PSEL_GPIOA_28_P2_7 BEE_PSEL(DWGPIO, P2_7)
353
354/* Port 3 */
355#define BEE_PSEL_GPIOA_29_P3_0 BEE_PSEL(DWGPIO, P3_0)
356#define BEE_PSEL_GPIOA_30_P3_1 BEE_PSEL(DWGPIO, P3_1)
357#define BEE_PSEL_GPIOA_31_P3_2 BEE_PSEL(DWGPIO, P3_2)
358#define BEE_PSEL_GPIOB_0_P3_3 BEE_PSEL(DWGPIO, P3_3)
359#define BEE_PSEL_GPIOB_1_P3_4 BEE_PSEL(DWGPIO, P3_4)
360#define BEE_PSEL_GPIOB_2_P3_5 BEE_PSEL(DWGPIO, P3_5)
361#define BEE_PSEL_GPIOB_3_P3_6 BEE_PSEL(DWGPIO, P3_6)
362#define BEE_PSEL_GPIOB_4_P3_7 BEE_PSEL(DWGPIO, P3_7)
363
364/* Port 4 */
365#define BEE_PSEL_GPIOB_5_P4_0 BEE_PSEL(DWGPIO, P4_0)
366#define BEE_PSEL_GPIOB_6_P4_1 BEE_PSEL(DWGPIO, P4_1)
367#define BEE_PSEL_GPIOB_7_P4_2 BEE_PSEL(DWGPIO, P4_2)
368#define BEE_PSEL_GPIOB_8_P4_3 BEE_PSEL(DWGPIO, P4_3)
369#define BEE_PSEL_GPIOB_9_P4_4 BEE_PSEL(DWGPIO, P4_4)
370#define BEE_PSEL_GPIOB_10_P4_5 BEE_PSEL(DWGPIO, P4_5)
371#define BEE_PSEL_GPIOB_11_P4_6 BEE_PSEL(DWGPIO, P4_6)
372#define BEE_PSEL_GPIOB_12_P4_7 BEE_PSEL(DWGPIO, P4_7)
373
374/* Port 5 */
375#define BEE_PSEL_GPIOB_13_P5_0 BEE_PSEL(DWGPIO, P5_0)
376#define BEE_PSEL_GPIOB_14_P5_1 BEE_PSEL(DWGPIO, P5_1)
377#define BEE_PSEL_GPIOB_15_P5_2 BEE_PSEL(DWGPIO, P5_2)
378#define BEE_PSEL_GPIOB_16_P5_3 BEE_PSEL(DWGPIO, P5_3)
379#define BEE_PSEL_GPIOB_17_P5_4 BEE_PSEL(DWGPIO, P5_4)
380#define BEE_PSEL_GPIOB_18_P5_5 BEE_PSEL(DWGPIO, P5_5)
381#define BEE_PSEL_GPIOB_19_P5_6 BEE_PSEL(DWGPIO, P5_6)
382#define BEE_PSEL_GPIOB_20_P5_7 BEE_PSEL(DWGPIO, P5_7)
383
384/* Port 6 */
385#define BEE_PSEL_GPIOB_19_P6_0 BEE_PSEL(DWGPIO, P6_0)
386#define BEE_PSEL_GPIOB_20_P6_1 BEE_PSEL(DWGPIO, P6_1)
387#define BEE_PSEL_GPIOB_21_P6_2 BEE_PSEL(DWGPIO, P6_2)
388#define BEE_PSEL_GPIOB_22_P6_3 BEE_PSEL(DWGPIO, P6_3)
389#define BEE_PSEL_GPIOB_23_P6_4 BEE_PSEL(DWGPIO, P6_4)
390#define BEE_PSEL_GPIOB_24_P6_5 BEE_PSEL(DWGPIO, P6_5)
391#define BEE_PSEL_GPIOB_25_P6_6 BEE_PSEL(DWGPIO, P6_6)
392#define BEE_PSEL_GPIOB_26_P6_7 BEE_PSEL(DWGPIO, P6_7)
393
394/* Port 7 */
395#define BEE_PSEL_GPIOB_27_P7_0 BEE_PSEL(DWGPIO, P7_0)
396#define BEE_PSEL_GPIOB_28_P7_1 BEE_PSEL(DWGPIO, P7_1)
397#define BEE_PSEL_GPIOB_29_P7_2 BEE_PSEL(DWGPIO, P7_2)
398#define BEE_PSEL_GPIOB_30_P7_3 BEE_PSEL(DWGPIO, P7_3)
399#define BEE_PSEL_GPIOB_31_P7_4 BEE_PSEL(DWGPIO, P7_4)
400
401/* Special Functions / Port 8 Equivalent */
402/* Note: Using P8_x extracted from comments */
403#define BEE_PSEL_GPIOA_16_P8_0 BEE_PSEL(DWGPIO, MICBIAS)
404#define BEE_PSEL_GPIOA_17_P8_1 BEE_PSEL(DWGPIO, XI32K)
405#define BEE_PSEL_GPIOA_18_P8_2 BEE_PSEL(DWGPIO, XO32K)
406#define BEE_PSEL_GPIOA_19_P8_3 BEE_PSEL(DWGPIO, DACP)
407#define BEE_PSEL_GPIOA_20_P8_4 BEE_PSEL(DWGPIO, DACN)
408
409/* Port 9 */
410#define BEE_PSEL_GPIOB_21_P9_0 BEE_PSEL(DWGPIO, P9_0)
411#define BEE_PSEL_GPIOB_22_P9_1 BEE_PSEL(DWGPIO, P9_1)
412#define BEE_PSEL_GPIOB_23_P9_2 BEE_PSEL(DWGPIO, P9_2)
413#define BEE_PSEL_GPIOB_24_P9_3 BEE_PSEL(DWGPIO, P9_3)
414#define BEE_PSEL_GPIOB_25_P9_4 BEE_PSEL(DWGPIO, P9_4)
415#define BEE_PSEL_GPIOB_26_P9_5 BEE_PSEL(DWGPIO, P9_5)
416#define BEE_PSEL_GPIOB_27_P9_6 BEE_PSEL(DWGPIO, P9_6)
417#define BEE_PSEL_GPIOB_28_P9_7 BEE_PSEL(DWGPIO, P9_7)
418
419/* Port 10 */
420#define BEE_PSEL_GPIOB_29_P10_0 BEE_PSEL(DWGPIO, P10_0)
421#define BEE_PSEL_GPIOB_30_P10_1 BEE_PSEL(DWGPIO, P10_1)
422#define BEE_PSEL_GPIOB_31_P10_2 BEE_PSEL(DWGPIO, P10_2)
423
425
426#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RTL87X2G_PINCTRL_H_ */
Realtek BEE Pinctrl Devicetree Bindings.