Zephyr API Documentation
4.4.99
A Scalable Open Source RTOS
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siwx91x-pinctrl.h
Go to the documentation of this file.
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/*
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* Copyright (c) 2024 Silicon Laboratories Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_SIWX91X_PINCTRL_H_
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#define INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_SIWX91X_PINCTRL_H_
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#include <
zephyr/dt-bindings/pinctrl/silabs-pinctrl-siwx91x.h
>
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#define AGPIO_ULP0 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 0)
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#define AGPIO_ULP1 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 1)
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#define AGPIO_ULP2 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 2)
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#define AGPIO_ULP4 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 4)
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#define AGPIO_ULP5 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 5)
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#define AGPIO_ULP6 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 6)
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#define AGPIO_ULP7 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 7)
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#define AGPIO_ULP8 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 8)
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#define AGPIO_ULP9 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 9)
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#define AGPIO_ULP10 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 10)
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#define AGPIO_ULP11 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 11)
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#define ADC_TOPGPIO_HP25 SIWX91X_GPIO(14, 0xFF, 0, 1, 9, 0)
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#define ADC_TOPGPIO_HP26 SIWX91X_GPIO(14, 0xFF, 0, 1, 10, 0)
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#define ADC_TOPGPIO_HP27 SIWX91X_GPIO(14, 0xFF, 0, 1, 11, 0)
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#define ADC_TOPGPIO_HP28 SIWX91X_GPIO(14, 0xFF, 0, 1, 12, 0)
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#define ADC_TOPGPIO_HP29 SIWX91X_GPIO(14, 0xFF, 0, 1, 13, 0)
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#define ADC_TOPGPIO_HP30 SIWX91X_GPIO(14, 0xFF, 0, 1, 14, 0)
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#define AUXULP_TRIG0_HP11 SIWX91X_GPIO(9, 5, 6, 0, 11, 5)
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#define AUXULP_TRIG0_HP30 SIWX91X_GPIO(11, 5, 0, 1, 14, 11)
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#define AUXULP_TRIG0_HP49 SIWX91X_GPIO(9, 5, 13, 3, 1, 11)
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#define AUXULP_TRIG0_ULP5 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 5)
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#define AUXULP_TRIG0_ULP6 SIWX91X_GPIO(0xFF, 10, 0xFF, 4, 0, 6)
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#define AUXULP_TRIG0_ULP11 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 11)
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#define AUXULP_TRIG1_ULP4 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 4)
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#define AUXULP_TRIG1_ULP7 SIWX91X_GPIO(0xFF, 10, 0xFF, 4, 0, 7)
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#define CLK_I2SPLL_HP27 SIWX91X_GPIO(12, 0xFF, 0, 1, 11, 0)
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#define CLK_I2SPLL_HP48 SIWX91X_GPIO(10, 0xFF, 12, 3, 0, 0)
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#define CLK_I2SPLL_HP54 SIWX91X_GPIO(10, 0xFF, 18, 3, 6, 0)
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#define CLK_INTFPLL_HP26 SIWX91X_GPIO(12, 0xFF, 0, 1, 10, 0)
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#define CLK_INTFPLL_HP47 SIWX91X_GPIO(10, 0xFF, 11, 2, 15, 0)
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#define CLK_INTFPLL_HP53 SIWX91X_GPIO(10, 0xFF, 17, 3, 5, 0)
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#define CLK_MCUOUT_HP11 SIWX91X_GPIO(12, 0xFF, 6, 0, 11, 0)
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#define CLK_MEMSREF_HP50 SIWX91X_GPIO(10, 0xFF, 14, 3, 2, 0)
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#define CLK_MEMSREF_HP56 SIWX91X_GPIO(10, 0xFF, 20, 3, 8, 0)
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#define CLK_OUT_HP12 SIWX91X_GPIO(8, 0xFF, 7, 0, 12, 0)
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#define CLK_OUT_HP15 SIWX91X_GPIO(8, 0xFF, 8, 0, 15, 0)
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#define CLK_PLLTESTMODE_HP51 SIWX91X_GPIO(10, 0xFF, 15, 3, 3, 0)
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#define CLK_SOCPLL_HP25 SIWX91X_GPIO(12, 0xFF, 0, 1, 9, 0)
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#define CLK_SOCPLL_HP46 SIWX91X_GPIO(10, 0xFF, 10, 2, 14, 0)
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#define CLK_SOCPLL_HP52 SIWX91X_GPIO(10, 0xFF, 16, 3, 4, 0)
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#define CLK_XTALONIN_HP28 SIWX91X_GPIO(12, 0xFF, 0, 1, 12, 0)
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#define CLK_XTALONIN_HP57 SIWX91X_GPIO(10, 0xFF, 21, 3, 9, 0)
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#define COMP1_OUT_HP8 SIWX91X_GPIO(9, 5, 3, 0, 8, 2)
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#define COMP1_OUT_HP28 SIWX91X_GPIO(11, 5, 0, 1, 12, 9)
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#define COMP1_OUT_HP47 SIWX91X_GPIO(9, 5, 11, 2, 15, 9)
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#define COMP1_OUT_ULP2 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 2)
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#define COMP1_OUT_ULP6 SIWX91X_GPIO(0xFF, 9, 0xFF, 4, 0, 6)
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#define COMP2_OUT_ULP7 SIWX91X_GPIO(0xFF, 9, 0xFF, 4, 0, 7)
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#define GSPI_CLK_HP8 SIWX91X_GPIO(4, 0xFF, 3, 0, 8, 0)
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#define GSPI_CLK_HP25 SIWX91X_GPIO(4, 0xFF, 0, 1, 9, 0)
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#define GSPI_CLK_HP46 SIWX91X_GPIO(4, 0xFF, 10, 2, 14, 0)
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#define GSPI_CLK_HP52 SIWX91X_GPIO(4, 0xFF, 16, 3, 4, 0)
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#define GSPI_CS0_HP9 SIWX91X_GPIO(4, 0xFF, 4, 0, 9, 0)
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#define GSPI_CS0_HP28 SIWX91X_GPIO(4, 0xFF, 0, 1, 12, 0)
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#define GSPI_CS0_HP49 SIWX91X_GPIO(4, 0xFF, 13, 3, 1, 0)
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#define GSPI_CS0_HP53 SIWX91X_GPIO(4, 0xFF, 17, 3, 5, 0)
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#define GSPI_CS1_HP10 SIWX91X_GPIO(4, 0xFF, 5, 0, 10, 0)
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#define GSPI_CS1_HP29 SIWX91X_GPIO(4, 0xFF, 0, 1, 13, 0)
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#define GSPI_CS1_HP50 SIWX91X_GPIO(4, 0xFF, 14, 3, 2, 0)
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#define GSPI_CS1_HP54 SIWX91X_GPIO(4, 0xFF, 18, 3, 6, 0)
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#define GSPI_CS2_HP15 SIWX91X_GPIO(4, 0xFF, 8, 0, 15, 0)
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#define GSPI_CS2_HP30 SIWX91X_GPIO(4, 0xFF, 0, 1, 14, 0)
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#define GSPI_CS2_HP51 SIWX91X_GPIO(4, 0xFF, 15, 3, 3, 0)
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#define GSPI_CS2_HP55 SIWX91X_GPIO(4, 0xFF, 19, 3, 7, 0)
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#define GSPI_MISO_HP11 SIWX91X_GPIO(4, 0xFF, 6, 0, 11, 0)
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#define GSPI_MISO_HP26 SIWX91X_GPIO(4, 0xFF, 0, 1, 10, 0)
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#define GSPI_MISO_HP47 SIWX91X_GPIO(4, 0xFF, 11, 2, 15, 0)
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#define GSPI_MISO_HP56 SIWX91X_GPIO(4, 0xFF, 20, 3, 8, 0)
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#define GSPI_MOSI_HP6 SIWX91X_GPIO(12, 0xFF, 1, 0, 6, 0)
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#define GSPI_MOSI_HP12 SIWX91X_GPIO(4, 0xFF, 7, 0, 12, 0)
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#define GSPI_MOSI_HP27 SIWX91X_GPIO(4, 0xFF, 0, 1, 11, 0)
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#define GSPI_MOSI_HP48 SIWX91X_GPIO(4, 0xFF, 12, 3, 0, 0)
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#define GSPI_MOSI_HP57 SIWX91X_GPIO(4, 0xFF, 21, 3, 9, 0)
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#define I2C0_SCL_HP7 SIWX91X_GPIO(4, 0xFF, 2, 0, 7, 0)
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#define I2C0_SCL_HP32 SIWX91X_GPIO(11, 0xFF, 9, 2, 0, 0)
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#define I2C0_SCL_ULP1 SIWX91X_GPIO(4, 6, 23, 4, 1, 1)
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#define I2C0_SCL_ULP2 SIWX91X_GPIO(4, 6, 24, 4, 2, 2)
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#define I2C0_SCL_ULP11 SIWX91X_GPIO(4, 6, 33, 4, 11, 11)
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#define I2C0_SDA_HP6 SIWX91X_GPIO(4, 0xFF, 1, 0, 6, 0)
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#define I2C0_SDA_HP31 SIWX91X_GPIO(11, 0xFF, 9, 1, 15, 0)
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#define I2C0_SDA_ULP0 SIWX91X_GPIO(4, 6, 22, 4, 0, 0)
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#define I2C0_SDA_ULP3 SIWX91X_GPIO(4, 6, 25, 4, 3, 3)
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#define I2C0_SDA_ULP10 SIWX91X_GPIO(4, 6, 32, 4, 10, 10)
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#define I2C1_SCL_HP6 SIWX91X_GPIO(5, 0xFF, 1, 0, 6, 0)
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#define I2C1_SCL_HP29 SIWX91X_GPIO(5, 0xFF, 0, 1, 13, 0)
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#define I2C1_SCL_HP33 SIWX91X_GPIO(11, 0xFF, 9, 2, 1, 0)
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#define I2C1_SCL_HP50 SIWX91X_GPIO(5, 0xFF, 14, 3, 2, 0)
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#define I2C1_SCL_HP54 SIWX91X_GPIO(5, 0xFF, 18, 3, 6, 0)
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#define I2C1_SCL_ULP0 SIWX91X_GPIO(5, 6, 22, 4, 0, 0)
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#define I2C1_SCL_ULP2 SIWX91X_GPIO(5, 6, 24, 4, 2, 2)
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#define I2C1_SCL_ULP6 SIWX91X_GPIO(5, 6, 28, 4, 6, 6)
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#define I2C1_SDA_HP7 SIWX91X_GPIO(5, 0xFF, 2, 0, 7, 0)
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#define I2C1_SDA_HP30 SIWX91X_GPIO(5, 0xFF, 0, 1, 14, 0)
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#define I2C1_SDA_HP34 SIWX91X_GPIO(11, 0xFF, 9, 2, 2, 0)
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#define I2C1_SDA_HP51 SIWX91X_GPIO(5, 0xFF, 15, 3, 3, 0)
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#define I2C1_SDA_HP55 SIWX91X_GPIO(5, 0xFF, 19, 3, 7, 0)
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#define I2C1_SDA_ULP1 SIWX91X_GPIO(5, 6, 23, 4, 1, 1)
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#define I2C1_SDA_ULP3 SIWX91X_GPIO(5, 6, 25, 4, 3, 3)
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#define I2C1_SDA_ULP7 SIWX91X_GPIO(5, 6, 29, 4, 7, 7)
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#define I2S0_CLK_HP8 SIWX91X_GPIO(7, 0xFF, 3, 0, 8, 0)
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#define I2S0_CLK_HP25 SIWX91X_GPIO(7, 0xFF, 0, 1, 9, 0)
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#define I2S0_CLK_HP46 SIWX91X_GPIO(7, 0xFF, 10, 2, 14, 0)
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#define I2S0_CLK_HP52 SIWX91X_GPIO(7, 0xFF, 16, 3, 4, 0)
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#define I2S0_DIN0_HP10 SIWX91X_GPIO(7, 0xFF, 5, 0, 10, 0)
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#define I2S0_DIN0_HP27 SIWX91X_GPIO(7, 0xFF, 0, 1, 11, 0)
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#define I2S0_DIN0_HP48 SIWX91X_GPIO(7, 0xFF, 12, 3, 0, 0)
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#define I2S0_DIN0_HP56 SIWX91X_GPIO(7, 0xFF, 20, 3, 8, 0)
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#define I2S0_DIN1_HP6 SIWX91X_GPIO(7, 0xFF, 1, 0, 6, 0)
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#define I2S0_DIN1_HP29 SIWX91X_GPIO(7, 0xFF, 0, 1, 13, 0)
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#define I2S0_DIN1_HP50 SIWX91X_GPIO(7, 0xFF, 14, 3, 2, 0)
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#define I2S0_DIN1_HP54 SIWX91X_GPIO(7, 0xFF, 18, 3, 6, 0)
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#define I2S0_DOUT0_HP11 SIWX91X_GPIO(7, 0xFF, 6, 0, 11, 0)
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#define I2S0_DOUT0_HP28 SIWX91X_GPIO(7, 0xFF, 0, 1, 12, 0)
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#define I2S0_DOUT0_HP49 SIWX91X_GPIO(7, 0xFF, 13, 3, 1, 0)
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#define I2S0_DOUT0_HP57 SIWX91X_GPIO(7, 0xFF, 21, 3, 9, 0)
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#define I2S0_DOUT1_HP7 SIWX91X_GPIO(7, 0xFF, 2, 0, 7, 0)
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#define I2S0_DOUT1_HP29 SIWX91X_GPIO(7, 0xFF, 0, 1, 14, 0)
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#define I2S0_DOUT1_HP51 SIWX91X_GPIO(7, 0xFF, 15, 3, 3, 0)
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#define I2S0_DOUT1_HP55 SIWX91X_GPIO(7, 0xFF, 19, 3, 7, 0)
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#define I2S0_WS_HP9 SIWX91X_GPIO(7, 0xFF, 4, 0, 9, 0)
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#define I2S0_WS_HP26 SIWX91X_GPIO(7, 0xFF, 0, 1, 10, 0)
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#define I2S0_WS_HP47 SIWX91X_GPIO(7, 0xFF, 11, 2, 15, 0)
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#define I2S0_WS_HP53 SIWX91X_GPIO(7, 0xFF, 17, 3, 5, 0)
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#define IR_INPUT_HP15 SIWX91X_GPIO(9, 1, 8, 0, 15, 7)
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#define IR_INPUT_HP26 SIWX91X_GPIO(11, 1, 0, 1, 10, 7)
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#define IR_INPUT_HP29 SIWX91X_GPIO(11, 4, 0, 1, 13, 10)
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#define IR_INPUT_HP48 SIWX91X_GPIO(9, 4, 12, 3, 0, 10)
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#define IR_INPUT_ULP4 SIWX91X_GPIO(0xFF, 10, 0xFF, 4, 0, 4)
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#define IR_INPUT_ULP7 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 7)
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#define IR_INPUT_ULP10 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 10)
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#define IR_OUTPUT_HP11 SIWX91X_GPIO(9, 1, 6, 0, 11, 5)
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#define IR_OUTPUT_ULP5 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 5)
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#define PMU_TEST1_HP6 SIWX91X_GPIO(8, 0xFF, 1, 0, 6, 0)
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#define PMU_TEST1_HP29 SIWX91X_GPIO(8, 0xFF, 0, 1, 13, 0)
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#define PMU_TEST1_HP30 SIWX91X_GPIO(12, 0xFF, 0, 1, 14, 0)
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#define PMU_TEST1_ULP0 SIWX91X_GPIO(13, 6, 22, 4, 0, 0)
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#define PMU_TEST1_ULP2 SIWX91X_GPIO(10, 6, 24, 4, 2, 2)
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#define PMU_TEST1_ULP6 SIWX91X_GPIO(12, 6, 28, 4, 6, 6)
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#define PMU_TEST1_ULP10 SIWX91X_GPIO(10, 6, 32, 4, 10, 10)
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#define PMU_TEST2_HP7 SIWX91X_GPIO(8, 0xFF, 2, 0, 7, 0)
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#define PMU_TEST2_HP30 SIWX91X_GPIO(8, 0xFF, 0, 1, 14, 0)
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#define PMU_TEST2_ULP1 SIWX91X_GPIO(13, 6, 23, 4, 1, 1)
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#define PMU_TEST2_ULP3 SIWX91X_GPIO(10, 6, 25, 4, 3, 3)
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#define PMU_TEST2_ULP7 SIWX91X_GPIO(12, 6, 29, 4, 7, 7)
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#define PMU_TEST2_ULP11 SIWX91X_GPIO(10, 6, 33, 4, 11, 11)
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#define PSRAM_CLK_HP46 SIWX91X_GPIO(11, 0xFF, 10, 2, 14, 0)
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#define PSRAM_CLK_HP52 SIWX91X_GPIO(12, 0xFF, 16, 3, 4, 0)
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#define PSRAM_CSN0_HP49 SIWX91X_GPIO(11, 0xFF, 13, 3, 1, 0)
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#define PSRAM_CSN0_HP55 SIWX91X_GPIO(12, 0xFF, 19, 3, 7, 0)
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#define PSRAM_CSN1_HP53 SIWX91X_GPIO(11, 0xFF, 17, 3, 5, 0)
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#define PSRAM_D0_HP47 SIWX91X_GPIO(11, 0xFF, 11, 2, 15, 0)
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#define PSRAM_D0_HP53 SIWX91X_GPIO(12, 0xFF, 17, 3, 5, 0)
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#define PSRAM_D1_HP48 SIWX91X_GPIO(11, 0xFF, 12, 3, 0, 0)
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#define PSRAM_D1_HP54 SIWX91X_GPIO(12, 0xFF, 18, 3, 6, 0)
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#define PSRAM_D2_HP50 SIWX91X_GPIO(11, 0xFF, 14, 3, 2, 0)
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#define PSRAM_D2_HP56 SIWX91X_GPIO(12, 0xFF, 20, 3, 8, 0)
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#define PSRAM_D3_HP51 SIWX91X_GPIO(11, 0xFF, 15, 3, 3, 0)
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#define PSRAM_D3_HP57 SIWX91X_GPIO(12, 0xFF, 21, 3, 9, 0)
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#define PSRAM_D4_HP54 SIWX91X_GPIO(11, 0xFF, 18, 3, 6, 0)
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#define PSRAM_D5_HP55 SIWX91X_GPIO(11, 0xFF, 19, 3, 7, 0)
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#define PSRAM_D6_HP56 SIWX91X_GPIO(11, 0xFF, 20, 3, 8, 0)
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#define PSRAM_D7_HP57 SIWX91X_GPIO(11, 0xFF, 21, 3, 9, 0)
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#define PWM_0H_HP7 SIWX91X_GPIO(10, 0xFF, 2, 0, 7, 0)
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#define PWM_0H_ULP1 SIWX91X_GPIO(12, 6, 23, 4, 1, 1)
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#define PWM_0L_HP6 SIWX91X_GPIO(10, 0xFF, 1, 0, 6, 0)
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#define PWM_0L_ULP0 SIWX91X_GPIO(12, 6, 22, 4, 0, 0)
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#define PWM_1H_HP9 SIWX91X_GPIO(10, 0xFF, 4, 0, 9, 0)
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#define PWM_1H_ULP3 SIWX91X_GPIO(8, 6, 25, 4, 3, 3)
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#define PWM_1H_ULP5 SIWX91X_GPIO(12, 6, 27, 4, 5, 5)
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#define PWM_1L_HP8 SIWX91X_GPIO(10, 0xFF, 3, 0, 8, 0)
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#define PWM_1L_ULP2 SIWX91X_GPIO(8, 6, 24, 4, 2, 2)
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#define PWM_1L_ULP4 SIWX91X_GPIO(12, 6, 26, 4, 4, 4)
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#define PWM_2H_HP11 SIWX91X_GPIO(10, 0xFF, 6, 0, 11, 0)
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#define PWM_2H_ULP5 SIWX91X_GPIO(8, 6, 27, 4, 5, 5)
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#define PWM_2L_HP10 SIWX91X_GPIO(10, 0xFF, 5, 0, 10, 0)
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#define PWM_2L_ULP4 SIWX91X_GPIO(8, 6, 26, 4, 4, 4)
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#define PWM_3H_HP15 SIWX91X_GPIO(10, 0xFF, 8, 0, 15, 0)
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#define PWM_3H_ULP7 SIWX91X_GPIO(8, 6, 29, 4, 7, 7)
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#define PWM_3L_HP12 SIWX91X_GPIO(10, 0xFF, 7, 0, 12, 0)
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#define PWM_3L_ULP6 SIWX91X_GPIO(8, 6, 28, 4, 6, 6)
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#define PWM_EXTTRIG0_HP27 SIWX91X_GPIO(10, 0xFF, 0, 1, 11, 0)
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#define PWM_EXTTRIG0_HP51 SIWX91X_GPIO(8, 0xFF, 15, 3, 3, 0)
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#define PWM_EXTTRIG0_ULP6 SIWX91X_GPIO(10, 6, 28, 4, 6, 6)
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#define PWM_EXTTRIG0_ULP11 SIWX91X_GPIO(8, 6, 33, 4, 11, 11)
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#define PWM_EXTTRIG1_HP28 SIWX91X_GPIO(10, 0xFF, 0, 1, 12, 0)
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#define PWM_EXTTRIG1_HP54 SIWX91X_GPIO(8, 0xFF, 18, 3, 6, 0)
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#define PWM_EXTTRIG1_ULP7 SIWX91X_GPIO(10, 6, 29, 4, 7, 7)
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#define PWM_EXTTRIG2_HP29 SIWX91X_GPIO(10, 0xFF, 0, 1, 13, 0)
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#define PWM_EXTTRIG2_HP55 SIWX91X_GPIO(8, 0xFF, 19, 3, 7, 0)
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#define PWM_EXTTRIG2_ULP8 SIWX91X_GPIO(10, 6, 30, 4, 8, 8)
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#define PWM_EXTTRIG3_HP30 SIWX91X_GPIO(10, 0xFF, 0, 1, 14, 0)
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#define PWM_EXTTRIG3_HP50 SIWX91X_GPIO(8, 0xFF, 14, 3, 2, 0)
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#define PWM_EXTTRIG3_ULP9 SIWX91X_GPIO(10, 6, 31, 4, 9, 9)
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#define PWM_FAULTA_HP25 SIWX91X_GPIO(10, 0xFF, 0, 1, 9, 0)
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#define PWM_FAULTA_ULP4 SIWX91X_GPIO(10, 6, 26, 4, 4, 4)
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#define PWM_FAULTA_ULP9 SIWX91X_GPIO(8, 6, 31, 4, 9, 9)
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#define PWM_FAULTB_HP26 SIWX91X_GPIO(10, 0xFF, 0, 1, 10, 0)
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#define PWM_FAULTB_ULP5 SIWX91X_GPIO(10, 6, 27, 4, 5, 5)
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#define PWM_FAULTB_ULP10 SIWX91X_GPIO(8, 6, 32, 4, 10, 10)
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#define PWM_SLEEPEVENT_ULP8 SIWX91X_GPIO(8, 6, 30, 4, 8, 8)
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#define QEI_DIR_HP11 SIWX91X_GPIO(5, 0xFF, 6, 0, 11, 0)
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#define QEI_DIR_HP28 SIWX91X_GPIO(5, 0xFF, 0, 1, 12, 0)
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#define QEI_DIR_HP34 SIWX91X_GPIO(13, 0xFF, 9, 2, 2, 0)
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#define QEI_DIR_HP49 SIWX91X_GPIO(3, 0xFF, 13, 3, 1, 0)
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#define QEI_DIR_HP57 SIWX91X_GPIO(5, 0xFF, 21, 3, 9, 0)
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#define QEI_DIR_ULP3 SIWX91X_GPIO(3, 6, 25, 4, 3, 3)
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#define QEI_DIR_ULP7 SIWX91X_GPIO(3, 6, 29, 4, 7, 7)
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#define QEI_DIR_ULP11 SIWX91X_GPIO(3, 6, 33, 4, 11, 11)
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#define QEI_IDX_HP8 SIWX91X_GPIO(5, 0xFF, 3, 0, 8, 0)
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#define QEI_IDX_HP31 SIWX91X_GPIO(13, 0xFF, 9, 1, 15, 0)
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#define QEI_IDX_HP25 SIWX91X_GPIO(5, 0xFF, 0, 1, 9, 0)
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#define QEI_IDX_HP46 SIWX91X_GPIO(3, 0xFF, 10, 2, 14, 0)
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#define QEI_IDX_HP52 SIWX91X_GPIO(5, 0xFF, 16, 3, 4, 0)
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#define QEI_IDX_ULP0 SIWX91X_GPIO(3, 6, 22, 4, 0, 0)
280
#define QEI_IDX_ULP4 SIWX91X_GPIO(3, 6, 26, 4, 4, 4)
281
#define QEI_IDX_ULP8 SIWX91X_GPIO(3, 6, 30, 4, 8, 8)
282
#define QEI_PHA_HP9 SIWX91X_GPIO(5, 0xFF, 4, 0, 9, 0)
283
#define QEI_PHA_HP26 SIWX91X_GPIO(5, 0xFF, 0, 1, 10, 0)
284
#define QEI_PHA_HP32 SIWX91X_GPIO(13, 0xFF, 9, 2, 0, 0)
285
#define QEI_PHA_HP47 SIWX91X_GPIO(3, 0xFF, 11, 2, 15, 0)
286
#define QEI_PHA_HP53 SIWX91X_GPIO(5, 0xFF, 17, 3, 5, 0)
287
#define QEI_PHA_ULP1 SIWX91X_GPIO(3, 6, 23, 4, 1, 1)
288
#define QEI_PHA_ULP5 SIWX91X_GPIO(3, 6, 27, 4, 5, 5)
289
#define QEI_PHA_ULP9 SIWX91X_GPIO(3, 6, 31, 4, 9, 9)
290
#define QEI_PHB_HP10 SIWX91X_GPIO(5, 0xFF, 5, 0, 10, 0)
291
#define QEI_PHB_HP27 SIWX91X_GPIO(5, 0xFF, 0, 1, 11, 0)
292
#define QEI_PHB_HP33 SIWX91X_GPIO(13, 0xFF, 9, 2, 1, 0)
293
#define QEI_PHB_HP48 SIWX91X_GPIO(3, 0xFF, 12, 3, 0, 0)
294
#define QEI_PHB_HP56 SIWX91X_GPIO(5, 0xFF, 20, 3, 8, 0)
295
#define QEI_PHB_ULP2 SIWX91X_GPIO(3, 6, 24, 4, 2, 2)
296
#define QEI_PHB_ULP6 SIWX91X_GPIO(3, 6, 28, 4, 6, 6)
297
#define QEI_PHB_ULP10 SIWX91X_GPIO(3, 6, 32, 4, 10, 10)
298
299
#define QSPI_CLK_HP8 SIWX91X_GPIO(11, 0xFF, 3, 0, 8, 0)
300
#define QSPI_CLK_HP46 SIWX91X_GPIO(1, 0xFF, 10, 2, 14, 0)
301
#define QSPI_CLK_HP52 SIWX91X_GPIO(9, 0xFF, 16, 3, 4, 0)
302
#define QSPI_CSN0_HP7 SIWX91X_GPIO(11, 0xFF, 2, 0, 7, 0)
303
#define QSPI_CSN0_HP49 SIWX91X_GPIO(1, 0xFF, 13, 3, 1, 0)
304
#define QSPI_CSN0_HP55 SIWX91X_GPIO(9, 0xFF, 19, 3, 7, 0)
305
#define QSPI_CSN1_HP7 SIWX91X_GPIO(12, 0xFF, 2, 0, 7, 0)
306
#define QSPI_CSN1_HP53 SIWX91X_GPIO(1, 0xFF, 17, 3, 5, 0)
307
#define QSPI_CSN9_HP49 SIWX91X_GPIO(10, 0xFF, 13, 3, 1, 0)
308
#define QSPI_D0_HP6 SIWX91X_GPIO(11, 0xFF, 1, 0, 6, 0)
309
#define QSPI_D0_HP47 SIWX91X_GPIO(1, 0xFF, 11, 2, 15, 0)
310
#define QSPI_D0_HP53 SIWX91X_GPIO(9, 0xFF, 17, 3, 5, 0)
311
#define QSPI_D1_HP9 SIWX91X_GPIO(11, 0xFF, 4, 0, 9, 0)
312
#define QSPI_D1_HP48 SIWX91X_GPIO(1, 0xFF, 12, 3, 0, 0)
313
#define QSPI_D1_HP54 SIWX91X_GPIO(9, 0xFF, 18, 3, 6, 0)
314
#define QSPI_D2_HP10 SIWX91X_GPIO(11, 0xFF, 5, 0, 10, 0)
315
#define QSPI_D2_HP50 SIWX91X_GPIO(1, 0xFF, 14, 3, 2, 0)
316
#define QSPI_D2_HP56 SIWX91X_GPIO(9, 0xFF, 20, 3, 8, 0)
317
#define QSPI_D3_HP11 SIWX91X_GPIO(11, 0xFF, 6, 0, 11, 0)
318
#define QSPI_D3_HP51 SIWX91X_GPIO(1, 0xFF, 15, 3, 3, 0)
319
#define QSPI_D3_HP57 SIWX91X_GPIO(9, 0xFF, 21, 3, 9, 0)
320
#define QSPI_D4_HP54 SIWX91X_GPIO(1, 0xFF, 18, 3, 6, 0)
321
#define QSPI_D5_HP55 SIWX91X_GPIO(1, 0xFF, 19, 3, 7, 0)
322
#define QSPI_D6_HP56 SIWX91X_GPIO(1, 0xFF, 20, 3, 8, 0)
323
#define QSPI_D7_HP57 SIWX91X_GPIO(1, 0xFF, 21, 3, 9, 0)
324
325
#define SCT_IN0_HP25 SIWX91X_GPIO(9, 0xFF, 0, 1, 9, 0)
326
#define SCT_IN0_ULP0 SIWX91X_GPIO(7, 6, 22, 4, 0, 0)
327
#define SCT_IN0_ULP4 SIWX91X_GPIO(9, 6, 26, 4, 4, 4)
328
#define SCT_IN1_HP26 SIWX91X_GPIO(9, 0xFF, 0, 1, 10, 0)
329
#define SCT_IN1_ULP1 SIWX91X_GPIO(7, 6, 23, 4, 1, 1)
330
#define SCT_IN1_ULP5 SIWX91X_GPIO(9, 6, 27, 4, 5, 5)
331
#define SCT_IN2_HP27 SIWX91X_GPIO(9, 0xFF, 0, 1, 11, 0)
332
#define SCT_IN2_ULP2 SIWX91X_GPIO(7, 6, 24, 4, 2, 2)
333
#define SCT_IN2_ULP6 SIWX91X_GPIO(9, 6, 28, 4, 6, 6)
334
#define SCT_IN3_HP28 SIWX91X_GPIO(9, 0xFF, 0, 1, 12, 0)
335
#define SCT_IN3_ULP3 SIWX91X_GPIO(7, 6, 25, 4, 3, 3)
336
#define SCT_IN3_ULP7 SIWX91X_GPIO(9, 6, 29, 4, 7, 7)
337
#define SCT_OUT0_HP29 SIWX91X_GPIO(9, 0xFF, 0, 1, 13, 0)
338
#define SCT_OUT0_ULP4 SIWX91X_GPIO(7, 6, 26, 4, 4, 4)
339
#define SCT_OUT1_HP30 SIWX91X_GPIO(9, 0xFF, 0, 1, 14, 0)
340
#define SCT_OUT1_ULP5 SIWX91X_GPIO(7, 6, 27, 4, 5, 5)
341
#define SCT_OUT2_HP8 SIWX91X_GPIO(12, 0xFF, 3, 0, 8, 0)
342
#define SCT_OUT2_ULP6 SIWX91X_GPIO(7, 6, 28, 4, 6, 6)
343
#define SCT_OUT3_HP9 SIWX91X_GPIO(12, 0xFF, 4, 0, 9, 0)
344
#define SCT_OUT3_ULP7 SIWX91X_GPIO(7, 6, 29, 4, 7, 7)
345
#define SCT_OUT4_ULP4 SIWX91X_GPIO(13, 6, 26, 4, 4, 4)
346
#define SCT_OUT4_ULP8 SIWX91X_GPIO(7, 6, 30, 4, 8, 8)
347
#define SCT_OUT5_ULP5 SIWX91X_GPIO(13, 6, 27, 4, 5, 5)
348
#define SCT_OUT5_ULP9 SIWX91X_GPIO(7, 6, 31, 4, 9, 9)
349
#define SCT_OUT6_ULP6 SIWX91X_GPIO(13, 6, 28, 4, 6, 6)
350
#define SCT_OUT6_ULP10 SIWX91X_GPIO(7, 6, 32, 4, 10, 10)
351
#define SCT_OUT7_ULP7 SIWX91X_GPIO(13, 6, 29, 4, 7, 7)
352
#define SCT_OUT7_ULP11 SIWX91X_GPIO(7, 6, 33, 4, 11, 11)
353
354
#define SIO_0_HP6 SIWX91X_GPIO(1, 0xFF, 1, 0, 6, 0)
355
#define SIO_0_HP25 SIWX91X_GPIO(1, 0xFF, 0, 1, 9, 0)
356
#define SIO_0_ULP0 SIWX91X_GPIO(1, 6, 22, 4, 0, 0)
357
#define SIO_0_ULP8 SIWX91X_GPIO(1, 6, 30, 4, 8, 8)
358
#define SIO_1_HP7 SIWX91X_GPIO(1, 0xFF, 2, 0, 7, 0)
359
#define SIO_1_HP26 SIWX91X_GPIO(1, 0xFF, 0, 1, 10, 0)
360
#define SIO_1_ULP1 SIWX91X_GPIO(1, 6, 23, 4, 1, 1)
361
#define SIO_1_ULP9 SIWX91X_GPIO(1, 6, 31, 4, 9, 9)
362
#define SIO_2_HP8 SIWX91X_GPIO(1, 0xFF, 3, 0, 8, 0)
363
#define SIO_2_HP27 SIWX91X_GPIO(1, 0xFF, 0, 1, 11, 0)
364
#define SIO_2_ULP2 SIWX91X_GPIO(1, 6, 24, 4, 2, 2)
365
#define SIO_2_ULP10 SIWX91X_GPIO(1, 6, 32, 4, 10, 10)
366
#define SIO_3_HP9 SIWX91X_GPIO(1, 0xFF, 4, 0, 9, 0)
367
#define SIO_3_HP28 SIWX91X_GPIO(1, 0xFF, 0, 1, 12, 0)
368
#define SIO_3_ULP3 SIWX91X_GPIO(1, 6, 25, 4, 3, 3)
369
#define SIO_3_ULP11 SIWX91X_GPIO(1, 6, 33, 4, 11, 11)
370
#define SIO_4_HP10 SIWX91X_GPIO(1, 0xFF, 5, 0, 10, 0)
371
#define SIO_4_HP29 SIWX91X_GPIO(1, 0xFF, 0, 1, 13, 0)
372
#define SIO_4_ULP4 SIWX91X_GPIO(1, 6, 26, 4, 4, 4)
373
#define SIO_5_HP11 SIWX91X_GPIO(1, 0xFF, 6, 0, 11, 0)
374
#define SIO_5_HP30 SIWX91X_GPIO(1, 0xFF, 0, 1, 14, 0)
375
#define SIO_5_ULP5 SIWX91X_GPIO(1, 6, 27, 4, 5, 5)
376
#define SIO_6_ULP6 SIWX91X_GPIO(1, 6, 28, 4, 6, 6)
377
#define SIO_7_HP15 SIWX91X_GPIO(1, 0xFF, 8, 0, 15, 0)
378
#define SIO_7_ULP7 SIWX91X_GPIO(1, 6, 29, 4, 7, 7)
379
380
#define SSI_CLK_HP8 SIWX91X_GPIO(3, 0xFF, 3, 0, 8, 0)
381
#define SSI_CLK_HP25 SIWX91X_GPIO(3, 0xFF, 0, 1, 9, 0)
382
#define SSI_CLK_HP52 SIWX91X_GPIO(3, 0xFF, 16, 3, 4, 0)
383
#define SSI_CS0_HP9 SIWX91X_GPIO(3, 0xFF, 4, 0, 9, 0)
384
#define SSI_CS0_HP28 SIWX91X_GPIO(3, 0xFF, 0, 1, 12, 0)
385
#define SSI_CS0_HP53 SIWX91X_GPIO(3, 0xFF, 17, 3, 5, 0)
386
#define SSI_CS1_HP10 SIWX91X_GPIO(3, 0xFF, 5, 0, 10, 0)
387
#define SSI_CS2_HP15 SIWX91X_GPIO(3, 0xFF, 8, 0, 15, 0)
388
#define SSI_CS2_HP50 SIWX91X_GPIO(3, 0xFF, 14, 3, 2, 0)
389
#define SSI_CS3_HP51 SIWX91X_GPIO(3, 0xFF, 15, 3, 3, 0)
390
#define SSI_DATA0_HP11 SIWX91X_GPIO(3, 0xFF, 6, 0, 11, 0)
391
#define SSI_DATA0_HP26 SIWX91X_GPIO(3, 0xFF, 0, 1, 10, 0)
392
#define SSI_DATA0_HP56 SIWX91X_GPIO(3, 0xFF, 20, 3, 8, 0)
393
#define SSI_DATA1_HP10 SIWX91X_GPIO(12, 0xFF, 5, 0, 10, 0)
394
#define SSI_DATA1_HP12 SIWX91X_GPIO(3, 0xFF, 7, 0, 12, 0)
395
#define SSI_DATA1_HP27 SIWX91X_GPIO(3, 0xFF, 0, 1, 11, 0)
396
#define SSI_DATA1_HP57 SIWX91X_GPIO(3, 0xFF, 21, 3, 9, 0)
397
#define SSI_DATA2_HP6 SIWX91X_GPIO(3, 0xFF, 1, 0, 6, 0)
398
#define SSI_DATA2_HP29 SIWX91X_GPIO(3, 0xFF, 0, 1, 13, 0)
399
#define SSI_DATA2_HP54 SIWX91X_GPIO(3, 0xFF, 18, 3, 6, 0)
400
#define SSI_DATA3_HP7 SIWX91X_GPIO(3, 0xFF, 2, 0, 7, 0)
401
#define SSI_DATA3_HP30 SIWX91X_GPIO(3, 0xFF, 0, 1, 14, 0)
402
#define SSI_DATA3_HP55 SIWX91X_GPIO(3, 0xFF, 19, 3, 7, 0)
403
404
#define SSIS_CLK_HP8 SIWX91X_GPIO(8, 0xFF, 3, 0, 8, 0)
405
#define SSIS_CLK_HP26 SIWX91X_GPIO(8, 0xFF, 0, 1, 10, 0)
406
#define SSIS_CLK_HP47 SIWX91X_GPIO(8, 0xFF, 11, 2, 15, 0)
407
#define SSIS_CLK_HP52 SIWX91X_GPIO(8, 0xFF, 16, 3, 4, 0)
408
#define SSIS_CS_HP9 SIWX91X_GPIO(8, 0xFF, 4, 0, 9, 0)
409
#define SSIS_CS_HP25 SIWX91X_GPIO(8, 0xFF, 0, 1, 9, 0)
410
#define SSIS_CS_HP46 SIWX91X_GPIO(8, 0xFF, 10, 2, 14, 0)
411
#define SSIS_CS_HP53 SIWX91X_GPIO(8, 0xFF, 17, 3, 5, 0)
412
#define SSIS_MISO_HP11 SIWX91X_GPIO(8, 0xFF, 6, 0, 11, 0)
413
#define SSIS_MISO_HP28 SIWX91X_GPIO(8, 0xFF, 0, 1, 12, 0)
414
#define SSIS_MISO_HP49 SIWX91X_GPIO(8, 0xFF, 13, 3, 1, 0)
415
#define SSIS_MISO_HP57 SIWX91X_GPIO(8, 0xFF, 21, 3, 9, 0)
416
#define SSIS_MOSI_HP10 SIWX91X_GPIO(8, 0xFF, 5, 0, 10, 0)
417
#define SSIS_MOSI_HP27 SIWX91X_GPIO(8, 0xFF, 0, 1, 11, 0)
418
#define SSIS_MOSI_HP48 SIWX91X_GPIO(8, 0xFF, 12, 3, 0, 0)
419
#define SSIS_MOSI_HP56 SIWX91X_GPIO(8, 0xFF, 20, 3, 8, 0)
420
421
#define TIMER0_HP7 SIWX91X_GPIO(9, 5, 2, 0, 7, 1)
422
#define TIMER0_HP27 SIWX91X_GPIO(11, 5, 0, 1, 11, 8)
423
#define TIMER0_HP46 SIWX91X_GPIO(9, 5, 10, 2, 14, 8)
424
#define TIMER0_ULP4 SIWX91X_GPIO(0xFF, 9, 0xFF, 4, 0, 4)
425
#define TIMER0_ULP8 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 8)
426
427
#define TIMER1_HP15 SIWX91X_GPIO(9, 5, 8, 0, 15, 7)
428
#define TIMER1_HP26 SIWX91X_GPIO(11, 5, 0, 1, 10, 7)
429
#define TIMER1_ULP5 SIWX91X_GPIO(0xFF, 9, 0xFF, 4, 0, 5)
430
#define TIMER1_ULP7 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 7)
431
432
#define TIMER2_ULP1 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 1)
433
434
#define TRACE_CLK_HP7 SIWX91X_GPIO(13, 0xFF, 2, 0, 7, 0)
435
#define TRACE_CLK_HP47 SIWX91X_GPIO(6, 0xFF, 11, 2, 15, 0)
436
#define TRACE_CLK_HP53 SIWX91X_GPIO(6, 0xFF, 17, 3, 5, 0)
437
#define TRACE_CLKIN_HP6 SIWX91X_GPIO(13, 0xFF, 1, 0, 6, 0)
438
#define TRACE_CLKIN_HP15 SIWX91X_GPIO(6, 0xFF, 8, 0, 15, 0)
439
#define TRACE_CLKIN_HP46 SIWX91X_GPIO(6, 0xFF, 10, 2, 14, 0)
440
#define TRACE_CLKIN_HP52 SIWX91X_GPIO(6, 0xFF, 16, 3, 4, 0)
441
#define TRACE_D0_HP8 SIWX91X_GPIO(13, 0xFF, 3, 0, 8, 0)
442
#define TRACE_D0_HP48 SIWX91X_GPIO(6, 0xFF, 12, 3, 0, 0)
443
#define TRACE_D0_HP54 SIWX91X_GPIO(6, 0xFF, 18, 3, 6, 0)
444
#define TRACE_D1_HP9 SIWX91X_GPIO(13, 0xFF, 4, 0, 9, 0)
445
#define TRACE_D1_HP49 SIWX91X_GPIO(6, 0xFF, 13, 3, 1, 0)
446
#define TRACE_D1_HP55 SIWX91X_GPIO(6, 0xFF, 19, 3, 7, 0)
447
#define TRACE_D2_HP10 SIWX91X_GPIO(13, 0xFF, 5, 0, 10, 0)
448
#define TRACE_D2_HP50 SIWX91X_GPIO(6, 0xFF, 14, 3, 2, 0)
449
#define TRACE_D2_HP56 SIWX91X_GPIO(6, 0xFF, 20, 3, 8, 0)
450
#define TRACE_D3_HP11 SIWX91X_GPIO(13, 0xFF, 6, 0, 11, 0)
451
#define TRACE_D3_HP51 SIWX91X_GPIO(6, 0xFF, 15, 3, 3, 0)
452
#define TRACE_D3_HP57 SIWX91X_GPIO(6, 0xFF, 21, 3, 9, 0)
453
454
#define UART0_CLK_HP8 SIWX91X_GPIO(2, 0xFF, 3, 0, 8, 0)
455
#define UART0_CLK_HP25 SIWX91X_GPIO(2, 0xFF, 0, 1, 9, 0)
456
#define UART0_CLK_HP52 SIWX91X_GPIO(2, 0xFF, 16, 3, 4, 0)
457
#define UART0_CLK_ULP0 SIWX91X_GPIO(2, 6, 22, 4, 0, 0)
458
#define UART0_CTS_HP6 SIWX91X_GPIO(2, 0xFF, 1, 0, 6, 0)
459
#define UART0_CTS_HP26 SIWX91X_GPIO(2, 0xFF, 0, 1, 10, 0)
460
#define UART0_CTS_HP56 SIWX91X_GPIO(2, 0xFF, 20, 3, 8, 0)
461
#define UART0_CTS_ULP6 SIWX91X_GPIO(2, 6, 28, 4, 6, 6)
462
#define UART0_DCD_HP12 SIWX91X_GPIO(2, 0xFF, 7, 0, 12, 0)
463
#define UART0_DCD_HP29 SIWX91X_GPIO(12, 0xFF, 0, 1, 13, 0)
464
#define UART0_DSR_HP11 SIWX91X_GPIO(2, 0xFF, 6, 0, 11, 0)
465
#define UART0_DSR_HP57 SIWX91X_GPIO(2, 0xFF, 21, 3, 9, 0)
466
#define UART0_DTR_HP7 SIWX91X_GPIO(2, 0xFF, 2, 0, 7, 0)
467
#define UART0_IRRX_HP25 SIWX91X_GPIO(13, 0xFF, 0, 1, 9, 0)
468
#define UART0_IRRX_HP47 SIWX91X_GPIO(2, 0xFF, 11, 2, 15, 0)
469
#define UART0_IRRX_ULP0 SIWX91X_GPIO(11, 6, 22, 4, 0, 0)
470
#define UART0_IRRX_ULP7 SIWX91X_GPIO(2, 6, 29, 4, 7, 7)
471
#define UART0_IRTX_HP26 SIWX91X_GPIO(13, 0xFF, 0, 1, 10, 0)
472
#define UART0_IRTX_HP48 SIWX91X_GPIO(2, 0xFF, 12, 3, 0, 0)
473
#define UART0_IRTX_ULP1 SIWX91X_GPIO(11, 6, 23, 4, 1, 1)
474
#define UART0_IRTX_ULP8 SIWX91X_GPIO(2, 6, 30, 4, 8, 8)
475
#define UART0_RI_HP27 SIWX91X_GPIO(2, 0xFF, 0, 1, 11, 0)
476
#define UART0_RI_HP46 SIWX91X_GPIO(2, 0xFF, 10, 2, 14, 0)
477
#define UART0_RI_ULP4 SIWX91X_GPIO(11, 6, 26, 4, 4, 4)
478
#define UART0_RS485DE_HP29 SIWX91X_GPIO(13, 0xFF, 0, 1, 13, 0)
479
#define UART0_RS485DE_HP51 SIWX91X_GPIO(2, 0xFF, 15, 3, 3, 0)
480
#define UART0_RS485DE_ULP7 SIWX91X_GPIO(11, 6, 29, 4, 7, 7)
481
#define UART0_RS485DE_ULP11 SIWX91X_GPIO(2, 6, 33, 4, 11, 11)
482
#define UART0_RS485EN_HP27 SIWX91X_GPIO(13, 0xFF, 0, 1, 11, 0)
483
#define UART0_RS485EN_HP49 SIWX91X_GPIO(2, 0xFF, 13, 3, 1, 0)
484
#define UART0_RS485EN_ULP5 SIWX91X_GPIO(11, 6, 27, 4, 5, 5)
485
#define UART0_RS485EN_ULP9 SIWX91X_GPIO(2, 6, 31, 4, 9, 9)
486
#define UART0_RS485RE_HP28 SIWX91X_GPIO(13, 0xFF, 0, 1, 12, 0)
487
#define UART0_RS485RE_HP50 SIWX91X_GPIO(2, 0xFF, 14, 3, 2, 0)
488
#define UART0_RS485RE_ULP6 SIWX91X_GPIO(11, 6, 28, 4, 6, 6)
489
#define UART0_RS485RE_ULP10 SIWX91X_GPIO(2, 6, 32, 4, 10, 10)
490
#define UART0_RTS_HP9 SIWX91X_GPIO(2, 0xFF, 4, 0, 9, 0)
491
#define UART0_RTS_HP28 SIWX91X_GPIO(2, 0xFF, 0, 1, 12, 0)
492
#define UART0_RTS_HP53 SIWX91X_GPIO(2, 0xFF, 17, 3, 5, 0)
493
#define UART0_RTS_ULP5 SIWX91X_GPIO(2, 6, 27, 4, 5, 5)
494
#define UART0_RX_HP10 SIWX91X_GPIO(2, 0xFF, 5, 0, 10, 0)
495
#define UART0_RX_HP29 SIWX91X_GPIO(2, 0xFF, 0, 1, 13, 0)
496
#define UART0_RX_HP55 SIWX91X_GPIO(2, 0xFF, 19, 3, 7, 0)
497
#define UART0_RX_ULP1 SIWX91X_GPIO(2, 6, 23, 4, 1, 1)
498
#define UART0_RX_ULP6 SIWX91X_GPIO(4, 6, 28, 4, 6, 6)
499
#define UART0_TX_HP30 SIWX91X_GPIO(2, 0xFF, 0, 1, 14, 0)
500
#define UART0_TX_HP54 SIWX91X_GPIO(2, 0xFF, 18, 3, 6, 0)
501
#define UART0_TX_ULP4 SIWX91X_GPIO(2, 6, 26, 4, 4, 4)
502
#define UART0_TX_ULP7 SIWX91X_GPIO(4, 6, 29, 4, 7, 7)
503
504
#define UART1_CTS_HP11 SIWX91X_GPIO(6, 0xFF, 6, 0, 11, 0)
505
#define UART1_CTS_HP32 SIWX91X_GPIO(12, 0xFF, 9, 2, 0, 0)
506
#define UART1_CTS_HP51 SIWX91X_GPIO(9, 0xFF, 15, 3, 3, 0)
507
#define UART1_CTS_ULP1 SIWX91X_GPIO(9, 6, 23, 4, 1, 1)
508
#define UART1_CTS_ULP7 SIWX91X_GPIO(6, 6, 29, 4, 7, 7)
509
#define UART1_CTS_ULP9 SIWX91X_GPIO(9, 6, 31, 4, 9, 9)
510
#define UART1_RS485DE_HP9 SIWX91X_GPIO(6, 0xFF, 4, 0, 9, 0)
511
#define UART1_RS485DE_ULP2 SIWX91X_GPIO(6, 6, 24, 4, 2, 2)
512
#define UART1_RS485DE_ULP11 SIWX91X_GPIO(6, 6, 33, 4, 11, 11)
513
#define UART1_RS485EN_HP12 SIWX91X_GPIO(6, 0xFF, 7, 0, 12, 0)
514
#define UART1_RS485EN_HP26 SIWX91X_GPIO(6, 0xFF, 0, 1, 10, 0)
515
#define UART1_RS485EN_ULP0 SIWX91X_GPIO(6, 6, 22, 4, 0, 0)
516
#define UART1_RS485RE_HP8 SIWX91X_GPIO(6, 0xFF, 3, 0, 8, 0)
517
#define UART1_RS485RE_ULP1 SIWX91X_GPIO(6, 6, 23, 4, 1, 1)
518
#define UART1_RS485RE_ULP10 SIWX91X_GPIO(6, 6, 32, 4, 10, 10)
519
#define UART1_RTS_HP10 SIWX91X_GPIO(6, 0xFF, 5, 0, 10, 0)
520
#define UART1_RTS_HP27 SIWX91X_GPIO(6, 0xFF, 0, 1, 11, 0)
521
#define UART1_RTS_HP28 SIWX91X_GPIO(6, 0xFF, 0, 1, 12, 0)
522
#define UART1_RTS_HP31 SIWX91X_GPIO(12, 0xFF, 9, 1, 15, 0)
523
#define UART1_RTS_HP50 SIWX91X_GPIO(9, 0xFF, 14, 3, 2, 0)
524
#define UART1_RTS_ULP0 SIWX91X_GPIO(9, 6, 22, 4, 0, 0)
525
#define UART1_RTS_ULP6 SIWX91X_GPIO(6, 6, 28, 4, 6, 6)
526
#define UART1_RTS_ULP8 SIWX91X_GPIO(9, 6, 30, 4, 8, 8)
527
#define UART1_RX_HP6 SIWX91X_GPIO(6, 0xFF, 1, 0, 6, 0)
528
#define UART1_RX_HP29 SIWX91X_GPIO(6, 0xFF, 0, 1, 13, 0)
529
#define UART1_RX_HP33 SIWX91X_GPIO(12, 0xFF, 9, 2, 1, 0)
530
#define UART1_RX_ULP2 SIWX91X_GPIO(9, 6, 24, 4, 1, 1)
531
#define UART1_RX_ULP4 SIWX91X_GPIO(6, 6, 26, 4, 4, 4)
532
#define UART1_RX_ULP8 SIWX91X_GPIO(6, 6, 30, 4, 8, 8)
533
#define UART1_RX_ULP10 SIWX91X_GPIO(9, 6, 32, 4, 10, 10)
534
#define UART1_TX_HP15 SIWX91X_GPIO(2, 0xFF, 8, 0, 15, 0)
535
#define UART1_TX_HP7 SIWX91X_GPIO(6, 0xFF, 2, 0, 7, 0)
536
#define UART1_TX_HP30 SIWX91X_GPIO(6, 0xFF, 0, 1, 14, 0)
537
#define UART1_TX_HP34 SIWX91X_GPIO(12, 0xFF, 9, 2, 2, 0)
538
#define UART1_TX_ULP3 SIWX91X_GPIO(9, 6, 25, 4, 1, 1)
539
#define UART1_TX_ULP5 SIWX91X_GPIO(6, 6, 27, 4, 5, 5)
540
#define UART1_TX_ULP9 SIWX91X_GPIO(6, 6, 31, 4, 9, 9)
541
#define UART1_TX_ULP11 SIWX91X_GPIO(9, 6, 33, 4, 11, 11)
542
543
#define ULPI2C_SCL_HP11 SIWX91X_GPIO(9, 4, 6, 0, 11, 5)
544
#define ULPI2C_SCL_HP15 SIWX91X_GPIO(9, 4, 8, 0, 15, 7)
545
#define ULPI2C_SCL_HP7 SIWX91X_GPIO(9, 4, 2, 0, 7, 1)
546
#define ULPI2C_SCL_HP26 SIWX91X_GPIO(11, 4, 0, 1, 10, 7)
547
#define ULPI2C_SCL_HP27 SIWX91X_GPIO(11, 4, 0, 1, 11, 8)
548
#define ULPI2C_SCL_HP46 SIWX91X_GPIO(9, 4, 10, 2, 14, 8)
549
#define ULPI2C_SCL_ULP1 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 1)
550
#define ULPI2C_SCL_ULP5 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 5)
551
#define ULPI2C_SCL_ULP7 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 7)
552
#define ULPI2C_SCL_ULP8 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 8)
553
#define ULPI2C_SDA_HP6 SIWX91X_GPIO(9, 4, 1, 0, 6, 0)
554
#define ULPI2C_SDA_HP10 SIWX91X_GPIO(9, 4, 5, 0, 10, 4)
555
#define ULPI2C_SDA_HP12 SIWX91X_GPIO(9, 4, 7, 0, 12, 6)
556
#define ULPI2C_SDA_HP25 SIWX91X_GPIO(11, 4, 0, 1, 9, 6)
557
#define ULPI2C_SDA_HP28 SIWX91X_GPIO(11, 4, 0, 1, 12, 9)
558
#define ULPI2C_SDA_HP30 SIWX91X_GPIO(11, 4, 0, 1, 14, 11)
559
#define ULPI2C_SDA_HP47 SIWX91X_GPIO(9, 4, 11, 2, 15, 9)
560
#define ULPI2C_SDA_HP49 SIWX91X_GPIO(9, 4, 13, 3, 1, 11)
561
#define ULPI2C_SDA_ULP0 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 0)
562
#define ULPI2C_SDA_ULP4 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 4)
563
#define ULPI2C_SDA_ULP6 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 6)
564
#define ULPI2C_SDA_ULP9 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 9)
565
#define ULPI2C_SDA_ULP11 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 11)
566
567
#define ULPI2S_CLK_HP15 SIWX91X_GPIO(9, 2, 8, 0, 15, 7)
568
#define ULPI2S_CLK_HP26 SIWX91X_GPIO(11, 2, 0, 1, 10, 7)
569
#define ULPI2S_CLK_HP27 SIWX91X_GPIO(11, 2, 0, 1, 11, 8)
570
#define ULPI2S_CLK_HP46 SIWX91X_GPIO(9, 2, 10, 2, 14, 8)
571
#define ULPI2S_CLK_ULP7 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 7)
572
#define ULPI2S_CLK_ULP8 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 8)
573
#define ULPI2S_DIN_HP12 SIWX91X_GPIO(9, 2, 7, 0, 12, 6)
574
#define ULPI2S_DIN_HP6 SIWX91X_GPIO(9, 2, 1, 0, 6, 0)
575
#define ULPI2S_DIN_HP25 SIWX91X_GPIO(11, 2, 0, 1, 9, 6)
576
#define ULPI2S_DIN_HP28 SIWX91X_GPIO(11, 2, 0, 1, 12, 9)
577
#define ULPI2S_DIN_HP47 SIWX91X_GPIO(9, 2, 11, 2, 15, 9)
578
#define ULPI2S_DIN_ULP0 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 0)
579
#define ULPI2S_DIN_ULP6 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 6)
580
#define ULPI2S_DIN_ULP9 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 9)
581
#define ULPI2S_DOUT_HP7 SIWX91X_GPIO(9, 2, 2, 0, 7, 1)
582
#define ULPI2S_DOUT_HP11 SIWX91X_GPIO(9, 2, 6, 0, 11, 5)
583
#define ULPI2S_DOUT_HP30 SIWX91X_GPIO(11, 2, 0, 1, 14, 11)
584
#define ULPI2S_DOUT_HP49 SIWX91X_GPIO(9, 2, 13, 3, 1, 11)
585
#define ULPI2S_DOUT_ULP1 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 1)
586
#define ULPI2S_DOUT_ULP5 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 5)
587
#define ULPI2S_DOUT_ULP11 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 11)
588
#define ULPI2S_WS_HP8 SIWX91X_GPIO(9, 2, 3, 0, 8, 2)
589
#define ULPI2S_WS_HP10 SIWX91X_GPIO(9, 2, 5, 0, 10, 4)
590
#define ULPI2S_WS_HP29 SIWX91X_GPIO(11, 2, 0, 1, 13, 10)
591
#define ULPI2S_WS_HP48 SIWX91X_GPIO(9, 2, 12, 3, 0, 10)
592
#define ULPI2S_WS_ULP2 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 2)
593
#define ULPI2S_WS_ULP4 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 4)
594
#define ULPI2S_WS_ULP10 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 10)
595
596
#define ULPSSI_CLK_HP6 SIWX91X_GPIO(9, 1, 1, 0, 6, 0)
597
#define ULPSSI_CLK_HP27 SIWX91X_GPIO(11, 1, 0, 1, 11, 8)
598
#define ULPSSI_CLK_HP46 SIWX91X_GPIO(9, 1, 10, 2, 14, 8)
599
#define ULPSSI_CLK_ULP0 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 0)
600
#define ULPSSI_CLK_ULP4 SIWX91X_GPIO(0xFF, 8, 0xFF, 4, 0, 4)
601
#define ULPSSI_CLK_ULP8 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 8)
602
#define ULPSSI_CS0_HP29 SIWX91X_GPIO(11, 1, 0, 1, 13, 10)
603
#define ULPSSI_CS0_HP48 SIWX91X_GPIO(9, 1, 12, 3, 0, 10)
604
#define ULPSSI_CS0_ULP7 SIWX91X_GPIO(0xFF, 8, 0xFF, 4, 0, 7)
605
#define ULPSSI_CS0_ULP10 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 10)
606
#define ULPSSI_CS1_HP10 SIWX91X_GPIO(9, 1, 5, 0, 10, 4)
607
#define ULPSSI_CS1_ULP4 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 4)
608
#define ULPSSI_CS2_HP12 SIWX91X_GPIO(9, 1, 7, 0, 12, 6)
609
#define ULPSSI_CS2_HP25 SIWX91X_GPIO(11, 1, 0, 1, 9, 6)
610
#define ULPSSI_CS2_ULP6 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 6)
611
#define ULPSSI_DIN_HP8 SIWX91X_GPIO(9, 1, 3, 0, 8, 2)
612
#define ULPSSI_DIN_HP28 SIWX91X_GPIO(11, 1, 0, 1, 12, 9)
613
#define ULPSSI_DIN_HP47 SIWX91X_GPIO(9, 1, 11, 2, 15, 9)
614
#define ULPSSI_DIN_ULP2 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 2)
615
#define ULPSSI_DIN_ULP6 SIWX91X_GPIO(0xFF, 8, 0xFF, 4, 0, 6)
616
#define ULPSSI_DIN_ULP9 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 9)
617
#define ULPSSI_DOUT_HP7 SIWX91X_GPIO(9, 1, 2, 0, 7, 1)
618
#define ULPSSI_DOUT_HP30 SIWX91X_GPIO(11, 1, 0, 1, 14, 11)
619
#define ULPSSI_DOUT_HP49 SIWX91X_GPIO(9, 1, 13, 3, 1, 11)
620
#define ULPSSI_DOUT_ULP1 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 1)
621
#define ULPSSI_DOUT_ULP5 SIWX91X_GPIO(0xFF, 8, 0xFF, 4, 0, 5)
622
#define ULPSSI_DOUT_ULP11 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 11)
623
624
#define ULPUART_CTS_HP7 SIWX91X_GPIO(9, 3, 2, 0, 7, 1)
625
#define ULPUART_CTS_HP11 SIWX91X_GPIO(9, 3, 6, 0, 11, 5)
626
#define ULPUART_CTS_HP27 SIWX91X_GPIO(11, 3, 0, 1, 11, 8)
627
#define ULPUART_CTS_HP46 SIWX91X_GPIO(9, 3, 10, 2, 14, 8)
628
#define ULPUART_CTS_ULP1 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 1)
629
#define ULPUART_CTS_ULP5 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 5)
630
#define ULPUART_CTS_ULP8 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 8)
631
#define ULPUART_RTS_HP6 SIWX91X_GPIO(9, 3, 1, 0, 6, 0)
632
#define ULPUART_RTS_HP10 SIWX91X_GPIO(9, 3, 5, 0, 10, 4)
633
#define ULPUART_RTS_HP29 SIWX91X_GPIO(11, 3, 0, 1, 13, 10)
634
#define ULPUART_RTS_HP48 SIWX91X_GPIO(9, 3, 12, 3, 0, 10)
635
#define ULPUART_RTS_ULP0 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 0)
636
#define ULPUART_RTS_ULP4 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 4)
637
#define ULPUART_RTS_ULP10 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 10)
638
#define ULPUART_RX_HP8 SIWX91X_GPIO(9, 3, 3, 0, 8, 2)
639
#define ULPUART_RX_HP12 SIWX91X_GPIO(9, 3, 7, 0, 12, 6)
640
#define ULPUART_RX_HP25 SIWX91X_GPIO(11, 3, 0, 1, 9, 6)
641
#define ULPUART_RX_HP28 SIWX91X_GPIO(11, 3, 0, 1, 12, 9)
642
#define ULPUART_RX_HP47 SIWX91X_GPIO(9, 3, 11, 2, 15, 9)
643
#define ULPUART_RX_ULP2 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 2)
644
#define ULPUART_RX_ULP6 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 6)
645
#define ULPUART_RX_ULP9 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 9)
646
#define ULPUART_TX_HP15 SIWX91X_GPIO(9, 3, 8, 0, 15, 7)
647
#define ULPUART_TX_HP26 SIWX91X_GPIO(11, 3, 0, 1, 10, 7)
648
#define ULPUART_TX_HP30 SIWX91X_GPIO(11, 3, 0, 1, 14, 11)
649
#define ULPUART_TX_HP49 SIWX91X_GPIO(9, 3, 13, 3, 1, 11)
650
#define ULPUART_TX_ULP7 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 7)
651
#define ULPUART_TX_ULP11 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 11)
652
653
#define UULP_GPIO4_ULP2 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 2)
654
#define UULP_TESTMODE0_ULP7 SIWX91X_GPIO(0xFF, 11, 0xFF, 4, 0, 7)
655
#define UULP_TESTMODE0_ULP9 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 9)
656
657
#define WIFI_ANT0_ULP0 SIWX91X_GPIO(0xFF, 6, 0xFF, 4, 0, 0)
658
#define WIFI_ANT1_ULP4 SIWX91X_GPIO(0xFF, 6, 0xFF, 4, 0, 4)
659
#define WIFI_ANT2_ULP5 SIWX91X_GPIO(0xFF, 6, 0xFF, 4, 0, 5)
660
662
664
665
/* The following definitions are duplicates of signals that are also
666
* available on the same pins using other GPIO modes.
667
* #define IR_OUTPUT_ULP5 SIWX91X_GPIO(0xFF, 10, 0xFF, 4, 0, 5)
668
* #define PMU_TEST2_HP30 SIWX91X_GPIO(13, 0xFF, 0, 1, 14, 0)
669
* #define PWM_1H_ULP1 SIWX91X_GPIO(8, 6, 23, 4, 1, 1)
670
* #define PWM_1L_ULP0 SIWX91X_GPIO(8, 6, 22, 4, 0, 0)
671
*/
672
673
#endif
silabs-pinctrl-siwx91x.h
zephyr
dt-bindings
pinctrl
silabs
siwx91x-pinctrl.h
Generated on
for Zephyr API Documentation by
1.16.1
1.16.1