stm32_common_clocks.h

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/*
 * Copyright (c) 2023 STMicroelectronics
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_COMMON_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_COMMON_CLOCKS_H_
 
#define STM32_SRC_SYSCLK        0x001
#define STM32_SRC_LSE           0x002
#define STM32_SRC_LSI           0x003
 
#define NO_SEL                  0xFF
 
#define STM32_CLOCK_DIV_SHIFT   12
 
#define STM32_CLOCK_DIV(div)    (((div) - 1) << STM32_CLOCK_DIV_SHIFT)
 
#define STM32_MCO_CFGR_REG_MASK     0xFFFFU
#define STM32_MCO_CFGR_REG_SHIFT    0U
#define STM32_MCO_CFGR_SHIFT_MASK   0x3FU
#define STM32_MCO_CFGR_SHIFT_SHIFT  16U
#define STM32_MCO_CFGR_MASK_MASK    0x1FU
#define STM32_MCO_CFGR_MASK_SHIFT   22U
#define STM32_MCO_CFGR_VAL_MASK     0x1FU
#define STM32_MCO_CFGR_VAL_SHIFT    27U
 
#define STM32_MCO_CFGR(val, mask, shift, reg)                        \
        ((((reg) & STM32_MCO_CFGR_REG_MASK) << STM32_MCO_CFGR_REG_SHIFT) |        \
         (((shift) & STM32_MCO_CFGR_SHIFT_MASK) << STM32_MCO_CFGR_SHIFT_SHIFT) |    \
         (((mask) & STM32_MCO_CFGR_MASK_MASK) << STM32_MCO_CFGR_MASK_SHIFT) |        \
         (((val) & STM32_MCO_CFGR_VAL_MASK) << STM32_MCO_CFGR_VAL_SHIFT))
 
#define STM32_CLOCK(bus, bit) (STM32_CLOCK_BUS_##bus) (1 << bit)
 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_COMMON_CLOCKS_H_ */