Zephyr API Documentation
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stm32h7_clock.h
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/*
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* Copyright (c) 2022 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
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#include "
stm32_common_clocks.h
"
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/* RM0468, Table 56 Kernel clock dictribution summary */
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/* defined in stm32_common_clocks.h */
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/* Low speed clocks defined in stm32_common_clocks.h */
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#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
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#define STM32_SRC_HSI48 (STM32_SRC_HSE + 1)
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#define STM32_SRC_HSI_KER (STM32_SRC_HSI48 + 1)
/* HSI + HSIKERON */
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#define STM32_SRC_CSI_KER (STM32_SRC_HSI_KER + 1)
/* CSI + CSIKERON */
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#define STM32_SRC_PLL1_P (STM32_SRC_CSI_KER + 1)
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#define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
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#define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
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#define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1)
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#define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
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#define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
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#define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
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#define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
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#define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
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#define STM32_SRC_CKPER (STM32_SRC_PLL3_R + 1)
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/* #define STM32_SRC_I2SCKIN TBD */
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/* #define STM32_SRC_SPDIFRX TBD */
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#define STM32_CLOCK_BUS_AHB3 0x0D4
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#define STM32_CLOCK_BUS_AHB1 0x0D8
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#define STM32_CLOCK_BUS_AHB2 0x0DC
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#define STM32_CLOCK_BUS_AHB4 0x0E0
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#define STM32_CLOCK_BUS_APB3 0x0E4
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#define STM32_CLOCK_BUS_APB1 0x0E8
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#define STM32_CLOCK_BUS_APB1_2 0x0EC
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#define STM32_CLOCK_BUS_APB2 0x0F0
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#define STM32_CLOCK_BUS_APB4 0x0F4
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/* TBD: To remove ? */
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#define STM32_SRC_PCLK1 STM32_CLOCK_BUS_APB1
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#define STM32_SRC_PCLK2 STM32_CLOCK_BUS_APB2
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#define STM32_SRC_HCLK3 STM32_CLOCK_BUS_AHB3
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#define STM32_SRC_PCLK3 STM32_CLOCK_BUS_APB3
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#define STM32_SRC_PCLK4 STM32_CLOCK_BUS_APB4
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB3
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB4
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#define STM32_CLOCK_REG_MASK 0xFFU
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#define STM32_CLOCK_REG_SHIFT 0U
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#define STM32_CLOCK_SHIFT_MASK 0x1FU
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#define STM32_CLOCK_SHIFT_SHIFT 8U
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#define STM32_CLOCK_MASK_MASK 0x7U
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#define STM32_CLOCK_MASK_SHIFT 13U
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#define STM32_CLOCK_VAL_MASK 0x7U
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#define STM32_CLOCK_VAL_SHIFT 16U
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#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
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((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
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(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
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(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
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(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
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#define D1CCIPR_REG 0x4C
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#define D2CCIP1R_REG 0x50
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#define D2CCIP2R_REG 0x54
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#define D3CCIPR_REG 0x58
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#define BDCR_REG 0x70
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#define CFGR_REG 0x10
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#define FMC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG)
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#define QSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)
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#define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, D1CCIPR_REG)
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#define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 16, D1CCIPR_REG)
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#define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG)
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/* Device domain clocks selection helpers (RM0468.pdf) */
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#define OSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)
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#define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP1R_REG)
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#define SAI23_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 6, D2CCIP1R_REG)
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#define SPI123_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, D2CCIP1R_REG)
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#define SPI45_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, D2CCIP1R_REG)
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#define SPDIF_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, D2CCIP1R_REG)
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#define DFSDM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 24, D2CCIP1R_REG)
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#define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D2CCIP1R_REG)
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#define SWP_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, D2CCIP1R_REG)
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#define USART2345678_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP2R_REG)
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#define USART16_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 3, D2CCIP2R_REG)
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#define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, D2CCIP2R_REG)
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#define I2C123_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, D2CCIP2R_REG)
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#define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, D2CCIP2R_REG)
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#define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, D2CCIP2R_REG)
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#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 28, D2CCIP2R_REG)
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#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D3CCIPR_REG)
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#define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, D3CCIPR_REG)
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#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 10, D3CCIPR_REG)
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#define LPTIM345_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 13, D3CCIPR_REG)
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#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, D3CCIPR_REG)
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#define SAI4A_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 21, D3CCIPR_REG)
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#define SAI4B_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 24, D3CCIPR_REG)
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#define SPI6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 28, D3CCIPR_REG)
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#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
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#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 22, CFGR_REG)
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#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 18, CFGR_REG)
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#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0xF, 29, CFGR_REG)
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#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 25, CFGR_REG)
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/* MCO prescaler : division factor */
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#define MCO_PRE_DIV_1 1
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#define MCO_PRE_DIV_2 2
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#define MCO_PRE_DIV_3 3
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#define MCO_PRE_DIV_4 4
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#define MCO_PRE_DIV_5 5
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#define MCO_PRE_DIV_6 6
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#define MCO_PRE_DIV_7 7
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#define MCO_PRE_DIV_8 8
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#define MCO_PRE_DIV_9 9
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#define MCO_PRE_DIV_10 10
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#define MCO_PRE_DIV_11 11
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#define MCO_PRE_DIV_12 12
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#define MCO_PRE_DIV_13 13
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#define MCO_PRE_DIV_14 14
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#define MCO_PRE_DIV_15 15
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */
stm32_common_clocks.h
zephyr
dt-bindings
clock
stm32h7_clock.h
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