Zephyr API Documentation 4.0.0-rc3
A Scalable Open Source RTOS
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stm32l1_clock.h
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1/*
2 * Copyright (c) 2022 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_
8
10
12#define STM32_CLOCK_BUS_AHB1 0x01c
13#define STM32_CLOCK_BUS_APB2 0x020
14#define STM32_CLOCK_BUS_APB1 0x024
15
16#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
17#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
18
20/* RM0038.pdf, ยง6.3.14 Control/status register (RCC_CSR) */
21
23/* defined in stm32_common_clocks.h */
25/* Low speed clocks defined in stm32_common_clocks.h */
26#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
27#define STM32_SRC_HSI (STM32_SRC_HSE + 1)
28
29#define STM32_CLOCK_REG_MASK 0xFFU
30#define STM32_CLOCK_REG_SHIFT 0U
31#define STM32_CLOCK_SHIFT_MASK 0x1FU
32#define STM32_CLOCK_SHIFT_SHIFT 8U
33#define STM32_CLOCK_MASK_MASK 0x7U
34#define STM32_CLOCK_MASK_SHIFT 13U
35#define STM32_CLOCK_VAL_MASK 0x7U
36#define STM32_CLOCK_VAL_SHIFT 16U
37
51#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
52 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
53 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
54 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
55 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
56
58#define CSR_REG 0x34
59
60#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CSR_REG)
61
62#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_ */