Zephyr API Documentation 4.0.0-rc3
A Scalable Open Source RTOS
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stm32l4_clock.h
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1/*
2 * Copyright (c) 2022 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_
8
9#include "stm32_common_clocks.h"
10
12#define STM32_CLOCK_BUS_AHB1 0x048
13#define STM32_CLOCK_BUS_AHB2 0x04c
14#define STM32_CLOCK_BUS_AHB3 0x050
15#define STM32_CLOCK_BUS_APB1 0x058
16#define STM32_CLOCK_BUS_APB1_2 0x05c
17#define STM32_CLOCK_BUS_APB2 0x060
18
19#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
20#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
21
23/* RM0351/RM0432/RM0438, ยง Clock configuration register (RCC_CCIPRx) */
24
26/* defined in stm32_common_clocks.h */
28/* Low speed clocks defined in stm32_common_clocks.h */
29#define STM32_SRC_HSI (STM32_SRC_LSI + 1)
30#define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
31#define STM32_SRC_MSI (STM32_SRC_HSI48 + 1)
33#define STM32_SRC_PCLK (STM32_SRC_MSI + 1)
35#define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1)
36#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
37#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
38/* TODO: PLLSAI clocks */
39
40#define STM32_CLOCK_REG_MASK 0xFFU
41#define STM32_CLOCK_REG_SHIFT 0U
42#define STM32_CLOCK_SHIFT_MASK 0x1FU
43#define STM32_CLOCK_SHIFT_SHIFT 8U
44#define STM32_CLOCK_MASK_MASK 0x7U
45#define STM32_CLOCK_MASK_SHIFT 13U
46#define STM32_CLOCK_VAL_MASK 0x7U
47#define STM32_CLOCK_VAL_SHIFT 16U
48
62#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
63 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
64 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
65 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
66 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
67
69#define CCIPR_REG 0x88
70#define CCIPR2_REG 0x9C
71
73#define BDCR_REG 0x90
74
76#define CFGR_REG 0x08
77
80#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
81#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
82#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG)
83#define UART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG)
84#define UART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
85#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
86#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
87#define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
88#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
89#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
90#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
91#define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG)
92#define SAI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR_REG)
93#define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)
94#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG)
95#define SWPMI1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 30, CCIPR_REG)
96#define DFSDM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, CCIPR_REG)
98#define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR2_REG)
99#define DFSDM_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 2, CCIPR2_REG)
100#define ADFSDM_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 3, CCIPR2_REG)
101/* #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 5, CCIPR2_REG) */
102/* #define SAI2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 8, CCIPR2_REG) */
103#define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 12, CCIPR2_REG)
104#define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 14, CCIPR2_REG)
105#define OSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR2_REG)
107#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
109#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR_REG)
110#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR_REG)
111
112#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_ */
stm32_common_clocks.h