Zephyr API Documentation
4.3.99
A Scalable Open Source RTOS
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stm32u3_clock.h
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/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U3_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U3_CLOCK_H_
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#include "
stm32_common_clocks.h
"
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/* RM0487, Figure 36 Clock tree for STM32U3 Series */
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/* defined in stm32_common_clocks.h */
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#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
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#define STM32_SRC_HSI16 (STM32_SRC_HSE + 1)
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#define STM32_SRC_HSI48 (STM32_SRC_HSI16 + 1)
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#define STM32_SRC_MSIS (STM32_SRC_HSI48 + 1)
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#define STM32_SRC_MSIK (STM32_SRC_MSIS + 1)
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#define STM32_SRC_HCLK (STM32_SRC_MSIK + 1)
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#define STM32_SRC_PCLK1 (STM32_SRC_HCLK + 1)
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#define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1)
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#define STM32_SRC_PCLK3 (STM32_SRC_PCLK2 + 1)
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#define STM32_SRC_TIMPCLK1 (STM32_SRC_PCLK3 + 1)
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#define STM32_SRC_TIMPCLK2 (STM32_SRC_TIMPCLK1 + 1)
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/* #define STM32_SRC_ICLK TBD */
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#define STM32_CLOCK_BUS_AHB1 0x088
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#define STM32_CLOCK_BUS_AHB1_2 0x094
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#define STM32_CLOCK_BUS_AHB2 0x08C
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#define STM32_CLOCK_BUS_AHB2_2 0x090
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#define STM32_CLOCK_BUS_APB1 0x09C
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#define STM32_CLOCK_BUS_APB1_2 0x0A0
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#define STM32_CLOCK_BUS_APB2 0x0A4
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#define STM32_CLOCK_BUS_APB3 0x0A8
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
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#define CCIPR1_REG 0x100
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#define CCIPR2_REG 0x104
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#define CCIPR3_REG 0x108
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#define BDCR_REG 0x110
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#define CFGR1_REG 0x0C
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#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0, 0, CCIPR1_REG)
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#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 2, CCIPR1_REG)
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#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 4, 4, CCIPR1_REG)
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#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 6, CCIPR1_REG)
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#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 8, 8, CCIPR1_REG)
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#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 10, CCIPR1_REG)
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#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 12, 12, CCIPR1_REG)
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#define I3C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 14, CCIPR1_REG)
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#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 16, 16, CCIPR1_REG)
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#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR1_REG)
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#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 20, 20, CCIPR1_REG)
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#define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR1_REG)
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#define FDCAN1_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 24, CCIPR1_REG)
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#define ICLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR1_REG)
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#define USB1_SEL(val) STM32_DT_CLOCK_SELECT((val), 28, 28, CCIPR1_REG)
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#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 29, CCIPR1_REG)
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#define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR2_REG)
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#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR2_REG)
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#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 5, CCIPR2_REG)
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#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 11, CCIPR2_REG)
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#define ADCDAC_PRE(val) STM32_DT_CLOCK_SELECT((val), 15, 12, CCIPR2_REG)
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#define ADCDAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR2_REG)
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#define DAC1SH_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 19, CCIPR2_REG)
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#define OCTOSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 20, 20, CCIPR2_REG)
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#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR3_REG)
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#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 6, CCIPR3_REG)
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#define LPTIM34_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR3_REG)
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#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR3_REG)
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#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG)
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#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 24, CFGR1_REG)
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#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 30, 28, CFGR1_REG)
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/* MCO prescaler : division factor */
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#define MCO_PRE_DIV_1 0
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#define MCO_PRE_DIV_2 1
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#define MCO_PRE_DIV_4 2
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#define MCO_PRE_DIV_8 3
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#define MCO_PRE_DIV_16 4
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#define MCO_PRE_DIV_32 5
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#define MCO_PRE_DIV_64 6
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#define MCO_PRE_DIV_128 7
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/* ADC/DAC prescaler division factor */
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#define ADCDAC_PRE_DIV_1 0x0
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#define ADCDAC_PRE_DIV_2 0x1
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#define ADCDAC_PRE_DIV_4 0x8
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#define ADCDAC_PRE_DIV_8 0x9
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#define ADCDAC_PRE_DIV_16 0xA
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#define ADCDAC_PRE_DIV_32 0xB
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#define ADCDAC_PRE_DIV_64 0xC
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#define ADCDAC_PRE_DIV_128 0xD
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#define ADCDAC_PRE_DIV_256 0xE
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#define ADCDAC_PRE_DIV_512 0xF
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U3_CLOCK_H_ */
stm32_common_clocks.h
zephyr
dt-bindings
clock
stm32u3_clock.h
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