Zephyr API Documentation
4.4.99
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
stm32u5_clock.h
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2022 Linaro Limited
3
* Copyright (c) 2023 STMicroelectronics
4
*
5
* SPDX-License-Identifier: Apache-2.0
6
*/
7
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
8
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
9
10
#include "
stm32_common_clocks.h
"
11
13
14
/* RM0456 Rev 6, Figure 38 Clock tree for STM32U5 Series */
15
17
/* defined in stm32_common_clocks.h */
20
#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
22
#define STM32_SRC_HSI16 (STM32_SRC_HSE + 1)
24
#define STM32_SRC_HSI48 (STM32_SRC_HSI16 + 1)
26
#define STM32_SRC_MSIS (STM32_SRC_HSI48 + 1)
28
#define STM32_SRC_MSIK (STM32_SRC_MSIS + 1)
30
#define STM32_SRC_SHSI (STM32_SRC_MSIK + 1)
33
#define STM32_SRC_HCLK (STM32_SRC_SHSI + 1)
35
#define STM32_SRC_PCLK1 (STM32_SRC_HCLK + 1)
37
#define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1)
39
#define STM32_SRC_PCLK3 (STM32_SRC_PCLK2 + 1)
41
#define STM32_SRC_TIMPCLK1 (STM32_SRC_PCLK3 + 1)
43
#define STM32_SRC_TIMPCLK2 (STM32_SRC_TIMPCLK1 + 1)
46
#define STM32_SRC_PLL1_P (STM32_SRC_TIMPCLK2 + 1)
48
#define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
50
#define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
52
#define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1)
54
#define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
56
#define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
58
#define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
60
#define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
62
#define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
64
#define STM32_SRC_DSIPHY (STM32_SRC_PLL3_R + 1)
66
/* #define STM32_SRC_ICLK TBD */
67
69
#define STM32_CLOCK_BUS_AHB1 0x088
70
#define STM32_CLOCK_BUS_AHB2 0x08C
71
#define STM32_CLOCK_BUS_AHB2_2 0x090
72
#define STM32_CLOCK_BUS_AHB3 0x094
73
#define STM32_CLOCK_BUS_APB1 0x09C
74
#define STM32_CLOCK_BUS_APB1_2 0x0A0
75
#define STM32_CLOCK_BUS_APB2 0x0A4
76
#define STM32_CLOCK_BUS_APB3 0x0A8
77
78
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
79
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
80
82
#define CCIPR1_REG 0xE0
83
#define CCIPR2_REG 0xE4
84
#define CCIPR3_REG 0xE8
85
87
#define BDCR_REG 0xF0
88
90
#define CFGR1_REG 0x1C
91
94
#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR1_REG)
95
#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR1_REG)
96
#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, CCIPR1_REG)
97
#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR1_REG)
98
#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR1_REG)
99
#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR1_REG)
100
#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR1_REG)
101
#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 14, CCIPR1_REG)
102
#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR1_REG)
103
#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR1_REG)
104
#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR1_REG)
105
#define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR1_REG)
106
#define FDCAN1_SEL(val) STM32_DT_CLOCK_SELECT((val), 25, 24, CCIPR1_REG)
107
#define ICKLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR1_REG)
108
#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 29, CCIPR1_REG)
110
#define MDF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR2_REG)
111
#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 5, CCIPR2_REG)
112
#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 8, CCIPR2_REG)
113
#define SAE_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 11, CCIPR2_REG)
114
#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR2_REG)
115
#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 14, CCIPR2_REG)
116
#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 15, CCIPR2_REG)
117
#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 16, 16, CCIPR2_REG)
118
#define LTDC_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 18, CCIPR2_REG)
119
#define OCTOSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR2_REG)
120
#define HSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR2_REG)
121
#define I2C5_SEL(val) STM32_DT_CLOCK_SELECT((val), 25, 24, CCIPR2_REG)
122
#define I2C6_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR2_REG)
123
#define OTGHS_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 30, CCIPR2_REG)
125
#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR3_REG)
126
#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 4, 3, CCIPR3_REG)
127
#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR3_REG)
128
#define LPTIM34_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR3_REG)
129
#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR3_REG)
130
#define ADCDAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 12, CCIPR3_REG)
131
#define DAC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 15, CCIPR3_REG)
132
#define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 16, CCIPR3_REG)
134
#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG)
135
137
#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 24, CFGR1_REG)
138
#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 30, 28, CFGR1_REG)
139
140
/* MCO prescaler : division factor */
141
#define MCO_PRE_DIV_1 0
142
#define MCO_PRE_DIV_2 1
143
#define MCO_PRE_DIV_4 2
144
#define MCO_PRE_DIV_8 3
145
#define MCO_PRE_DIV_16 4
146
147
#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ */
stm32_common_clocks.h
zephyr
dt-bindings
clock
stm32u5_clock.h
Generated on
for Zephyr API Documentation by
1.16.1
1.16.1