Zephyr API Documentation
4.0.99
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
stm32u5_clock.h
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2022 Linaro Limited
3
* Copyright (c) 2023 STMicroelectronics
4
*
5
* SPDX-License-Identifier: Apache-2.0
6
*/
7
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
8
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
9
10
#include "
stm32_common_clocks.h
"
11
14
/* RM0468, Table 56 Kernel clock distribution summary */
15
17
/* defined in stm32_common_clocks.h */
19
#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
20
#define STM32_SRC_HSI16 (STM32_SRC_HSE + 1)
21
#define STM32_SRC_HSI48 (STM32_SRC_HSI16 + 1)
22
#define STM32_SRC_MSIS (STM32_SRC_HSI48 + 1)
23
#define STM32_SRC_MSIK (STM32_SRC_MSIS + 1)
25
#define STM32_SRC_HCLK (STM32_SRC_MSIK + 1)
26
#define STM32_SRC_PCLK1 (STM32_SRC_HCLK + 1)
27
#define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1)
28
#define STM32_SRC_PCLK3 (STM32_SRC_PCLK2 + 1)
30
#define STM32_SRC_PLL1_P (STM32_SRC_PCLK3 + 1)
31
#define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
32
#define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
33
#define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1)
34
#define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
35
#define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
36
#define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
37
#define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
38
#define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
40
/* #define STM32_SRC_ICLK TBD */
41
43
#define STM32_CLOCK_BUS_AHB1 0x088
44
#define STM32_CLOCK_BUS_AHB2 0x08C
45
#define STM32_CLOCK_BUS_AHB2_2 0x090
46
#define STM32_CLOCK_BUS_AHB3 0x094
47
#define STM32_CLOCK_BUS_APB1 0x09C
48
#define STM32_CLOCK_BUS_APB1_2 0x0A0
49
#define STM32_CLOCK_BUS_APB2 0x0A4
50
#define STM32_CLOCK_BUS_APB3 0x0A8
51
52
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
53
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
54
55
#define STM32_CLOCK_REG_MASK 0xFFU
56
#define STM32_CLOCK_REG_SHIFT 0U
57
#define STM32_CLOCK_SHIFT_MASK 0x1FU
58
#define STM32_CLOCK_SHIFT_SHIFT 8U
59
#define STM32_CLOCK_MASK_MASK 0x7U
60
#define STM32_CLOCK_MASK_SHIFT 13U
61
#define STM32_CLOCK_VAL_MASK 0x7U
62
#define STM32_CLOCK_VAL_SHIFT 16U
63
77
#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
78
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
79
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
80
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
81
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
82
84
#define CCIPR1_REG 0xE0
85
#define CCIPR2_REG 0xE4
86
#define CCIPR3_REG 0xE8
87
89
#define BDCR_REG 0xF0
90
92
#define CFGR1_REG 0x1C
93
96
#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR1_REG)
97
#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR1_REG)
98
#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR1_REG)
99
#define UART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR1_REG)
100
#define UART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR1_REG)
101
#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR1_REG)
102
#define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR1_REG)
103
#define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR1_REG)
104
#define SPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR1_REG)
105
#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR1_REG)
106
#define SPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR1_REG)
107
#define SYSTICK_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR1_REG)
108
#define FDCAN1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR1_REG)
109
#define ICKLK_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR1_REG)
110
#define TIMIC_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 29, CCIPR1_REG)
112
#define MDF1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR2_REG)
113
#define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 5, CCIPR2_REG)
114
#define SAI2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 8, CCIPR2_REG)
115
#define SAE_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 11, CCIPR2_REG)
116
#define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG)
117
#define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 14, CCIPR2_REG)
118
#define DSIHOST_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, CCIPR2_REG)
119
#define USART6_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 16, CCIPR2_REG)
120
#define LTDC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 18, CCIPR2_REG)
121
#define OCTOSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR2_REG)
122
#define HSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR2_REG)
123
#define I2C5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR2_REG)
124
#define I2C6_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR2_REG)
125
#define OTGHS_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR2_REG)
127
#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR3_REG)
128
#define SPI3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 3, CCIPR3_REG)
129
#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR3_REG)
130
#define LPTIM34_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR3_REG)
131
#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR3_REG)
132
#define ADCDAC_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR3_REG)
133
#define DAC1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, CCIPR3_REG)
134
#define ADF1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, CCIPR3_REG)
136
#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
137
139
#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG)
140
#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG)
141
142
/* MCO prescaler : division factor */
143
#define MCO_PRE_DIV_1 0
144
#define MCO_PRE_DIV_2 1
145
#define MCO_PRE_DIV_4 2
146
#define MCO_PRE_DIV_8 3
147
#define MCO_PRE_DIV_16 4
148
149
#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ */
stm32_common_clocks.h
zephyr
dt-bindings
clock
stm32u5_clock.h
Generated on Mon Dec 23 2024 00:03:17 for Zephyr API Documentation by
1.12.0
1.12.0