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ftdi,ft800 (on spi bus)

Vendor: Future Technology Devices International Ltd.

Description

FTDI FT800 graphic controller

Properties

Properties not inherited from the base binding file.

Name

Type

Details

irq-gpios

phandle-array

Optional IRQ line of FT800 controller

pclk

int

The value to divide the main clock by for PCLK. If the
typical main clock was 48MHz and this value is 5, the PCLK
will be 9.6 MHz. Must be positive value to enable the screen

This property is required.

pclk_pol

int

Polarity of PCLK. If it is set to zero, PCLK polarity is on
the rising edge. If it is set to one, PCLK polarity is on
the falling edge.

This property is required.

cspread

int

Controls the transition of RGB signals with PCLK active clock
edge. When set to 0, R[7:2],G[7:2] and B[7:2] signals change
following the active edge of PCLK. When set to 1, R[7:2]
changes a PCLK clock early and B[7:2] a PCLK clock later,
which helps reduce the system noise.

This property is required.

swizzle

int

Controls the arrangement of output RGB pins, which may help
support different LCD panel. Please check FT800 Programmers
Guide for details.

This property is required.

vsize

int

Number of visible lines of pixels in one frame

This property is required.

voffset

int

Number of invisible lines at the beginning of a new frame

This property is required.

vcycle

int

Number of all lines in a frame. It includes all visible and
invisible lines at the beginning and at the end of a frame.

This property is required.

vsync0

int

Number of lines for the high state of signal VSYNC at
the start of new frame.

This property is required.

vsync1

int

Number of lines for signal VSYNC toggle takes at the start
of new frame.

This property is required.

hsize

int

Number of PCLK cycles per visible part of horizontal line

This property is required.

hoffset

int

Number of PCLK cycles before pixels are scanned out for
given line

This property is required.

hcycle

int

Number of total PCLK cycles per horizontal line scan.

This property is required.

hsync0

int

Number of PCLK cycles of HSYNC high state during start of line

This property is required.

hsync1

int

Number of PCLK cycles for HSYNC toggle during start of line.

This property is required.

spi-max-frequency

int

Maximum clock frequency of device's SPI interface in Hz

This property is required.

duplex

int

Duplex mode, full or half. By default it's always full duplex thus 0
as this is, by far, the most common mode.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
  0    SPI_FULL_DUPLEX
  2048 SPI_HALF_DUPLEX

Legal values: 0, 2048

frame-format

int

Motorola or TI frame format. By default it's always Motorola's,
thus 0 as this is, by far, the most common format.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
  0     SPI_FRAME_FORMAT_MOTOROLA
  32768 SPI_FRAME_FORMAT_TI

Legal values: 0, 32768

supply-gpios

phandle-array

GPIO specifier that controls power to the device.

This property should be provided when the device has a dedicated
switch that controls power to the device.  The supply state is
entirely the responsibility of the device driver.

Contrast with vin-supply.

vin-supply

phandle

Reference to the regulator that controls power to the device.
The referenced devicetree node must have a regulator compatible.

This property should be provided when device power is supplied
by a shared regulator.  The supply state is dependent on the
request status of all devices fed by the regulator.

Contrast with supply-gpios.  If both properties are provided
then the regulator must be requested before the supply GPIOS is
set to an active state, and the supply GPIOS must be set to an
inactive state before releasing the regulator.