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CONFIG_2ND_LVL_ISR_TBL_OFFSET

Offset in _sw_isr_table for level 2 interrupts

Type: int

Help

This is the offset in _sw_isr_table, the generated ISR handler table,
where storage for 2nd level interrupt ISRs begins. This is
typically allocated after ISRs for level 1 interrupts.

Defaults

  • 21

  • 21

  • 21

  • 21

  • 21

  • 32

  • 12

  • 12

  • 12

  • 12

  • 0

Kconfig definitions

At boards/xtensa/intel_adsp_cavs15/Kconfig.defconfig:32

Included via Kconfig:8Kconfig.zephyr:22

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 21
    depends on BOARD_INTEL_ADSP_CAVS15

At boards/xtensa/intel_adsp_cavs18/Kconfig.defconfig:32

Included via Kconfig:8Kconfig.zephyr:22

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 21
    depends on BOARD_INTEL_ADSP_CAVS18

At boards/xtensa/intel_adsp_cavs20/Kconfig.defconfig:32

Included via Kconfig:8Kconfig.zephyr:22

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 21
    depends on BOARD_INTEL_ADSP_CAVS20

At boards/xtensa/intel_adsp_cavs25/Kconfig.defconfig:32

Included via Kconfig:8Kconfig.zephyr:22

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 21
    depends on BOARD_INTEL_ADSP_CAVS25

At boards/xtensa/intel_s1000_crb/Kconfig.defconfig:38

Included via Kconfig:8Kconfig.zephyr:22

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 21
    depends on BOARD_INTEL_S1000_CRB

At soc/riscv/openisa_rv32m1/Kconfig.defconfig:52

Included via Kconfig:8Kconfig.zephyr:27

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 32
    depends on MULTI_LEVEL_INTERRUPTS && SOC_OPENISA_RV32M1_RISCV32

At soc/riscv/riscv-privilege/miv/Kconfig.defconfig.series:20

Included via Kconfig:8Kconfig.zephyr:27soc/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 12
    depends on SOC_SERIES_RISCV32_MIV

At soc/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series:20

Included via Kconfig:8Kconfig.zephyr:27soc/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 12
    depends on SOC_SERIES_RISCV_SIFIVE_FREEDOM

At soc/riscv/riscv-privilege/starfive_jh71xx/Kconfig.defconfig.series:21

Included via Kconfig:8Kconfig.zephyr:27soc/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 12
    depends on SOC_SERIES_STARFIVE_JH71XX

At soc/riscv/riscv-privilege/virt/Kconfig.defconfig.series:21

Included via Kconfig:8Kconfig.zephyr:27soc/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 12
    depends on SOC_SERIES_RISCV_VIRT

At drivers/interrupt_controller/Kconfig.multilevel:36

Included via Kconfig:8Kconfig.zephyr:40drivers/Kconfig:26drivers/interrupt_controller/Kconfig:49

Menu path: (Top) → Device Drivers → Interrupt Controllers → Multi-level interrupt support → Second-level interrupt support

config 2ND_LVL_ISR_TBL_OFFSET
    int "Offset in _sw_isr_table for level 2 interrupts"
    default 0
    depends on 2ND_LEVEL_INTERRUPTS
    help
      This is the offset in _sw_isr_table, the generated ISR handler table,
      where storage for 2nd level interrupt ISRs begins. This is
      typically allocated after ISRs for level 1 interrupts.

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)