CONFIG_CLOCK_STM32_PLL_R_DIVISOR

PLL R Divisor

PLL R Divisor

PLL R Divisor

PLL R Divisor

Type: int

Help

PLL R Output divisor, allowed values: 1-128.

Help

PLL R Output divisor, allowed values: 0, 2, 4, 6, 8.

Help

PLL R VCO divisor, allowed values: 2-8.

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PLL R Output divisor, allowed values: 2, 4, 6, 8.

Defaults

  • 2
  • 4
  • 2
  • 2

Kconfig definitions

At drivers/clock_control/Kconfig.stm32h7:90

Included via Kconfig:10Kconfig.zephyr:40drivers/Kconfig:50drivers/clock_control/Kconfig:28drivers/clock_control/Kconfig.stm32:125

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_R_DIVISOR
    int "PLL R Divisor"
    range 1 128
    default 2
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32H7X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    help
      PLL R Output divisor, allowed values: 1-128.

At drivers/clock_control/Kconfig.stm32l4_wb:44

Included via Kconfig:10Kconfig.zephyr:40drivers/Kconfig:50drivers/clock_control/Kconfig:28drivers/clock_control/Kconfig.stm32:127

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_R_DIVISOR
    int "PLL R Divisor"
    range 0 8
    default 4
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX) && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    help
      PLL R Output divisor, allowed values: 0, 2, 4, 6, 8.

At drivers/clock_control/Kconfig.stm32g0:43

Included via Kconfig:10Kconfig.zephyr:40drivers/Kconfig:50drivers/clock_control/Kconfig:28drivers/clock_control/Kconfig.stm32:128

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_R_DIVISOR
    int "PLL R Divisor"
    range 2 8
    default 2
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32G0X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    help
      PLL R VCO divisor, allowed values: 2-8.

At drivers/clock_control/Kconfig.stm32g4:42

Included via Kconfig:10Kconfig.zephyr:40drivers/Kconfig:50drivers/clock_control/Kconfig:28drivers/clock_control/Kconfig.stm32:129

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_R_DIVISOR
    int "PLL R Divisor"
    range 2 8
    default 2
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32G4X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    help
      PLL R Output divisor, allowed values: 2, 4, 6, 8.

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)