CONFIG_SOC_OPENISA_RV32M1_RISCV32

OpenISA RV32M1 RISC-V cores

Type: bool

Help

Enable support for OpenISA RV32M1 RISC-V processors. Choose this option to target the RI5CY or ZERO-RISCY core. This option should not be used to target either Arm core.

Direct dependencies

RISCV && <choice: SoC/CPU/Configuration Selection>

(Includes any dependencies from ifs and menus.)

Kconfig definition

At soc/riscv/openisa_rv32m1/Kconfig.soc:4

Included via Kconfig:8Kconfig.zephyr:29soc/Kconfig:6

Menu path: (Top) → SoC/CPU/Configuration Selection

config SOC_OPENISA_RV32M1_RISCV32
    bool "OpenISA RV32M1 RISC-V cores"
    select XIP
    select HAS_RV32M1_LPUART
    select HAS_RV32M1_LPI2C
    select HAS_RV32M1_LPSPI
    select ATOMIC_OPERATIONS_C
    select VEGA_SDK_HAL
    select RISCV_SOC_INTERRUPT_INIT
    select CLOCK_CONTROL
    select HAS_RV32M1_FTFX
    select HAS_FLASH_LOAD_OFFSET
    depends on RISCV && <choice: SoC/CPU/Configuration Selection>
    help
      Enable support for OpenISA RV32M1 RISC-V processors. Choose
      this option to target the RI5CY or ZERO-RISCY core. This
      option should not be used to target either Arm core.

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)