All Configuration Options¶
Kconfig files describe build-time configuration options (called symbols
in Kconfig-speak), how they’re grouped into menus and sub-menus, and
dependencies between them that determine what configurations are valid.
Kconfig files appear throughout the directory tree. For example,
subsys/power/Kconfig defines power-related options.
This documentation is generated automatically from the Kconfig files by
the genrest.py script. Click on symbols for more
information.
Configuration Options¶
Symbol name |
Help/prompt |
|---|---|
Second level interrupts are used to increase the number of addressable interrupts in a system. |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the offset in _sw_isr_table, the generated ISR handler table, where storage for 2nd level interrupt ISRs begins. This is typically allocated after ISRs for level 1 interrupts. |
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Third level interrupts are used to increase the number of addressable interrupts in a system. |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the offset in _sw_isr_table, the generated ISR handler table, where storage for 3rd level interrupt ISRs begins. This is typically allocated after ISRs for level 2 interrupts. |
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This option tells the build system that the target system is using a 64-bit address space, meaning that pointer and long types are 64 bits wide. This option is selected by arch/$ARCH/Kconfig, soc//Kconfig, or boards//Kconfig and the user should generally avoid modifying it. |
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Allow retrieval of platform configuration at runtime. |
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Enable ADC (Analog to Digital Converter) driver configuration. |
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Enable ADC 0 |
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Enable ADC 1 |
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Enable ADC 2 |
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This option enables the asynchronous API calls. |
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Enable LMP90xxx ADC driver. The LMP90xxx is a multi-channel, low power sensor analog frontend (AFE). |
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Priority level for the internal ADC data acquisition thread. |
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Size of the stack used for the internal data acquisition thread. |
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Use Cyclic Redundancy Check (CRC) to verify the integrity of the data read from the LMP90xxx. |
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Enable GPIO child device support in the LMP90xxx ADC driver. The GPIO functionality is handled by the LMP90xxx GPIO driver. |
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LMP90xxx ADC device driver initialization priority. |
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Debug |
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Error |
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Info |
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Off |
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Warning |
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Enable the MCUX ADC12 driver. |
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Enable the MCUX ADC16 driver. |
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Divide ratio is 1 |
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Divide ratio is 2 |
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Divide ratio is 4 |
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Divide ratio is 8 |
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Alternate reference pair |
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Default voltage reference pair V_REFH and V_REFL |
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Enable support for nrfx ADC driver for nRF51 MCU series. |
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Number of ADC channels to be supported by the driver. Each channel needs a dedicated structure in RAM that stores the ADC settings to be used when sampling this channel. |
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Enable support for nrfx SAADC driver for nRF52 MCU series. |
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Enable Atmel SAM0 MCU Family Analog-to-Digital Converter (ADC) driver. |
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Enable Atmel SAM MCU Family Analog-to-Digital Converter (ADC) driver based on AFEC module. |
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Enable ADC Shell for testing. |
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Enable the driver implementation for the stm32xx ADC |
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Enable ADC driver for Microchip XEC MCU series. |
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Enable the driver for Analog Devices ADT7420 High-Accuracy 16-bit Digital I2C Temperature Sensors. |
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The critical overtemperature pin asserts when the temperature exceeds this value. The default value of 147 is the reset default of the ADT7420. |
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Specify the temperature hysteresis in °C for the THIGH, TLOW, and TCRIT temperature limits. |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable driver for ADXL362 Three-Axis Digital Accelerometers. |
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Unsigned value that sets the ADXL362 interrupt mode in either absolute or referenced mode. 0 - Absolute mode 1 - Referenced mode |
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100 Hz |
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12.5 Hz |
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200 Hz |
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25 Hz |
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400 Hz |
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50 Hz |
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Set at runtime. |
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2G |
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4G |
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8G |
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Set at runtime. |
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Unsigned value that the adxl362 samples are compared to in activity trigger mode. |
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Unsigned value that the adxl362 samples are compared to in inactivity trigger mode. |
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Unsigned value that sets the ADXL362 in different interrupt modes. 0 - Default mode 1 - Linked mode 3 - Loop mode |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable driver for ADXL372 Three-Axis Digital Accelerometers. |
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Threshold for activity detection. |
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The activity timer implements a robust activity detection that minimizes false positive motion triggers. When the timer is used, only sustained motion can trigger activity detection. Number of multiples of 3.3 ms activity timer for which above threshold acceleration is required to detect activity. It is 3.3 ms per code for 6400 Hz ODR, and it is 6.6 ms per code for 3200 Hz ODR and below. |
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1600 Hz |
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200 Hz |
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3200 Hz |
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400 Hz |
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800 Hz |
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ODR/210 |
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ODR/411 |
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ODR/812 |
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ODR/1616 |
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Disabled |
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I2C Interface |
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Threshold for in-activity detection. |
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The time that all enabled axes must be lower than the inactivity threshold for an inactivity event to be detected. Number of multiples of 26 ms inactivity timer for which below threshold acceleration is required to detect inactivity. It is 26 ms per code for 3200 Hz ODR and below, and it is 13 ms per code for 6400 Hz ODR. |
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Disabled |
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In this mode, acceleration data is provided continuously at the output data rate (ODR). |
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1600 Hz |
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3200 Hz |
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400 Hz |
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6400 Hz |
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800 Hz |
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In most high-g applications, a single (3-axis) acceleration sample at the peak of an impact event contains sufficient information about the event, and the full acceleration history is not required. In this mode the device returns only the over threshold Peak Acceleration between two consecutive sample fetches. |
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Activity detection can be configured as referenced or absolute. When using absolute activity detection, acceleration samples are compared directly to a user set threshold to determine whether motion is present. In many applications, it is advantageous for activity detection to be based not on an absolute threshold, but on a deviation from a reference point or orientation. |
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SPI Interface |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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AHB clock divider |
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Enable driver for AK8975 magnetometer. |
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I2C address of the AK8975 sensor. Choose:
If the AK8975 sensor is part of a MPU9159 chip, the I2C address needs to be 0x0C. |
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Specify the device name of the I2C master device to which the AK8975 chip is connected. |
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Device name with which the AK8975 sensor is identified. |
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This module implements a kernel device driver for the Altera Avalon Interval Timer as described in the Embedded IP documentation, for use with Nios II and possibly other Altera soft CPUs. It provides the standard “system clock driver” interfaces. |
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Enable driver for AMG88XX infrared thermopile sensor. |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable driver for iAQ-core Digital VOC sensor. |
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Enable the LED strip driver for a chain of APA102 RGB LEDs. These are sold as DotStar by Adafruit and Superled by others. |
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Enable driver for APDS9960 sensors. |
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16x |
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1x |
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4x |
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64x |
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Enable Ambient Light Sense (ALS). |
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1x |
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2x |
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4x |
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8x |
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100% |
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150% |
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200% |
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300% |
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Proximity Pulse Count |
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16us |
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32us |
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4us |
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8us |
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Use global thread |
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No trigger |
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Use the “new” local APIC timer driver for the system timer. This is a replacement for the legacy local APIC timer driver which supports tickless operation, but not the Quark MVIC. |
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This option specifies the IRQ used by the local APIC timer. |
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This option specifies the IRQ priority used by the local APIC timer. |
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If your CPU supports invariant TSC, and you know the ratio of the TSC frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC (the local APIC timer frequency), then enable this for a much faster and more accurate z_timer_cycle_get_32(). |
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TSC to local APIC timer frequency divisor (M) |
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TSC to local APIC timer frequency multiplier (N) |
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Scan additional folders inside application source folder for application defined syscalls. |
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This priority level is for end-user drivers such as sensors and display which have no inward dependencies. |
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Add FS header files to the ‘app’ include path. It may be disabled if the include paths for FS are causing aliasing issues for ‘app’. |
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Add LVGL header files to the ‘app’ include path. It may be disabled if the include paths for LVGL are causing aliasing issues for ‘app’. |
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Add MBEDTLS header files to the ‘app’ include path. It may be disabled if the include paths for MBEDTLS are causing aliasing issues for ‘app’. |
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Add MCUMGR header files to the ‘app’ include path. It may be disabled if the include paths for MCUMGR are causing aliasing issues for ‘app’. |
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Add POSIX subsystem header files to the ‘app’ include path. |
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ARC architecture |
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System architecture string. |
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It’s possible that an architecture port cannot or does not want to use the provided k_busy_wait(), but instead must do something custom. It must enable this option in that case. |
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It’s possible that an architecture port cannot use _Swap() to swap to the _main() thread, but instead must do something custom. It must enable this option in that case. |
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Helper symbol to detect SoCs forgetting to select one of the arch symbols above. See the top-level CMakeLists.txt. |
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Debug |
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Error |
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Info |
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Off |
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Warning |
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POSIX (native) architecture |
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In bytes, stack size for Zephyr threads meant only for the POSIX architecture. (In this architecture only part of the thread status is kept in the Zephyr thread stack, the real stack is the native underlying pthread stack. Therefore the allocated stack can be limited to this size) |
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This option controls alignment size of generated _sw_isr_table. Some architecture needs a software ISR table to be aligned to architecture specific size. The default size is 0 for no alignment. |
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The ARCv2 interrupt unit has 16 allocated exceptions associated with vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255. The interrupt unit is optional in the ARCv2-based processors. When building a processor, you can configure the processor to include an interrupt unit. The ARCv2 interrupt unit is highly programmable. |
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This module implements a kernel device driver for the ARCv2 processor timer 0 and provides the standard “system clock driver” interfaces. |
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This option specifies the IRQ priority used by the ARC timer. Lower values have higher priority. |
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ARC is configured with ARC CONNECT which is a hardware for connecting multi cores. |
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ARC core MPU functionalities |
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Print human-readable information about exception vectors, cause codes, and parameters, at a cost of code/data size for the human-readable strings. |
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Size in bytes of exception handling stack which is at the top of interrupt stack to get smaller memory footprint because exception is not frequent. To reduce the impact on interrupt handling, especially nested interrupt, it cannot be too large. |
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Fast interrupts are supported (FIRQ). If FIRQ enabled, for interrupts with highest priority, status32 and pc will be saved in aux regs, other regs will be saved according to the number of register bank; If FIRQ is disabled, the handle of interrupts with highest priority will be same with other interrupts. |
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Use separate stack for FIRQ handing. When the fast irq is also a direct irq, this will get the minimal interrupt latency. |
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The size of firq stack. |
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Depending on the configuration, CPU can contain accumulator reg-pair (also referred to as r58:r59). These can also be used by gcc as GPR so kernel needs to save/restore per process |
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This option is enabled when ARC core supports secure mode |
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ARC is configured with STACK_CHECKING which is a mechanism for checking stack accesses and raising an exception when a stack overflow or underflow is detected. |
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Target has ARC MPU (currently only works for EMSK 2.2/2.3 ARCEM7D) |
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Enable MPU |
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ARC MPU has several versions. For MPU v2, the minimum region is 2048 bytes; For MPU v3, the minimum region is 32 bytes |
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This option indicates that we are building a Zephyr image that is intended to execute in normal mode. Execution of this image is triggered by secure firmware that executes in secure mode. The option is only applicable to ARC processors that implement the SecureShield. This option enables Zephyr to include code that executes in normal mode only, as well as to exclude code that is designed to execute only in secure mode. Code executing in normal mode has no access to secure resources of the ARC processors, and, therefore, it shall avoid accessing them. |
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This option indicates that we are building a Zephyr image that is intended to execute in secure mode. The option is only applicable to ARC processors that implement the SecureShield. This option enables Zephyr to include code that executes in secure mode, as well as to exclude code that is designed to execute only in normal mode. Code executing in secure mode has access to both the secure and normal resources of the ARC processors. |
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Use ARC STACK_CHECKING to do stack protection |
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This option enables either: - The ARC stack checking, or - the MPU-based stack guard to cause a system fatal error if the bounds of the current process stack are overflowed. The two stack guard options are mutually exclusive. The selection of the ARC stack checking is prioritized over the MPU-based stack guard. |
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ARC EM cores w/o secure shield 2+2 mode support might be configured to support unaligned memory access which is then disabled by default. Enable unaligned access in hardware and make software to use it. |
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ARM architecture |
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32-bit |
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36-bit |
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42-bit |
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48-bit |
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32-bit |
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36-bit |
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42-bit |
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48-bit |
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This option signifies the use of an ARMv6-M processor implementation, or the use of an ARMv8-M processor supporting the Baseline implementation. Notes: - A Processing Element (PE) without the Main Extension is also referred to as a Baseline Implementation. A Baseline implementation has a subset of the instructions, registers, and features, of a Mainline implementation. - ARMv6-M compatibility is provided by all ARMv8-M implementations. |
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This option specifies the size of the stack used by the undefined instruction and data abort exception handlers. |
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This option specifies the size of the stack used by the FIQ handler. |
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This option signifies the use of an ARMv7-M processor implementation, or the use of an ARMv8-M processor implementation supporting the Floating-Point Extension. |
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This option signifies the use of an ARMv7-M processor implementation, or the use of a backwards-compatible ARMv8-M processor implementation supporting the Main Extension. Notes: - A Processing Element (PE) with the Main Extension is also referred to as a Mainline Implementation. - ARMv7-M compatibility requires the Main Extension. From https://developer.arm.com/products/architecture/m-profile: The Main Extension provides backwards compatibility with ARMv7-M. |
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This option signifies the use of an ARMv7-R processor implementation. From https://developer.arm.com/products/architecture/cpu-architecture/r-profile: The Armv7-R architecture implements a traditional Arm architecture with multiple modes and supports a Protected Memory System Architecture (PMSA) based on a Memory Protection Unit (MPU). It supports the Arm (32) and Thumb (T32) instruction sets. |
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This option signifies the use of an ARMv7-R processor implementation supporting the Floating-Point Extension. |
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This option specifies the size of the stack used by the SVC handler. |
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This option specifies the size of the stack used by the system mode. |
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This option signifies the use of an ARMv8-A processor implementation. From https://developer.arm.com/products/architecture/cpu-architecture/a-profile: The Armv8-A architecture introduces the ability to use 64-bit and 32-bit Execution states, known as AArch64 and AArch32 respectively. The AArch64 Execution state supports the A64 instruction set, holds addresses in 64-bit registers and allows instructions in the base instruction set to use 64-bit registers for their processing. The AArch32 Execution state is a 32-bit Execution state that preserves backwards compatibility with the Armv7-A architecture and enhances that profile so that it can support some features included in the AArch64 state. It supports the T32 and A32 instruction sets. |
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This option signifies the use of an ARMv8-M processor implementation. ARMv8-M Baseline includes additional features not present in the ARMv6-M architecture. |
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This option signifies the use of an ARMv8-M processor implementation supporting the DSP Extension. |
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This option signifies the use of an ARMv8-M processor implementation, supporting the Main Extension. ARMv8-M Main Extension includes additional features not present in the ARMv7-M architecture. |
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This option signifies the use of an ARMv8-M processor implementation (Baseline or Mainline) supporting the Security Extensions. |
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This module implements a kernel device driver for the ARM architected timer which provides per-cpu timers attached to a GIC to deliver its per-processor interrupts via PPIs. |
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Configure Clock Config Device name |
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ARM clock divider |
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Library file to find the symbol table for the entry veneers. The library will typically come from building the Secure Firmware that contains secure entry functions, and allows the Non-Secure Firmware to call into the Secure Firmware. |
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Option indicates that ARM Secure Firmware contains Secure Entry functions that may be called from Non-Secure state. Secure Entry functions must be located in Non-Secure Callable memory regions. |
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Option indicates that ARM Non-Secure Firmware uses Secure Entry functions provided by the Secure Firmware. The Secure Firmware must be configured to provide these functions. |
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Memory Management Unit support. |
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MCU implements Memory Protection Unit. Notes: The ARMv6-M and ARMv7-M MPU architecture requires a power-of-two alignment of MPU region base address and size. The NXP MPU as well as the ARMv8-M MPU do not require MPU regions to have power-of-two alignment for base address and region size. The ARMv8-M MPU requires the active MPU regions be non-overlapping. As a result of this, the ARMv8-M MPU needs to fully partition the memory map when programming dynamic memory regions (e.g. PRIV stack guard, user thread stack, and application memory domains), if the system requires PRIV access policy different from the access policy of the ARMv8-M background memory map. The application developer may enforce full PRIV (kernel) memory partition by enabling the CONFIG_MPU_GAP_FILLING option. By not enforcing full partition, MPU may leave part of kernel SRAM area covered only by the default ARMv8-M memory map. This is fine for User Mode, since the background ARM map does not allow nPRIV access at all. However, since the background map policy allows instruction fetches by privileged code, forcing this Kconfig option off prevents the system from directly triggering MemManage exceptions upon accidental attempts to execute code from SRAM in XIP builds. Since this does not compromise User Mode, we make the skipping of full partitioning the default behavior for the ARMv8-M MPU driver. |
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Minimum size (and alignment) of an ARM MPU region. Use this symbol to guarantee minimum size and alignment of MPU regions. A minimum 4-byte alignment is enforced in ARM builds without support for Memory Protection. |
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This option indicates that we are building a Zephyr image that is intended to execute in Non-Secure state. Execution of this image is triggered by Secure firmware that executes in Secure state. The option is only applicable to ARMv8-M MCUs that implement the Security Extension. This option enables Zephyr to include code that executes in Non-Secure state only, as well as to exclude code that is designed to execute only in Secure state. Code executing in Non-Secure state has no access to Secure resources of the Cortex-M MCU, and, therefore, it shall avoid accessing them. |
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Start address of Non-Secure Callable section. Notes: - The default value (i.e. when the user does not configure the option explicitly) instructs the linker script to place the Non-Secure Callable section, automatically, inside the .text area. - Certain requirements/restrictions may apply regarding the size and the alignment of the starting address for a Non-Secure Callable section, depending on the available security attribution unit (SAU or IDAU) for a given SOC. |
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Force NMI, HardFault, and BusFault (in Mainline ARMv8-M) exceptions as Secure exceptions. |
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This option indicates that we are building a Zephyr image that is intended to execute in Secure state. The option is only applicable to ARMv8-M MCUs that implement the Security Extension. This option enables Zephyr to include code that executes in Secure state, as well as to exclude code that is designed to execute only in Non-secure state. Code executing in Secure state has access to both the Secure and Non-Secure resources of the Cortex-M MCU. Code executing in Non-Secure state may trigger Secure Faults, if Secure MCU resources are accessed from the Non-Secure state. Secure Faults may only be handled by code executing in Secure state. |
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This option enables either: - The built-in Stack Pointer limit checking, or - the MPU-based stack guard to cause a system fatal error if the bounds of the current process stack are overflowed. The two stack guard options are mutually exclusive. The selection of the built-in Stack Pointer limit checking is prioritized over the MPU-based stack guard. The developer still has the option to manually select the MPU-based stack guard, if this is desired. |
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Platform has support for ARM TrustZone-M. |
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Builds Zephyr with Address Sanitizer enabled. This is currently
only supported by boards based on the posix architecture, and requires a
recent-ish compiler with the Note that at exit leak detection is disabled for 64-bit boards when GCC is used due to potential risk of a deadlock in libasan. This behavior can be changes by adding leak_check_at_exit=1 to the environment variable ASAN_OPTIONS. |
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Override host OS dlclose() with a NOP. This NOP implementation is needed as workaround for a known limitation in LSAN (leak sanitizer) that if dlcose is called before performing the leak check, “<unknown module>” is reported in the stack traces during the leak check and these can not be suppressed, see https://github.com/google/sanitizers/issues/89 for more info. |
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This enables the __ASSERT() macro in the kernel code. If an assertion fails, the policy for what to do is controlled by the implementation of the assert_post_action() function, which by default will trigger a fatal error. Disabling this option will cause assertions to compile to nothing, improving performance and system footprint. |
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This option specifies the assertion level used by the __ASSERT() macro. It can be set to one of three possible values: Level 0: off Level 1: on + warning in every file that includes __assert.h Level 2: on + no warning |
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This option removes the assert condition from the printed assert message. Enabling this will save target code space, and thus may be necessary for tiny targets. It is recommended to disable condition info before disabling file info since the condition can be found in the source using file info. |
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This option removes the name and the path of the source file in which the assertion occurred. Enabling this will save target code space, and thus may be necessary for tiny targets. |
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This option removes the additional message from the printed assert. Enabling this will save target code space, and thus may be necessary for tiny targets. It is recommended to disable message before disabling file info since the message can be found in the source using file info. |
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Assert on errors covered with the CHECK macro. |
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This option enables printing an assert message with information about the assertion that occurred. This includes printing the location, the conditional expression and additional message specific to the assert. |
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Use the compiler builtin functions for atomic operations. This is the preferred method. However, support for all arches in GCC is incomplete. |
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Use atomic operations routines that are implemented entirely in C by locking interrupts. Selected by architectures which either do not have support for atomic operations in their instruction set, or haven’t been implemented yet during bring-up, and also the compiler does not have support for the atomic __sync_* builtins. |
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Use when there isn’t support for compiler built-ins, but you have written optimized assembly code under arch/ which implements these. |
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Enable support for Audio |
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Enable Audio Codec Driver Configuration |
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Audio codec device driver initialization priority. |
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Debug |
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Error |
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Info |
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Off |
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Warning |
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Enable Digital Microphone Driver Configuration |
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Audio Digital Microphone device driver initialization priority. |
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Debug |
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Error |
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Info |
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Off |
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Warning |
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Enable Intel digital PDM microphone driver |
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Enable MPXXDTYY microphone support on the selected board |
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Enable TLV320DAC support on the selected board |
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Enable base64 encoding and decoding functionality |
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Enable the battery sense circuit |
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This option tells the build system that the target system is big-endian. Little-endian architecture is the default and should leave this option unselected. This option is selected by arch/$ARCH/Kconfig, soc//Kconfig, or boards//Kconfig and the user should generally avoid modifying it. The option is used to select linker script OUTPUT_FORMAT and command line option for gen_isr_tables.py. |
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Bluetooth device class bulk endpoint size |
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Bluetooth device class interrupt endpoint size |
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Enable driver for BMA280 I2C-based triaxial accelerometer sensor family. |
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7.81Hz |
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15.63HZ |
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31.25Hz |
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62.5Hz |
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125Hz |
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250HZ |
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500Hz |
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unfiltered |
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+/-16g |
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+/-2g |
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+/-4g |
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+/-8g |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable driver for BMC150 I2C-based magnetometer sensor. |
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Enhanced regular (15, 27, 10) |
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High accuracy (47, 83, 20) |
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Low power (3, 3, 10) |
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Regular (9, 15, 10) |
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Enable alteration of sampling rate attribute at runtime. |
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Enable alteration of XY oversampling at runtime. |
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Enable alteration of Z oversampling at runtime. |
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Enable triggers for BMC150 magnetometer |
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Enable data ready interrupt for BMC150 magnetometer |
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Specify the internal thread stack size. |
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Enable driver for BME280 I2C-based or SPI-based temperature and pressure sensor. |
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16 |
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2 |
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4 |
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8 |
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filter off |
|
x16 |
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x1 |
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x2 |
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x4 |
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x8 |
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x16 |
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x1 |
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x2 |
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x4 |
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x8 |
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0.5ms |
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1000ms |
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125ms |
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2000ms BMP280 / 10ms BME280 |
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250ms |
|
4000ms BMP280 / 20ms BME280 |
|
500ms |
|
62.5ms |
|
x16 |
|
x1 |
|
x2 |
|
x4 |
|
x8 |
|
Enable driver for BME680 I2C-based based temperature, pressure, humidity and gas sensor. |
|
128 |
|
16 |
|
2 |
|
32 |
|
4 |
|
64 |
|
8 |
|
filter off |
|
197 |
|
1943 |
|
320 |
|
400 |
|
x16 |
|
x1 |
|
x2 |
|
x4 |
|
x8 |
|
x16 |
|
x1 |
|
x2 |
|
x4 |
|
x8 |
|
x16 |
|
x1 |
|
x2 |
|
x4 |
|
x8 |
|
Enable Bosch BMG160 gyroscope support. |
|
Fast bus speed of up to 400KHz. |
|
Standard bus speed of up to 100kHz. |
|
100 Hz |
|
1000 Hz |
|
200 Hz |
|
2000 Hz |
|
400 Hz |
|
Set at runtime. |
|
1000 DPS |
|
125 DPS |
|
2000 DPS |
|
250 DPS |
|
500 DPS |
|
Set at runtime. |
|
The priority of the thread used for handling interrupts. |
|
The thread stack size. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable Bosch BMI160 inertial measurement unit that provides acceleration and angular rate measurements. |
|
100 Hz |
|
1600 Hz |
|
200 Hz |
|
25 Hz |
|
1.56 Hz |
|
12.5 Hz |
|
0.78 Hz |
|
6.25 Hz |
|
3.125 Hz |
|
400 Hz |
|
50 Hz |
|
800 Hz |
|
Set at runtime. |
|
low power |
|
normal |
|
Set at runtime. |
|
suspended/not used |
|
16G |
|
2G |
|
4G |
|
8G |
|
Set at runtime. |
|
100 Hz |
|
1600 Hz |
|
200 Hz |
|
25 Hz |
|
3200 Hz |
|
400 Hz |
|
50 Hz |
|
800 Hz |
|
Set at runtime. |
|
fast start-up |
|
normal |
|
Set at runtime. |
|
suspended/not used |
|
1000 DPS |
|
125 DPS |
|
2000 DPS |
|
250 DPS |
|
500 DPS |
|
Set at runtime. |
|
The priority of the thread used for handling interrupts. |
|
The thread stack size. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for BMM150 I2C-based Geomagnetic sensor. |
|
Enhanced regular (15, 27, 10) |
|
High accuracy (47, 83, 20) |
|
Low power (3, 3, 10) |
|
Regular (9, 15, 10) |
|
Enable alteration of sampling rate attribute at runtime. |
|
Enable alteration of XY oversampling at runtime. |
|
Enable alteration of Z oversampling at runtime. |
|
This option holds the name of the board and is used to locate the files related to the board in the source tree (under boards/). The Board is the first location where we search for a linker.ld file, if not found we look for the linker file in soc/<arch>/<family>/<series> |
|
96Boards Argonkey |
|
96Boards Avenger96 Board |
|
96Boards Carbon (STM32F401) |
|
96Boards Carbon (nRF51) |
|
96Boards Meerkat96 board |
|
96Boards Neonkey |
|
96Boards Nitrogen |
|
96Boards STM32 Sensor Mezzanine Board |
|
96boards WisTrio Development Board |
|
ACRN User OS |
|
Actinius Icarus |
|
Actinius Icarus Non-Secure |
|
Adafruit Feather M0 Basic Proto |
|
Adafruit Trinket M0 |
|
Altera MAX10 Board |
|
Arduino Due Board |
|
Arduino Zero |
|
SAM D20 Xplained Pro |
|
SAM D21 Xplained Pro |
|
SAM E54 Xplained Pro |
|
SAM R21 Xplained Pro |
|
BBC MICRO:BIT |
|
BL652 DVK |
|
BL654 DVK |
|
STMicroelectronics B-L072Z-LRWAN1 Discovery kit |
|
TI CC1352R1 LaunchXL |
|
TI CC26x2R1 LaunchXL |
|
TI CC3220SF LAUNCHXL |
|
TI CC3235SF LAUNCHXL |
|
Initialization priority for the CCS_VDD power rail. This powers the CCS811 gas sensor. The value has to be greater than BOARD_VDD_PWR_CTRL_INIT_PRIORITY, but smaller than SENSOR_INIT_PRIORITY. |
|
Toradex Colibri iMX7 Dual |
|
PSoC6 WiFi-BT Pioneer Kit M0 |
|
PSoC6 WiFi-BT Pioneer Kit M4 |
|
Decawave DWM1001-DEV |
|
DEGU_EVK |
|
This hidden option is set in the board configuration and indicates the Zephyr release that the board configuration will be removed. When set, any build for that board will generate a clearly visible deprecation warning. |
|
Discovery IoT L475 Development Board |
|
Dragino LSN50 Sensor Node |
|
SiLabs EFM32GG-STK3701A (Giant Gecko 11) |
|
SiLabs EFM32HG-SLSTK3400A (Happy Gecko) |
|
SiLabs EFM32PG-STK3402A (Pearl Gecko) |
|
SiLabs EFM32PG-STK3402A (Jade Gecko) |
|
SiLabs EFM32WG-STK3800 (Wonder Gecko) |
|
SiLabs EFR32MG-SLTB004A (Thunderboard Sense 2) |
|
SiLabs EFR32-SLWSTK6061A (Flex Gecko) |
|
The ARC EM Software Development Platform (emsdp) is an FPGA based development platform intended to support ARC licenses in developing their software for the ARC EM processor family and ARC EM Subsystems. It has the support for ARC EM4, EM5D, EM6, EM7D, EM9D and EM11D processors. ARC EM Enhanced Security Package (ESP) and ARC EM Subsystems (DFSS, SCSS, DSS) are also supported. |
|
The DesignWare ARC EM Starter Kit board is a board that can host up to 3 different SOC FPGA bit files. Both version 2.2 and 2.3 firmware have EM7D, EM9D and EM11D configurations. EM9D using CCM memories and is a Harvard Architecture. EM7D and EM11D have access to 128MB DRAM and use i-cache and d-cache. EM7D of EMSK 2.3 supports secure mode. |
|
2.2 |
|
2.3 |
|
Enable DCDC mode |
|
Enable Application MCU DCDC converter |
|
Enable High Voltage DCDC converter |
|
Enable Network MCU DCDC converter |
|
ESP32 Development Board |
|
NXP FRDM-K22F |
|
Freescale FRDM-K64F |
|
NXP FRDM-K82F |
|
NXP FRDM-KL25Z |
|
NXP FRDM-KW41Z |
|
Google Kukui EC |
|
Gordon Peak MRB |
|
If selected, applications are linked so that they can be loaded by Nordic nRF5 bootloader. |
|
NXP Hexiwear K64 |
|
Hexiwear KW40Z |
|
HiFive1 target |
|
HiFive1 Rev B target |
|
Holyiot YJ-16019 |
|
The DesignWare ARC HS Development Kit is a ready-to-use platform for rapid software development on the ARC HS3x family of processors. It supports single- and multi-core ARC HS34, HS36 and HS38 processors and offers a wide range of interfaces |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Board initialization priority. This must be bigger than GPIO_GECKO_COMMON_INIT_PRIORITY. |
|
Xtensa on Intel_S1000 |
|
The DesignWare ARC IoT Development Kit board is a versatile platform that includes the necessary hardware and software to accelerate software development and debugging of sensor fusion, voice recognition and face detection designs. It includes a silicon implementation of the ARC Data Fusion IP Subsystem running at 144 MHz on SMIC’s 55-nm ultra-low power process, and a rich set of peripherals commonly used in IoT designs such as USB, UART, SPI, I2C, PWM, SDIO and ADCs. |
|
Board with LiteX/VexRiscV CPU |
|
NXP LPCXPRESSO-54114 M0 |
|
NXP LPCXPRESSO-54114 M4 |
|
NXP LPCXPRESSO-55S69 [CPU0] |
|
NXP LPCXPRESSO-55S69 [CPU1] |
|
Microsemi M2GL025 IGLOO2 dev board with Mi-V CPU |
|
Microchip MEC1501 Modular ASSY 6885 Development board |
|
Microchip MEC15XX EVB ASSY 6853 Development board |
|
Microchip MEC2016 EVB ASSY 6797 Development board |
|
Mikroe MINI-M4 for STM32 Board |
|
NXP MIMXRT1010-EVK |
|
NXP MIMXRT1015-EVK |
|
NXP MIMXRT1020-EVK |
|
NXP MIMXRT1050-EVK |
|
NXP MIMXRT1050-EVK-QSPI |
|
NXP MIMXRT1060-EVK |
|
NXP MIMXRT1060-EVK-HYPERFLASH |
|
NXP MIMXRT1064-EVK |
|
MinnowBoard Max |
|
MM MM-SWIFTIO |
|
ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385) |
|
ARM Cortex-M33 SMM on V2M-MPS2 (AN521) |
|
TI MSP-EXP432P401R LAUNCHXL |
|
ARM Cortex-M33 SMM on V2M-MUSCA |
|
ARM Cortex-M33 SMM on V2M-MUSCA |
|
Will produce a console Linux process which can be executed natively as a 32-bit executable. It provides some minimal needed models: An interrupt controller, timer (system tick), and redirects kernel prints to stdout. |
|
Will produce a console Linux process which can be executed natively as a 64-bit executable. It provides some minimal needed models: An interrupt controller, timer (system tick), and redirects kernel prints to stdout. |
|
nRF51 BLE400 |
|
nRF51 BLENANO |
|
nRF51 PCA10028 |
|
nRF51 PCA10031 |
|
nRF51 VBLUno51 BLE |
|
nRF52810 PCA10040 |
|
nRF52811 PCA10056 |
|
nRF52832-MDK |
|
NRF52833 PCA10100 |
|
Electronut Labs Blip |
|
Use a GPIO pin to reset the nRF52840 controller and let it wait until all bytes traveling to the H4 device have been received and drained, thus ensuring communication can begin correctly. |
|
GPIO pin on the nRF9160 used to reset the nRF52840. |
|
NRF52840-MDK |
|
NRF52840 PAPYR |
|
NRF52840 PCA10056 |
|
NRF52840 PCA10059 |
|
NRF52840 PCA10090 |
|
nRF52 ADAFRUIT FEATHER |
|
nRF52 BLENANO2 |
|
Will produce a console Linux process which can be executed natively. It needs the BabbleSim simulator both in compile time and to execute |
|
nRF52 PCA10040 |
|
nRF52 PCA20020 |
|
nRF52 SPARKFUN |
|
nRF52 VBLUno52 |
|
nRF5340 DK nRF5340 Application MCU |
|
nRF5340 DK nRF5340 Application MCU non-secure |
|
nRF5340 DK NRF5340 Network MCU |
|
nRF9160 PCA10090 |
|
nRF9160 PCA10090 non-secure |
|
The DesignWare ARC nSIM board is a virtual board based on the ARC nSIM simulator. It demonstrates the ARC core features and a console based on the legacy ARC UART model. |
|
NUCLEO-64 F030R8 Development Board |
|
NUCLEO-64 F070RB Development Board |
|
NUCLEO-64 F091RC Development Board |
|
NUCLEO-64 F103RB Development Board |
|
NUCLEO-144 F207ZG Development Board |
|
NUCLEO-64 F302R8 Development Board |
|
NUCLEO-64 F334R8 Development Board |
|
NUCLEO-64 F401RE Development Board |
|
NUCLEO-64 F411RE Development Board |
|
NUCLEO-144 F412ZG Development Board |
|
NUCLEO-144 F413ZH Development Board |
|
NUCLEO-144 F429ZI Development Board |
|
Nucleo F446RE Development Board |
|
Nucleo F746ZG Development Board |
|
Nucleo F756ZG Development Board |
|
Nucleo F767ZI Development Board |
|
NUCLEO-64 G071RB Development Board |
|
Nucleo G431RB Development Board |
|
Nucleo G474RE Development Board |
|
NUCLEO-64 L053R8 Development Board |
|
NUCLEO-64 L073RZ Development Board |
|
NUCLEO-64 L152RE Development Board |
|
Nucleo L432KC Development Board |
|
Nucleo L452RE Development Board |
|
Nucleo L476RG Development Board |
|
Nucleo L496ZG Development Board |
|
Nucleo L4R5ZI Development Board |
|
Nucleo WB55RG Development Board |
|
ODROID-GO Game Kit |
|
OLIMEXINO-STM32 Development Board |
|
OLIMEX-STM32-E407 Development Board |
|
OLIMEX-STM32-H407 Development Board |
|
OLIMEX-STM32-P405 Development Board |
|
Particle Argon Board |
|
Particle Boron Board |
|
Particle Xenon Board |
|
Route to Arduino pins |
|
Route to buttons on the kit |
|
Route to Arduino pins |
|
Route to buttons on the kit |
|
Pin 0: nRF9160 P0.17 connects to A3 Pin 1: nRF9160 P0.18 connects to A4 Pin 2: nRF9160 P0.19 connects to A5 |
|
This connects the following pins on the nRF9160 to pins on the nRF52840: Pin 0: nRF9160 P0.17 connects to nRF52840 P0.17 Pin 1: nRF9160 P0.18 connects to nRF52840 P0.20 Pin 2: nRF9160 P0.19 connects to nRF52840 P0.15 |
|
Pin 3: nRF9160 P0.21 connects to nRF52840 P0.22 Pin 4: nRF9160 P0.22 connects to nRF52840 P1.04 Pin 5: nRF9160 P0.23 connects to nRF52840 P1.02 |
|
Pin 3: nRF9160 P0.21 connects to TRACECLK Pin 4: nRF9160 P0.22 connects to TRACEDATA0 Pin 5: nRF9160 P0.23 connects to TRACEDATA1 |
|
Pin 6: nRF9160 COEX0 connects to COEX0_PH Pin 7: nRF9160 COEX1 connects to COEX1_PH Pin 8: nRF9160 COEX2 connects to COEX2_PH |
|
Pin 6: nRF9160 COEX0 connects to nRF52840 P1.13 Pin 7: nRF9160 COEX1 connects to nRF52840 P1.11 Pin 8: nRF9160 COEX2 connects to nRF52840 P1.15 |
|
Route to Arduino pins |
|
Route to LED on the kit |
|
Route to Arduino pins |
|
Route to LED on the kit |
|
Route to Arduino pins |
|
Route to LED on the kit |
|
Route to Arduino pins |
|
Route to LED on the kit |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Let the nRF52840 be reset from the nRF9160 via a GPIO line. The GPIO line may only be one of the first 6 MCU interface pins. The line is active high. |
|
Pin P0.15 on nRF52840, connected to P0.19 on the nRF9160. |
|
Pin P0.17 on nRF52840, connected to P0.17 on the nRF9160. |
|
Pin P0.20 on nRF52840, connected to P0.18 on the nRF9160. |
|
Pin P0.22 on nRF52840, connected to P0.21 on the nRF9160. |
|
Pin P1.02 on nRF52840, connected to P0.23 on the nRF9160. |
|
Pin P1.04 on nRF52840, connected to P0.22 on the nRF9160. |
|
Route to Arduino pins |
|
Route to switches on the kit |
|
Route to Arduino pins |
|
Route to switches on the kit |
|
Route to Arduino pins |
|
Route to VCOM0 |
|
Route to Arduino pins |
|
Route to VCOM2 |
|
Pico-PI iMX7D Dual |
|
Cortex-A53 Emulation (QEMU) |
|
Cortex-M0 Emulation (QEMU) |
|
Cortex-M3 Emulation (QEMU) |
|
Cortex-R5 Emulation (QEMU) |
|
QEMU NIOS II target |
|
QEMU RISCV32 target |
|
QEMU RISCV64 target |
|
QEMU x86 |
|
QEMU x86_64 |
|
Xtensa emulation using QEMU |
|
reel board equipped with GDEH0213B1 display |
|
reel board equipped with GDEH0213B72 display |
|
RV32M1 RISC-V cores |
|
Atmel SAM4E Xplained Pro |
|
Atmel SAM4S Xplained |
|
Atmel SMART SAM E70 Xplained Board |
|
Atmel SMART SAM V71 Xplained Ultra Board |
|
Use the external SIM for communication, instead of the eSIM |
|
SensorTile.box Development Board |
|
STM32 Flight Controller Unit |
|
STM3210C-EVAL Evaluation Board |
|
STM32373C_EVAL Evaluation Board |
|
STM32F030 DEMO Board |
|
STM32F072B-DISCO Development Board |
|
STM32F072-EVAL Development Board |
|
STM32F0DISCOVERY Development Board |
|
STM32F3DISCOVERY Development Board |
|
STM32F411E-DISCO Development Board |
|
STM32F412G-DISCO Development Board |
|
STM32F429I-DISC1 Development Board |
|
STM32F469I-DISCO Development Board |
|
STM32F4DISCOVERY Development Board |
|
STM32F723E Discovery Development Board |
|
STM32F746G Discovery Development Board |
|
STM32F769I Discovery Development Board |
|
STM32G0316 Discovery Development Board |
|
STM32H747I Discovery Development Board |
|
STM32H747I Discovery Development Board |
|
STM32L1DISCOVERY Development Board |
|
STM32L476G Discovery Development Board |
|
STM32L496G Discovery Development Board |
|
STM32MP157C Discovery Development 2 Board |
|
STM32VLDISCOVERY Development Board |
|
STM32 Minimum Development Board (Black) |
|
STM32 Minimum Development Board (Blue) |
|
NXP TWR-KE18F |
|
Enable the CLKOUT signal on FlexIO header pin 7 (PTE10). |
|
Use PTE6 as dedicated SPI_0 PCS2 chip select |
|
Use PTD3 as dedicated SPI_1 PCS0 chip select |
|
Use PTA16 as dedicated SPI_1 PCS2 chip select |
|
NXP TWR-KV58F220M |
|
UDOO Neo Full |
|
UP Squared |
|
Xtensa on Up Squared |
|
NXP USB-KW24D512 |
|
ARM V2M Beetle Board |
|
Broadcom Valkyrie BCM958401M2 |
|
Initialization priority for the VDD power rail. Has to be greater than GPIO_NRF_INIT_PRIORITY. |
|
WaRP7 iMX7 Solo |
|
Xtensa Development ISS |
|
Xtensa Development ISS |
|
This option signifies that the target has a bootloader that restores CPU context upon resuming from deep sleep power state. |
|
This option signifies that the target has options of bootloaders that support context restore upon resume from deep sleep |
|
This option will trigger the compilation of the ESP-IDF bootloader inside the build folder. At flash time, the bootloader will be flashed with the zephyr image |
|
This option signifies that Linux boots the kernel using kexec system call and utility. This method is used to boot the kernel over the network. |
|
This option signifies that the target uses MCUboot as a bootloader, or in other words that the image is to be chain-loaded by MCUboot. This sets several required build system and Device Tree options in order for the image generated to be bootable using the MCUboot open source bootloader. Currently this includes:
|
|
This option specifies the amount of SRAM (measure in kB) reserved for a bootloader image, when either: - the Zephyr image itself is to act as the bootloader, or - Zephyr is a !XIP image, which implicitly assumes existence of a bootloader that loads the Zephyr !XIP image onto SRAM. |
|
This option outputs a banner to the console device during boot up. |
|
This option delays bootup for the specified amount of milliseconds. This is used to allow serial ports to get ready before starting to print information on them during boot, as some systems might boot to fast for a receiving endpoint to detect the new USB serial bus, enumerate it and get ready to receive before it actually gets data. A similar effect can be achieved by waiting for DCD on the serial port–however, not all serial ports have DCD. |
|
FlexSPI serial NAND |
|
FlexSPI serial NOR |
|
SEMC parallel NAND |
|
SEMC parallel NOR |
|
This option enables the recording of timestamps during system boot. |
|
Untrusted parameters from user mode may be used in system calls to index arrays during speculative execution, also known as the Spectre V1 vulnerability. When enabled, various macros defined in misc/speculation.h will insert fence instructions or other appropriate mitigations after bounds checking any array index parameters passed in from untrusted sources (user mode threads). When disabled, these macros do nothing. |
|
This option enables Bluetooth support. |
|
This option enables the A2DP profile |
|
Number of buffers available for incoming ACL data. |
|
Maximum supported advertising sets. |
|
Use a custom Bluetooth assert implementation instead of the kernel-wide __ASSERT() when CONFIG_ASSERT is disabled. |
|
When CONFIG_BT_ASSERT is enabled, this option makes the code call k_panic() instead of k_oops() when an assertion is triggered. |
|
When CONFIG_BT_ASSERT is enabled, this option turns on printing the cause of the assert to the console using printk(). |
|
Enforce flow control rules on incoming PDUs, preventing a peer from sending new requests until a previous one has been responded or sending a new indication until a previous one has been confirmed. This may need to be disabled to avoid potential race conditions arising from a USB based HCI transport that splits HCI events and ACL data to separate endpoints. |
|
Number of buffers available for ATT prepare write, setting this to 0 disables GATT long/reliable writes. |
|
Number of ATT PDUs that can be at a single moment queued for transmission. If the application tries to send more than this amount the calls will block until an existing queued PDU gets sent. |
|
Initiate PHY Update Procedure on connection establishment. Disable this if you want PHY Update Procedure feature supported but want to rely on remote device to initiate the procedure at its discretion. |
|
This option enables Bluetooth AVDTP support |
|
Scan interval used for background scanning in 0.625 ms units |
|
Scan window used for background scanning in 0.625 ms units |
|
Enable support for devices compatible with the BlueNRG Bluetooth Stack. Current driver supports: ST BLUENRG-MS. |
|
This option enables support for Bondable Mode. In this mode, Bonding flag in AuthReq of SMP Pairing Request/Response will be set indicating the support for this mode. |
|
When this option is enabled remote devices are required to always set the bondable flag in their pairing request. Any other kind of requests will be rejected. |
|
This option enables Bluetooth BR/EDR support |
|
Select this for LE Broadcaster role support. |
|
Select this for LE Central role support. |
|
Set the Bluetooth Company Identifier for this device. The Linux Foundation’s Company Identifier (0x05F1) is the default value for this option although silicon vendors and hardware manufacturers can set their own. Note that the controller’s Company Identifier is controlled by BT_CTLR_COMPANY_ID. The full list of Bluetooth Company Identifiers can be found here: https://www.bluetooth.com/specifications/assigned-numbers/company-identifiers |
|
The value is a timeout used by peripheral device to wait until it starts the connection parameters update procedure to change default connection parameters. The default value is set to 5s, to comply with BT protocol specification: Core 4.2 Vol 3, Part C, 9.3.12.2 |
|
Maximum number of pending TX buffers that have an associated callback. Normally this can be left to the default value, which is equal to the number of TX buffers in the stack-internal pool. |
|
Timeout for pending LE Create Connection command in seconds |
|
Enables support for SoC native controller implementations. |
|
Makes advanced features visible to controller developers. |
|
Enable support for Bluetooth 5.0 LE Advertising Extensions in the Controller. |
|
Generate events indicating on air advertisement events. |
|
This option enables an application-defined sink for the controller assertion mechanism. This must be defined in application code as void “bt_ctlr_assert_handle(char *, int)” and will be invoked whenever the controller code encounters an unrecoverable error. |
|
Enable support for Bluetooth 5.0 LE Channel Selection Algorithm #2 in the Controller. |
|
Set the Bluetooth Company Identifier that will be used in the VERSION_IND PDU. Uses BT_COMPANY_ID by default, although silicon vendors and hardware manufacturers can set their own Company Identifier for the controller. The full list of Bluetooth Company Identifiers can be found here: https://www.bluetooth.com/specifications/assigned-numbers/company-identifiers |
|
Enables vendor specific per-connection meta data as part of the LLL connection object. |
|
Enable support for Bluetooth v4.1 Connection Parameter Request feature in the Controller. |
|
Enable connection RSSI measurement. |
|
Use random number generation and AES encryption support functions provided by the controller. |
|
Enable support for Bluetooth v4.2 LE Data Length Update procedure, up to 251 byte cleartext payloads in the Controller. Encrypted connections are not supported. |
|
Set the maximum data length of PDU supported in the Controller. |
|
Turn on debug GPIO toggling for the BLE Controller. This is useful when debugging with a logic analyzer or profiling certain sections of the code. |
|
Enable support for Direct Test Mode in the Controller. |
|
Enable support for Direct Test Mode over the HCI transport. |
|
Set the number of unique BLE addresses that can be filtered as duplicates while scanning. |
|
Enable support for Bluetooth v4.1 Extended Reject Indication feature in the Controller. |
|
Enable support for Bluetooth v4.2 LE Extended Scanner Filter Policies in the Controller. |
|
Enable connection encryption setup in 3 connection intervals. Peripheral will respond to Encryption Request with Encryption Response in the same connection interval, and also, will respond with Start Encryption Response PDU in the 3rd connection interval, hence completing encryption setup in 3 connection intervals. Encrypted data would be transmitted as fast as in 3rd connection interval from the connection establishment. Maximum CPU time in Radio ISR will increase if this feature is selected. |
|
Enable support for controller device whitelist feature |
|
Enable GPIO interface to a Low Noise Amplifier. This allows hardware designs using LNAs to let the Controller toggle their state based on radio activity. |
|
Time before Rx ready to turn on LNA. |
|
GPIO Pin number connected to a Low Noise Amplifier. |
|
Enable inverted polarity (active low) for the LNA pin. |
|
Enable GPIO interface to a Power Amplifier. This allows hardware designs using PA to let the Controller toggle their state based on radio activity. |
|
Time before Tx ready to turn on PA. |
|
GPIO Pin number connected to a Power Amplifier. |
|
Enable inverted polarity (active low) for the PA pin. |
|
User-defined string that will be returned by the Zephyr VS Read Build Information command after the Zephyr version and build time. When setting this to a value different from an empty string, a space character is required at the beginning to separate it from the already included information. |
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The interrupt priority for Ticker’s Job (SWI4) IRQ. This value shall be greater than or equal to the Ticker’s Worker IRQ priority value. |
|
Enable support for Bluetooth v4.0 LE Encryption feature in the Controller. |
|
Enable support for Bluetooth v4.1 LE Ping feature in the Controller. |
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Set the number connections for which worst-case buffer requirements for LLCP procedures must be met. Executing LLCP procedures on more than this number of connections simultaneously may cause instabilities. |
|
Handle zero length L2CAP start frame. |
|
The interrupt priority for event preparation and radio IRQ. |
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Use low latency non-negotiating event preemption. This reduces Radio ISR latencies by the controller event scheduling framework. Consequently, this reduces on-air radio utilization due to redundant radio state switches. |
|
Low latency ULL implementation that uses tailchaining instead of while loop to demux rx messages from LLL. |
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Set the number of unique Mesh Scan Filters available as part of the Intel Mesh Vendor Specific Extensions. |
|
Set the number of unique Mesh Scan Filter patterns available per Scan Filter as part of the Intel Mesh Vendor Specific Extensions. |
|
Enable support for Bluetooth 5.0 Minimum Number of Used Channels Procedure in the Controller. |
|
Optimize compilation of controller for execution speed. |
|
Enable code checking HCI Command Parameters. This is not needed in combined host plus controller builds, saving some code space. |
|
Select the nRF5 GPIOTE channel to use for PA/LNA GPIO feature. |
|
Enable support for Bluetooth 5.0 2Mbps PHY in the Controller. |
|
Enable support for Nordic Semiconductor proprietary 2Mbps PHY in the Controller. Encrypted connections are not supported. |
|
Enable support for Bluetooth 5.0 Coded PHY in the Controller. |
|
Enable support for Bluetooth v4.2 LE Controller-based Privacy feature in the Controller. |
|
Turn on measurement of radio ISR latency, CPU usage and generation of controller event with these profiling data. The controller event contains current, minimum and maximum ISR entry latencies; and current, minimum and maximum ISR CPU use in micro-seconds. |
|
Enable use of fast radio ramp-up mode. |
|
Set the size of the Resolving List for LE Controller-based Privacy. On nRF5x-based controllers, the hardware imposes a limit of 8 devices. |
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Set the size of the Known Unknown Resolving List for LE Controller-based Software deferred Privacy. |
|
Set the number of Rx PDUs to be buffered in the controller. In a 7.5ms connection interval and 2M PHY, maximum 18 packets with L2CAP payload size of 1 byte can be received. |
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Hold enqueue of Procedure Complete events with instant until after the on-air instant is reached. |
|
Enable RX pdu meta data |
|
High priority Rx thread stack size |
|
Generate events indicating on air scanner events. |
|
Generate events notifying the on air scan requests received. |
|
Measure RSSI of the on air scan requests received. |
|
Enable non-overlapping placement of observer, initiator and master roles in timespace. Uses window offset in connection updates and uses connection parameter request in slave role to negotiate non-overlapping placement with active master roles to avoid slave roles drifting into active master roles in the local controller. This feature maximizes the average data transmission amongst active concurrent master and slave connections while other observer, initiator, master or slave roles are active in the local controller. Disabling this feature will lead to overlapping role in timespace leading to skipped events amongst active roles. |
|
Enable use of settings system in controller. |
|
Enable support for Bluetooth v4.1 Slave-initiated Features Exchange feature in the Controller. |
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Enable support for Bluetooth 5.0 SMI RX in the Controller. |
|
Enable support for Bluetooth 5.0 SMI TX in the Controller. |
|
Enable support for Bluetooth 5.0 SMI TX through a system setting. |
|
Set the Subversion Number that will be used in VERSION_IND PDU. |
|
Enable support for software based deferred privacy calculations. |
|
Implement the tIFS Trx SW switch with the same TIMER instance, as the one used for BLE event timing. Requires SW switching be enabled. Using a single TIMER: (+) frees up one TIMER instance (+) removes jitter for HCTO implementation (-) introduces drifting to the absolute time inside BLE events, that increases linearly with the number of packets exchanged in the event (-) makes it impossible to use most of the pre-programmed PPI channels for the controller, resulting in 4 channels less left for other uses |
|
Enable use of hardware accelerated tIFS Trx switching. |
|
This option specifies the name of UART device to be used to connect to an external Bluetooth Host when Zephyr is acting as a Bluetooth Controller. |
|
Set the number of Tx PDUs to be queued for transmission in the controller. In a 7.5ms connection interval and 2M PHY, maximum 19 packets can be enqueued, with 18 packets with L2CAP payload size of 1 byte can be acknowledged. |
|
Size of the Tx buffers and the value returned in HCI LE Read Buffer Size command response. If this size if greater than effective PDU size then controller will perform fragmentation before transmitting on the the packet on air. Maximum is set to 251 due to implementation limitations (use of u8_t for length field in PDU buffer structure). |
|
0 dBm |
|
Enable dynamic control of Tx power per role/connection. Provides HCI VS commands to set and get the current Tx power on an individual role/connection basis. |
|
-12 dBm |
|
-16 dBm |
|
-20 dBm |
|
-30 dBm |
|
-4 dBm |
|
-40 dBm |
|
-8 dBm |
|
+2 dBm |
|
+3 dBm |
|
+4 dBm |
|
+5 dBm |
|
+6 dBm |
|
+7 dBm |
|
+8 dBm |
|
Avoid retransmission of a PDU if peer device Nack-ed a transmission in the current connection event, close the connection event so as to save current consumption on retries (in case peer has no buffers to receive new PDUs). Enabling this will lower power consumption, but increase transmission latencies by one connection interval as the next attempt to send a PDU would happen in the next connection event instead of repeated retries in the current connection event. |
|
The interrupt priority for Ticker’s Worker IRQ and Upper Link Layer higher priority functions. |
|
The interrupt priority for Ticker’s Job IRQ and Upper Link Layer lower priority functions. |
|
Number of event types reserved for proprietary use. The range is typically used when BT_CTLR_USER_EXT is in use. |
|
Catch-all for enabling proprietary event types in Controller behavior. |
|
Number of ticker ids reserved for proprietary use. The range is typically used when BT_CTLR_USER_EXT is in use. |
|
Make the controller’s Company Id and Subversion Number configurable through settings system. |
|
The interrupt priority for event preparation and radio IRQ. This value shall be less than or equal to the Ticker’s Job priority value. |
|
Enables advanced event preparation offset ahead of radio tx/rx, taking into account predictive processing time requirements in preparation to the event, like control procedure handling and CPU execution speeds. Crystal oscillator is retained between closely spaced consecutive radio events to reduce the overall number of crystal settling current consumptions. This feature maximizes radio utilization in an average role event timeslice when they are closely spaced by using a reduced offset between preparation and radio event. By disabling this feature, the controller will use a constant offset between the preparation and radio event. The controller will toggle crystal oscillator between two closely spaced radio events leading to higher average current due to increased number of crystal settling current consumptions. |
|
Configure the optimal delta in micro seconds between two consecutive radio events, event done to next preparation, below which (active clock) crystal will be retained. This value is board dependent. |
|
Enable support for use of Zero Latency IRQ feature. Note, applications shall not use Zero Latency IRQ themselves when this option is selected, else will impact controller stability. |
|
Select a custom, non-HCI based stack. If you’re not sure what this is, you probably want the HCI-based stack instead. |
|
Enable support for Bluetooth v4.2 LE Data Length Update procedure. |
|
This option enables debug support for the Bluetooth A2DP profile. |
|
This option enables debug support for the Bluetooth Attribute Protocol (ATT). |
|
This option enables debug support for the Bluetooth AVDTP. |
|
This option enables debug support for Bluetooth connection handling. |
|
This option enables debug support for the Bluetooth Generic Attribute Profile (GATT). |
|
This option enables debug support for Bluetooth HCI core. |
|
This option enables debug support for the active Bluetooth HCI driver, including the Controller-side HCI layer when included in the build. |
|
This option enables debug support for the Bluetooth Hands Free Profile (HFP). |
|
This option enables debug support for the handling of Bluetooth security keys. |
|
This option enables debug support for the Bluetooth L2ACP layer. |
|
This option enables Bluetooth debug going to standard serial console. |
|
Use a custom logging protocol over the console UART instead of plain-text output. Requires a special application on the host side that can decode this protocol. Currently the ‘btmon’ tool from BlueZ is capable of doing this. If the target board has two or more external UARTs it is possible to keep using UART_CONSOLE together with this option, however if there is only a single external UART then UART_CONSOLE needs to be disabled (in which case printk/printf will get encoded into the monitor protocol). |
|
Select this to disable all Bluetooth debug logs. |
|
This option enables debug support for the Bluetooth RFCOMM layer. |
|
This option enables debug support for the Bluetooth Resolvable Private Address (RPA) generation and resolution. |
|
This option enables debug support for the Bluetooth Service Discovery Protocol (SDP). |
|
This option enables debug support for the Bluetooth Services. |
|
This option enables debug support for Bluetooth storage. |
|
This option enables debug support for the Bluetooth Security Manager Protocol (SMP). |
|
Bluetooth device appearance. For the list of possible values please consult the following link: https://www.bluetooth.com/specifications/assigned-numbers |
|
Bluetooth device name. Name can be up to 248 bytes long (excluding NULL termination). Can be empty string. |
|
Enabling this option allows for runtime configuration of Bluetooth device name. |
|
Enabling this option allows remote GATT clients to write to device name GAP characteristic. |
|
Bluetooth device name storage size. Storage can be up to 248 bytes long (excluding NULL termination). |
|
Number of buffers in a separate buffer pool for events which the HCI driver considers discardable. Examples of such events could be e.g. Advertising Reports. The benefit of having such a pool means that the if there is a heavy inflow of such events it will not cause the allocation for other critical events to block and may even eliminate deadlocks in some cases. |
|
Size of buffers in the separate discardable event buffer pool. The minimum size is set based on the Advertising Report. Setting the buffer size different than BT_RX_BUF_LEN can save memory. |
|
This option adds support for ECDH HCI commands. |
|
With this option enabled, the application will be able to call the bt_passkey_set() API to set a fixed passkey. If set, the pairing_confim() callback will be called for all incoming pairings. |
|
This option if enabled allows automatically sending request for connection parameters update after GAP recommended 5 seconds of connection as peripheral. |
|
This allows to configure peripheral preferred connection parameters. Enabling this option results in adding PPCP characteristic in GAP. If disabled it is up to application to set expected connection parameters. |
|
Enable GATT Battery service |
|
Sets log level for the Battery service. Levels are: 0 OFF, do not write 1 ERROR, only write LOG_ERR 2 WARNING, write LOG_WRN in addition to previous level 3 INFO, write LOG_INF in addition to previous levels 4 DEBUG, write LOG_DBG in addition to previous levels |
|
This option enables support for GATT Caching. When enabled the stack will register Client Supported Features and Database Hash characteristics which can be used by clients to detect if anything has changed on the GATT database. |
|
This option enables support for the GATT Client role. |
|
Enable GATT Device Information service |
|
Enable Firmware Revision characteristic in Device Information Service. |
|
Enable firmware revision characteristic in Device Information Service. |
|
Enable Hardware Revision characteristic in Device Information Service. |
|
Enable hardware revision characteristic in Device Information Service. |
|
The device manufacturer inside Device Information Service. |
|
The device model inside Device Information Service. |
|
Enable PnP_ID characteristic in Device Information Service. |
|
The Product ID field is intended to distinguish between different products made by the vendor identified with the Vendor ID field. The vendors themselves manage Product ID field values. |
|
The Product Version field is a numeric expression identifying the device release number in Binary-Coded Decimal. This is a vendor-assigned value, which defines the version of the product identified by the Vendor ID and Product ID fields. This field is intended to differentiate between versions of products with identical Vendor IDs and Product IDs. The value of the field value is 0xJJMN for version JJ.M.N (JJ - major version number, M - minor version number, N - sub-minor version number); e.g., version 2.1.3 is represented with value 0x0213 and version 2.0.0 is represented with a value of 0x0200. When upward-compatible changes are made to the device, it is recommended that the minor version number be incremented. If incompatible changes are made to the device, it is recommended that the major version number be incremented. The sub-minor version is incremented for bug fixes. |
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The Vendor ID field is intended to uniquely identify the vendor of the device. This field is used in conjunction with Vendor ID Source field, which determines which organization assigned the Vendor ID field value. Note: The Bluetooth Special Interest Group assigns Device ID Vendor ID, and the USB Implementers Forum assigns Vendor IDs, either of which can be used for the Vendor ID field value. Device providers should procure the Vendor ID from the USB Implementers Forum or the Company Identifier from the Bluetooth SIG. |
|
The Vendor ID Source field designates which organization assigned the value used in the Vendor ID field value. The possible values are: - 1 Bluetooth SIG, the Vendor ID was assigned by the Bluetooth SIG - 2 USB IF, the Vendor ID was assigned by the USB IF |
|
Enable Serial Number characteristic in Device Information Service. |
|
Enable Serial Number characteristic in Device Information Service. |
|
Enable Settings usage in Device Information Service. |
|
Bluetooth DIS string storage size. Storage can be up to 248 bytes long (excluding NULL termination). |
|
Enable Software Revision characteristic in Device Information Service. |
|
Enable software revision characteristic in Device Information Service. |
|
This option enables registering/unregistering services at runtime. |
|
When enable this option blocks notification and indications to client to conform to the following statement from the Bluetooth 5.1 specification: ‘…the server shall not send notifications and indications to such a client until it becomes change-aware.” In case the service cannot deal with sudden errors (-EAGAIN) then it shall not use this option. |
|
Enable GATT Heart Rate service |
|
Sets log level for the Heart Rate service. Levels are: 0 OFF, do not write 1 ERROR, only write LOG_ERR 2 WARNING, write LOG_WRN in addition to previous level 3 INFO, write LOG_INF in addition to previous levels 4 DEBUG, write LOG_DBG in addition to previous levels |
|
This option enables support for the GATT Read Multiple Characteristic Values procedure. |
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This option enables support for the service changed characteristic. |
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Bluetooth H:4 UART driver. Requires hardware flow control lines to be available. |
|
Bluetooth three-wire (H:5) UART driver. Implementation of HCI Three-Wire UART Transport Layer. |
|
This option is set by the Bluetooth controller to indicate support for the Zephyr HCI Vendor-Specific Commands and Event. |
|
HCI-based stack with optional host & controller parts and an HCI driver in between. |
|
Enable support for throttling ACL buffers from the controller to the host. This is particularly useful when the host and controller are on separate cores since it ensures that we do not run out of incoming ACL buffers. |
|
Number of buffers available for HCI commands. |
|
NOTE: This is an advanced setting and should not be changed unless absolutely necessary |
|
Enable support for the Bluetooth Mesh HCI Commands. |
|
This option allows to access Bluetooth controller from the application with the RAW HCI protocol. |
|
This option is used by the HCI raw transport implementation to declare how much headroom it needs for any HCI transport headers. |
|
Headroom that the driver needs for sending and receiving buffers. Add a new ‘default’ entry for each new driver. |
|
Stack size needed for executing bt_send with specified driver. NOTE: This is an advanced setting and should not be changed unless absolutely necessary |
|
Override HCI Tx thread stack size |
|
Enable support for the Zephyr HCI Vendor-Specific Commands in the Host and/or Controller. This enables Set Version Information, Supported Commands, Supported Features vendor commands. |
|
Enable registering a callback for delegating to the user the handling of VS events that are not known to the stack |
|
Enable support for the Zephyr HCI Vendor-Specific Extensions in the Host and/or Controller. This enables Write BD_ADDR, Read Build Info, Read Static Addresses and Read Key Hierarchy Roots vendor commands. |
|
Use some heuristics to try to guess in advance whether the controller supports the HCI vendor extensions in advance, in order to prevent sending vendor commands to controller which may interpret them in completely different ways. |
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This option enables Bluetooth HF support |
|
Enables the software based AES-CCM engine in the host. Will use the controller’s AES encryption functions if available, or BT_HOST_CRYPTO otherwise. |
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Maximum number of supported local identity addresses. For most products this is safe to leave as the default value (1). |
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With this option enabled, if a pairing attempt occurs and the key storage is full, then the oldest keys in storage will be removed to free space for the new pairing keys. |
|
With this option enabled, aging counter will be stored in settings every time a successful pairing occurs. This increases flash wear out but offers a more correct finding of the oldest unused pairing info. |
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This option enables support for LE Connection oriented Channels, allowing the creation of dynamic L2CAP Channels. |
|
Maximum size of each incoming L2CAP PDU. |
|
Number of buffers available for outgoing L2CAP packets. |
|
Number of buffers available for fragments of TX buffers. Warning: setting this to 0 means that the application must ensure that queued TX buffers never need to be fragmented, i.e. that the controller’s buffer size is large enough. If this is not ensured, and there are no dedicated fragment buffers, a deadlock may occur. In most cases the default value of 2 is a safe bet. |
|
Maximum L2CAP MTU for L2CAP TX buffers. |
|
Use Nordic Lower Link Layer implementation. |
|
Use OpenISA Lower Link Layer implementation. |
|
Use Zephyr software BLE Link Layer implementation. |
|
Use Zephyr software BLE Link Layer ULL LLL split implementation. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
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Maximum number of simultaneous Bluetooth connections supported. |
|
Maximum number of paired Bluetooth devices. The minimum (and default) number is 1. |
|
Maximum number of simultaneous Bluetooth synchronous connections supported. The minimum (and default) number is 1. |
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Only process one mayfly callback per invocation (legacy behavior). If set to ‘n’, all pending mayflies for callee are executed before yielding |
|
This option enables Bluetooth Mesh support. The specific features that are available may depend on other features that have been enabled in the stack, such as GATT support. |
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Number of advertising buffers available. This should be chosen based on what kind of features the local node should have. E.g. a relay will perform better the more buffers it has. Another thing to consider is outgoing segmented messages. There must be at least three more advertising buffers than the maximum supported outgoing segment count (BT_MESH_TX_SEG_MAX). |
|
This option specifies how many application keys the device can store per network. |
|
Mesh Configuration Database [EXPERIMENTAL] |
|
This option specifies how many application keys that can at most be saved in the configuration database. |
|
This option specifies how many nodes each network can at most save in the configuration database. |
|
This option specifies how many subnets that can at most be saved in the configuration database. |
|
Enable support for the configuration client model. |
|
This options specifies the maximum capacity of the replay protection list. This option is similar to the network message cache size, but has a different purpose. |
|
Use this option to enable debug logs for the Bluetooth Mesh functionality. |
|
Use this option to enable Access layer and device composition related debug logs for Bluetooth Mesh. |
|
Use this option to enable advertising debug logs for the Bluetooth Mesh functionality. |
|
Use this option to enable Beacon-related debug logs for the Bluetooth Mesh functionality. |
|
Use this option to enable configuration database debug logs. |
|
Use this option to enable cryptographic debug logs for the Bluetooth Mesh functionality. |
|
Use this option to enable Friend debug logs for the Bluetooth Mesh functionality. |
|
Use this option to enable Low Power debug logs for the Bluetooth Mesh functionality. |
|
Use this option to enable debug logs for the Foundation Models. |
|
Use this option to enable Network layer debug logs for the Bluetooth Mesh functionality. |
|
Use this option to enable Provisioning debug logs for the Bluetooth Mesh functionality. |
|
Use this option to enable Proxy protocol debug logs. |
|
Use this option to enable persistent settings debug logs. |
|
Use this option to enable Transport layer debug logs for the Bluetooth Mesh functionality. |
|
This option forces the usage of the local identity address for all advertising. This can be a help for debugging (analyzing traces), however it should never be enabled for a production build as it compromises the privacy of the device. |
|
Enable this option to be able to act as a Friend Node. |
|
Number of Low Power Nodes the Friend can have a Friendship with simultaneously. |
|
Minimum number of buffers available to be stored for each local Friend Queue. |
|
Receive Window in milliseconds supported by the Friend node. |
|
Number of incomplete segment lists that we track for each LPN that we are Friends for. In other words, this determines how many elements we can simultaneously be receiving segmented messages from when the messages are going into the Friend queue. |
|
Size of the Subscription List that can be supported by a Friend node for a Low Power node. |
|
This option enables support for the Mesh GATT Proxy Service, i.e. the ability to act as a proxy between a Mesh GATT Client and a Mesh network. |
|
Enable support for the health client model. |
|
When the IV Update state enters Normal operation or IV Update in Progress, we need to keep track of how many hours has passed in the state, since the specification requires us to remain in the state at least for 96 hours (Update in Progress has an additional upper limit of 144 hours). In order to fulfill the above requirement, even if the node might be powered off once in a while, we need to store persistently how many hours the node has been in the state. This doesn’t necessarily need to happen every hour (thanks to the flexible duration range). The exact cadence will depend a lot on the ways that the node will be used and what kind of power source it has. Since there is no single optimal answer, this configuration option allows specifying a divider, i.e. how many intervals the 96 hour minimum gets split into. After each interval the duration that the node has been in the current state gets stored to flash. E.g. the default value of 4 means that the state is saved every 24 hours (96 / 4). |
|
This option removes the 96 hour limit of the IV Update Procedure and lets the state be changed at any time. |
|
This option specifies how many Label UUIDs can be stored. |
|
Enable this option to be able to act as a Low Power Node. |
|
Automatically enable LPN functionality once provisioned and start looking for Friend nodes. If this option is disabled LPN mode needs to be manually enabled by calling bt_mesh_lpn_set(true). |
|
Time in seconds from the last received message, that the node will wait before starting to look for Friend nodes. |
|
Perform the Friendship establishment using low power, with the help of a reduced scan duty cycle. The downside of this is that the node may miss out on messages intended for it until it has successfully set up Friendship with a Friend node. |
|
Maximum number of groups that the LPN can subscribe to. |
|
The initial value of the PollTimeout timer when Friendship gets established for the first time. After this the timeout will gradually grow toward the actual PollTimeout, doubling in value for each iteration. The value is in units of 100 milliseconds, so e.g. a value of 300 means 30 seconds. |
|
The MinQueueSizeLog field is defined as log_2(N), where N is the minimum number of maximum size Lower Transport PDUs that the Friend node can store in its Friend Queue. As an example, MinQueueSizeLog value 1 gives N = 2, and value 7 gives N = 128. |
|
PollTimeout timer is used to measure time between two consecutive requests sent by the Low Power node. If no requests are received by the Friend node before the PollTimeout timer expires, then the friendship is considered terminated. The value is in units of 100 milliseconds, so e.g. a value of 300 means 30 seconds. |
|
The ReceiveDelay is the time between the Low Power node sending a request and listening for a response. This delay allows the Friend node time to prepare the response. The value is in units of milliseconds. |
|
The contribution of the supported Receive Window used in Friend Offer Delay calculations. 0 = 1, 1 = 1.5, 2 = 2, 3 = 2.5. |
|
Time in seconds between Friend Requests, if a previous Friend Request did not receive any acceptable Friend Offers. |
|
The contribution of the RSSI measured by the Friend node used in Friend Offer Delay calculations. 0 = 1, 1 = 1.5, 2 = 2, 3 = 2.5. |
|
Latency in milliseconds that it takes to enable scanning. This is in practice how much time in advance before the Receive Window that scanning is requested to be enabled. |
|
Enable support for the model extension concept, allowing the Access layer to know about Mesh model relationships. |
|
This option specifies how many group addresses each model can at most be subscribed to. |
|
This option specifies how many application keys each model can at most be bound to. |
|
Number of messages that are cached for the network. This helps prevent unnecessary decryption operations and unnecessary relays. This option is similar to the replay protection list, but has a different purpose. |
|
This option determines for how long the local node advertises using Node Identity. The given value is in seconds. The specification limits this to 60 seconds, and implies that to be the appropriate value as well, so just leaving this as the default is the safest option. |
|
Enable this option to allow the device to be provisioned over the advertising bearer. |
|
Enable this option to allow the device to be provisioned over GATT. |
|
Enable this option to have support for provisioning remote devices. |
|
This option specifies how many Proxy Filter entries the local node supports. |
|
Support for acting as a Mesh Relay Node. |
|
This value defines in seconds how soon the RPL gets written to persistent storage after a change occurs. If the node receives messages frequently it may make sense to have this set to a large value, whereas if the RPL gets updated infrequently a value as low as 0 (write immediately) may make sense. Note that if the node operates a security sensitive use case, and there’s a risk of sudden power loss, it may be a security vulnerability to set this value to anything else than 0 (a power loss before writing to storage exposes the node to potential message replay attacks). |
|
Maximum incoming Upper Transport Access PDU length. This determines also how many segments incoming segmented messages can have. Each segment can contain 12 bytes, so this value should be set to a multiple of 12 to avoid wasted memory. The minimum requirement is 2 segments (24 bytes) whereas the maximum supported by the Mesh specification is 32 segments (384 bytes). |
|
Maximum number of simultaneous incoming multi-segment and/or reliable messages. |
|
This option adds extra self-tests which are run every time mesh networking is initialized. |
|
This value defines how often the local sequence number gets updated in persistent storage (i.e. flash). E.g. a value of 100 means that the sequence number will be stored to flash on every 100th increment. If the node sends messages very frequently a higher value makes more sense, whereas if the node sends infrequently a value as low as 0 (update storage for every increment) can make sense. When the stack gets initialized it will add this number to the last stored one, so that it starts off with a value that’s guaranteed to be larger than the last one used before power off. |
|
Activate shell module that provides Bluetooth Mesh commands to the console. |
|
This value defines in seconds how soon any pending changes are actually written into persistent storage (flash) after a change occurs. |
|
This option specifies how many subnets a Mesh network can participate in at the same time. |
|
Maximum number of segments supported for outgoing messages. This value should typically be fine-tuned based on what models the local node supports, i.e. what’s the largest message payload that the node needs to be able to send. This value affects memory and call stack consumption, which is why the default is lower than the maximum that the specification would allow (32 segments). The maximum outgoing SDU size is 12 times this number (out of which 4 or 8 bytes is used for the Transport Layer MIC). For example, 5 segments means the maximum SDU size is 60 bytes, which leaves 56 bytes for application layer data using a 4-byte MIC and 52 bytes using an 8-byte MIC. Be sure to specify a sufficient number of advertising buffers when setting this option to a higher value. There must be at least three more advertising buffers (BT_MESH_ADV_BUF_COUNT) as there are outgoing segments. |
|
Maximum number of simultaneous outgoing multi-segment and/or reliable messages. |
|
This option specifies the name of UART device to be used for the Bluetooth monitor logging. |
|
This is intended for unit tests where no internal driver should be selected. |
|
Select this for LE Observer role support. |
|
With this option enabled, the application will be able to perform LESC pairing with OOB data that consists of fixed random number and confirm value. This option should only be enabled for debugging and should never be used in production. |
|
This option sets the page timeout value. Value is selected as (N * 0.625) ms. |
|
Select this for LE Peripheral role support. |
|
Range 3200 to 65534 is invalid. 65535 represents no specific value. |
|
Range 3200 to 65534 is invalid. 65535 represents no specific value. |
|
Peripheral preferred slave latency in Connection Intervals |
|
It is up to user to provide valid timeout which pass required minimum value: in milliseconds it shall be larger than “(1+ Conn_Latency) * Conn_Interval_Max * 2” where Conn_Interval_Max is given in milliseconds. Range 3200 to 65534 is invalid. 65535 represents no specific value. |
|
Enable support for Bluetooth 5.0 PHY Update Procedure. |
|
Enable local Privacy Feature support. This makes it possible to use Resolvable Private Addresses (RPAs). |
|
Enable application access to the remote information available in the stack. The remote information is retrieved once a connection has been established and the application will be notified when this information is available through the remote_version_available connection callback. |
|
Enable this to get access to the remote version in the Controller and in the Host through bt_conn_get_info(). The fields in question can be then found in the bt_conn_info struct. |
|
This option enables Bluetooth RFCOMM support |
|
Maximum size of L2CAP PDU for RFCOMM frames. |
|
This option defines how often resolvable private address is rotated. Value is provided in seconds and defaults to 900 seconds (15 minutes). |
|
Bluetooth HCI driver for communication with another CPU using RPMsg framework. |
|
Enable RPMsg configuration for nRF53. Two channels of the IPM driver are used in the HCI driver: channel 0 for TX and channel 1 for RX. |
|
RPMsg RX thread priority |
|
RPMsg stack size for RX thread |
|
Number of buffers available for incoming ACL packets or HCI events from the controller. |
|
Maximum data size for each HCI RX buffer. This size includes everything starting with the ACL or HCI event headers. Note that buffer sizes are always rounded up to the nearest multiple of 4, so if this Kconfig value is something else then there will be some wasted space. The minimum of 73 has been taken for LE SC which has an L2CAP MTU of 65 bytes. On top of this there’s the L2CAP header (4 bytes) and the ACL header (also 4 bytes) which yields 73 bytes. |
|
Size of the receiving thread stack. This is the context from which all event callbacks to the application occur. The default value is sufficient for basic operation, but if the application needs to do advanced things in its callbacks that require extra stack space, this value can be increased to accommodate for that. |
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Maximum data size for each proprietary PDU. This size includes link layer header and payload. It does not account for HCI event headers as these PDUs are assumed to not go across HCI. |
|
Enable this if you want to perform active scanning using the local identity address as the scanner address. By default the stack will always use a non-resolvable private address (NRPA) in order to avoid disclosing local identity information. By not scanning with the identity address the scanner will receive directed advertise reports for for the local identity. If this use case is required, then enable this option. |
|
When selected, the Bluetooth stack will take care of storing (and restoring) the Bluetooth state (e.g. pairing keys) and configuration persistently in flash. When this option has been enabled, it’s important that the application makes a call to settings_load() after having done all necessary initialization (e.g. calling bt_enable). The reason settings_load() is handled externally to the stack, is that there may be other subsystems using the settings API, in which case it’s more efficient to load all settings in one go, instead of each subsystem doing it independently. |
|
Load Client Configuration Characteristic setting right after a bonded device connects. Disabling this option will increase memory usage as CCC values for all bonded devices will be loaded when calling settings_load. |
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Store Client Configuration Characteristic value right after it has been updated. By default, CCC is only stored on disconnection. Choosing this option is safer for battery-powered devices or devices that expect to be reset suddenly. However, it requires additional workqueue stack space. |
|
When selected, Bluetooth settings will use snprintk to encode key strings. When not selected, Bluetooth settings will use a faster builtin function to encode the key string. The drawback is that if printk is enabled then the program memory footprint will be larger. |
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Activate shell module that provides Bluetooth commands to the console. |
|
This option enables data signing which is used for transferring authenticated data in an unencrypted connection. |
|
This option enables support for the Security Manager Protocol (SMP), making it possible to pair devices over LE. |
|
This option allows all unauthenticated pairing attempts made by the peer where an unauthenticated bond already exists. This would enable cases where an attacker could copy the peer device address to connect and start an unauthenticated pairing procedure to replace the existing bond. When this option is disabled in order to create a new bond the old bond has to be explicitly deleted with bt_unpair. |
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When receiving pairing request or pairing response query the application whether to accept to proceed with pairing or not. This is for pairing over SMP and does not affect SSP, which will continue pairing without querying the application. The application can return an error code, which is translated into a SMP return value if the pairing is not allowed. |
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With this option enabled, the Security Manager will set MITM option in the Authentication Requirements Flags whenever local IO Capabilities allow the generated key to be authenticated. |
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This option enables SMP over BR/EDR even if controller is not supporting BR/EDR Secure Connections. This option is solely for testing and should never be enabled on production devices. |
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This option enables support for Secure Connection Only Mode. In this mode device shall only use Security Mode 1 Level 4 with exception for services that only require Security Mode 1 Level 1 (no security). Security Mode 1 Level 4 stands for authenticated LE Secure Connections pairing with encryption. Enabling this option disables legacy pairing. |
|
This option disables LE legacy pairing and forces LE secure connection pairing. All Security Mode 1 levels can be used with legacy pairing disabled, but pairing with devices that do not support secure connections pairing will not be supported. To force a higher security level use “Secure Connections Only Mode” |
|
This option enables SMP self-tests executed on startup to verify security and crypto functions. |
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This option enables support for USB HCI controllers that sometimes send out-of-order HCI events and ACL Data due to using different USB endpoints. Enabling this option will make the master role not require the encryption-change event to be received before accepting key-distribution data. It opens up for a potential vulnerability as the master cannot detect if the keys are distributed over an encrypted link. |
|
Supports Bluetooth ICs using SPI as the communication protocol. HCI packets are sent and received as single Byte transfers, prepended after a known header. Headers may vary per device, so additional platform specific knowledge may need to be added as devices are. |
|
Enable support for devices compatible with the BlueNRG Bluetooth Stack. Current driver supports: ST BLUENRG-MS. |
|
TODO |
|
This option enables support for storing bonds where either of devices has the Security Manager in Debug mode. This option should only be enabled for debugging and should never be used in production. |
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This option enables custom Bluetooth testing interface. Shall only be used for testing purposes. |
|
This option enables legacy ticker scheduling which defers overlapping ticker node timeouts and thereby prevents ticker interrupts during radio RX/TX. Enabling this option disables the ticker priority- and ‘must expire’ features. |
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This option enables ticker extensions such as re-scheduling of ticker nodes with slot_window set to non-zero. Ticker extensions are invoked by using available ‘_ext’ versions of ticker interface functions. |
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If this option is set TinyCrypt library is used for emulating the ECDH HCI commands and events needed by e.g. LE Secure Connections. In builds including the BLE Host, if not set the controller crypto is used for ECDH and if the controller doesn’t support the required HCI commands the LE Secure Connections support will be disabled. In builds including the HCI Raw interface and the BLE Controller, this option injects support for the 2 HCI commands required for LE Secure Connections so that Hosts can make use of those. The option defaults to enabled for a combined build with Zephyr’s own controller, since it does not have any special ECC support itself (at least not currently). |
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This option specifies the name of UART device to be used for Bluetooth. |
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This driver provides access to the local Linux host’s Bluetooth adapter using a User Channel HCI socket to the Linux kernel. It is only intended to be used with the native POSIX build of Zephyr. The Bluetooth adapter must be powered off in order for Zephyr to be able to use it. |
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This option places Security Manager in a Debug Mode. In this mode predefined Diffie-Hellman private/public key pair is used as described in Core Specification Vol. 3, Part H, 2.3.5.6.1. This option should only be enabled for debugging and should never be used in production. If this option is enabled anyone is able to decipher encrypted air traffic. |
|
Emit a Command Complete event from the Controller (and wait for it from the Host) for the NOP opcode to indicate that the Controller is ready to receive commands. |
|
This option enables the whitelist API. This takes advantage of the whitelisting feature of a BLE controller. The whitelist is a global list and the same whitelist is used by both scanner and advertiser. The whitelist cannot be modified while it is in use. An Advertiser can whitelist which peers can connect or request scan response data. A scanner can whitelist advertiser for which it will generate advertising reports. Connections can be established automatically for whitelisted peers. This options deprecates the bt_le_set_auto_conn API in favor of the bt_conn_create_aute_le API. |
|
Don’t fill gaps in generated hex/bin/s19 files. |
|
Build a binary in BIN format. This will build a zephyr.bin file need by some platforms. |
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Build a binary in ELF format that can run in the host system. This will build a zephyr.exe file. |
|
Build a binary in HEX format. This will build a zephyr.hex file need by some platforms. |
|
Build a binary in S19 format. This will build a zephyr.s19 file need by some platforms. |
|
Build a stripped binary. This will build a zephyr.stripped file need by some platforms. |
|
Enable Thread/Interrupt Stack Guards via built-in Stack Pointer limit checking. The functionality must be supported by HW. |
|
This links in the sys_cache_flush() function, which provides a way to flush multiple lines of the d-cache. If the d-cache is present, set this to y. If the d-cache is NOT present, set this to n. |
|
Size in bytes of a CPU d-cache line. Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT. |
|
This option enables querying the d-cache build register for finding the d-cache line size at the expense of taking more memory and code and a slightly increased boot time. If the CPU’s d-cache line size is known in advance, disable this option and manually enter the value for CACHE_LINE_SIZE. |
|
Enable CAN Driver Configuration |
|
Enable CANopen (EN 50325-4) (CiA 301) protocol support. Support is provided by the 3rd party CANopenNode protocol stack. |
|
This option enables the CANopenNode library. |
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Enable support for CANopen LED indicators according to the CiA 303-3 specification. |
|
Handle CANopen LEDs as one bicolor LED, favoring the red LED over the green LED in accordance with the CiA 303-3 specification. |
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Debug |
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Error |
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Info |
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Off |
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Warning |
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Size of the internal CANopen SDO buffer in bytes. Size must be at least equal to the size of the largest variable in the object dictionary. If data type is DOMAIN, data length is not limited to the SDO buffer size. If block transfer is implemented, value should be set to 889. |
|
Enable support for storing the CANopen object dictionary to non-volatile storage. |
|
Erase CANopen object dictionary EEPROM entries upon write to object dictionary index 0x1011 subindex 1. |
|
Enable internal thread for processing CANopen SYNC RPDOs and TPDOs. Application layer must take care of SYNC RPDO and TPDO processing on its own if this is disabled. |
|
Priority level of the internal thread which processes CANopen SYNC RPDOs and TPDOs. |
|
Size of the stack used for the internal thread which processes CANopen SYNC RPDOs and TPDOs. |
|
Size of the CANopen trace buffer in bytes. |
|
Priority level of the internal CANopen transmit workqueue. |
|
Size of the stack used for the internal CANopen transmit workqueue. |
|
Enable CAN controller 0 |
|
Enable CAN controller 1 |
|
Enable CAN controller 2 on the STM32F4 series of processors. (Tested on the STM32F4 series, may also work on F7, F1, F2 and L4) |
|
This option enables the automatic bus-off recovery according to ISO 11898-1 (recovery after 128 occurrences of 11 consecutive recessive bits). When this option is enabled, the recovery API is not available. |
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CAN device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
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Debug |
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Error |
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Info |
|
Off |
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Warning |
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This is a dummy driver that can only loopback messages. |
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“Device name for the loopback device” |
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Defines the array size of the callback/msgq pointers. Must be at least the size of concurrent reads. |
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Enable MCP2515 CAN Driver |
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MCP2515 driver initialization priority, must be higher than SPI. |
|
Priority level of the internal thread which is ran for interrupt handling and incoming packets. |
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Size of the stack used for internal thread which is ran for interrupt handling and incoming packets. |
|
Defines the array size of the callback/msgq pointers. Must be at least the size of concurrent reads. |
|
Enable support for mcux flexcan driver. |
|
Enable IPv6 Networking over can (6loCAN) |
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CAN NET device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
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Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
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Use default log level. |
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Only write to log when NET_ERR or LOG_ERR is used. |
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Write to log with NET_INFO or LOG_INF in addition to previous levels. |
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Do not write to log. |
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Write to log with NET_WARN or LOG_WRN in addition to previous level. |
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Name of the network device driver for IPv6 over CAN. |
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This option enables a timestamp value of the CAN free running timer. The value is incremented every bit time and starts when the controller is initialized. |
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Enable CAN Shell for testing. |
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Enable STM32 CAN Driver. Tested on stm32F0, stm32L4 and stm32F7 series. |
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Number of frames in the buffer of a zcan_work. |
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These are 4 in number supporting a max of 32 interrupts each. |
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CAVS 0 Driver name |
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Parent interrupt number to which CAVS_0 maps |
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CAVS 1 Driver name |
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Parent interrupt number to which CAVS_1 maps |
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CAVS 2 Driver name |
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Parent interrupt number to which CAVS_2 maps |
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CAVS 3 Driver name |
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Parent interrupt number to which CAVS_3 maps |
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Cavs Interrupt Logic initialization priority. |
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This indicates the offset in the SW_ISR_TABLE beginning from where the ISRs for CAVS Interrupt Controller are assigned. |
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This option specifies whether a check user exists for a cbor encoder. |
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This option enables floating point support. |
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This option enables half float type support. |
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This option specifies whether a default reader exists. |
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This option specifies whether a default writer exists. |
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This option specifies max recursions for the parser. |
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This option enables the strict parser checks. |
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This option enables cbor_value_to_pretty_stream function. |
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This option enables open memstream support. |
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Enable the ROM bootloader backdoor which starts the bootloader if the associated pin is at the correct logic level on reset. |
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Set the active level of the pin selected for the bootloader backdoor. |
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Set the pin that is level checked if the bootloader backdoor is enabled. |
|
Enable the serial bootloader which resides in ROM on CC13xx / CC26xx devices. |
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This module implements a kernel device driver for the TI SimpleLink CC13X2_CC26X2 series Real Time Counter and provides the standard “system clock driver” interfaces. |
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Prepend debug header, disabling flash verification |
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Prepend debug header, disabling flash verification |
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Enable driver for CCS811 Gas sensors. |
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Measurements disabled |
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Measurement every second |
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Measurement every ten seconds |
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Measurement every sixty seconds |
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Measurement every 250 milliseconds |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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CDC ACM class bulk endpoints size |
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IAD should not be required for non-composite CDC ACM device, but Windows 7 fails to properly enumerate without it. Enable if you want CDC ACM to work with Windows 7. |
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CDC ACM class interrupt IN endpoint size |
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CDC ECM class bulk endpoint size |
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CDC ECM class interrupt endpoint size |
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Debug |
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Error |
|
Info |
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Off |
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Warning |
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Character framebuffer for dot matrix displays. |
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Activate shell module that provides Framebuffer commands to the console. |
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Character Framebuffer Display Driver Name |
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Use default fonts. |
|
This option enables the civetweb HTTP API. |
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This option should be enabled if it is not known in advance whether the CPU supports the CLFLUSH instruction or not. The CPU is queried at boot time to determine which of the multiple implementations of sys_cache_flush() linked into the image is the correct one to use. If the CPU’s support (or lack thereof) of CLFLUSH is known in advance, then disable this option and set CLFLUSH_INSTRUCTION_SUPPORTED as appropriate. |
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An implementation of sys_cache_flush() that uses CLFLUSH is made available, instead of the one using WBINVD. This option should only be enabled if it is known in advance that the CPU supports the CLFLUSH instruction. It disables runtime detection of CLFLUSH support thereby reducing both memory footprint and boot time. |
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Enable support for hardware clock controller. Such hardware can provide clock for other subsystem, and thus can be also used for power efficiency by controlling their clock. Note that this has nothing to do with RTC. |
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Enable driver for Reset & Clock Control subsystem found in STM32F4 family of MCUs |
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This option controls the priority of clock control device initialization. Higher priority ensures that the device is initialized earlier in the startup cycle. If unsure, leave at default value 1 |
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Enable PLL on Beetle. Select n if not sure. |
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Debug |
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Error |
|
Info |
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Off |
|
Warning |
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Enable support for mcux ccm driver. |
|
Enable support for mcux mcg driver. |
|
Enable support for MCUX PCC driver. |
|
Enable support for mcux scg driver. |
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Enable support for mcux sim driver. |
|
Enable support for the Nordic Semiconductor nRFxx series SoC clock driver. |
|
Enables retrieving debug information like number of performed or skipped calibrations. |
|
Calibration is skipped when temperature change since last calibration was less than configured threshold. If number of consecutive skips reaches configured value then calibration is performed unconditionally. Set to 0 to perform calibration periodically regardless of temperature change. |
|
Periodically, calibration action is performed. Action includes temperature measurement followed by clock calibration. Calibration may be skipped if temperature change (compared to measurement of previous calibration) did not exceeded CLOCK_CONTROL_NRF_CALIBRATION_TEMP_DIFF and number of consecutive skips did not exceeded CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP. |
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Calibration is triggered if the temperature has changed by at least this amount since the last calibration. |
|
This option can be enabled to force an alternative implementation of the clock control driver. |
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76 ppm to 100 ppm |
|
101 ppm to 150 ppm |
|
0 ppm to 20 ppm |
|
151 ppm to 250 ppm |
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21 ppm to 30 ppm |
|
251 ppm to 500 ppm |
|
31 ppm to 50 ppm |
|
51 ppm to 75 ppm |
|
External full swing |
|
External low swing |
|
RC Oscillator |
|
Synthesized from HFCLK |
|
Crystal Oscillator |
|
Enable support for RV32M1 PCC driver. |
|
Enable driver for Reset & Clock Control subsystem found in STM32 family of MCUs |
|
This option controls the priority of clock control device initialization. Higher priority ensures that the device is initialized earlier in the startup cycle. If unsure, leave at default value 1 |
|
HCLK4 prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
|
AHB prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
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APB1 Low speed clock (PCLK1) prescaler, allowed values: 1, 2, 4, 8, 16 |
|
APB2 High speed clock (PCLK2) prescaler, allowed values: 1, 2, 4, 8, 16 |
|
CPU1 HCLK prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
|
CPU2 HCLK prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
|
D1 Domain, CPU1 clock (sys_d1cpre_ck prescaler), allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
|
APB3 clock (rcc_pclk3) prescaler, allowed values: 1, 2, 4, 8, 16 |
|
APB1 clock (rcc_pclk1) prescaler, allowed values: 1, 2, 4, 8, 16 |
|
APB2 clock (rcc_pclk2) prescaler, allowed values: 1, 2, 4, 8, 16 |
|
APB4 clock (rcc_pclk4) prescaler, allowed values: 1, 2, 4, 8, 16 |
|
hclk prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
|
Enable this option to bypass external high-speed clock (HSE). |
|
Value of external high-speed clock (HSE). |
|
Enable the low-speed external (LSE) clock supplied with a 32.768 kHz crystal resonator oscillator. |
|
allowed values: 1, 2, 3, 4, 5 |
|
Use HSE as source of MCO1 |
|
Use HSI as source of MCO1 |
|
Use LSE as source of MCO1 |
|
MCO1 output disabled, no clock on MCO1 |
|
Use PLLCLK as source of MCO1 |
|
allowed values: 1, 2, 3, 4, 5 |
|
Use HSE as source of MCO2 |
|
MCO2 output disabled, no clock on MCO2 |
|
Use PLLCLK as source of MCO2 |
|
Use PLLI2S as source of MCO2 |
|
Use SYSCLK as source of MCO2 |
|
Enable hardware auto-calibration with LSE. |
|
Frequency range of MSI when MSI range is provided in RCC_CR register Range 0: 100kHz Range 1: 200kHz Range 2 around 400 kHz Range 3 around 800 kHz Range 4: 1 MHz Range 5: 2 MHz Range 6: 4 MHz (reset value) Range 7: 8 MHz Range 8: 16 MHz Range 9: 24 MHz Range 10: 32 MHz Range 11: 48 MHz |
|
PLL divisor, allowed values: 2-4. |
|
PLL multiplier, allowed values: 2-16. PLL output must not exceed 48MHz. |
|
PLLM division factor needs to be set correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63 |
|
PLLN multiplier factor needs to be set correctly to ensure that the VCO output frequency is between 100 and 432 MHz, except on STM32F401 where the frequency must be between 192 and 432 MHz. Allowed values: 50-432 (STM32F401: 192-432) |
|
PREDIV is PLLSCR clock signal prescaler, allowed values: 1 - 16. |
|
PREDIV is PLLSCR clock signal prescaler, present on STM32F0 SoC having an HSE Oscillator available like the stm32f04xx, stm32f07xx, stm32f09xx and stm32f030xc parts. If configured on a non supported part, the HSI oscillator will be used a default PLL source and this config will be ignored. Allowed values: 1 - 16. |
|
PLLP division factor needs to be set correctly to not exceed 84MHz. Allowed values: 2, 4, 6, 8 |
|
The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly. Allowed values: 2-15 |
|
PLL R Output divisor, allowed values: 1-128. |
|
Use HSE as source of PLL |
|
Use HSI as source of PLL |
|
Use MSI as source of PLL |
|
Use PLL2 as source of main PLL. This is equivalent of defining PLL2 as source PREDIV1SCR. If not selected, default source is HSE. |
|
Enable this option to enable /2 prescaler on HSE to PLL clock signal |
|
Use HSE as source of SYSCLK |
|
Use HSI as source of SYSCLK |
|
Use MSI as source of SYSCLK |
|
Use PLL as source of SYSCLK |
|
Mention maximum number of mutexes in CMSIS compliant application. |
|
This enables CMSIS RTOS v1 API support. This is an OS-integration layer which allows applications using CMSIS RTOS APIs to build on Zephyr. |
|
This enables CMSIS RTOS v2 API support. This is an OS-integration layer which allows applications using CMSIS RTOS V2 APIs to build on Zephyr. |
|
Mention maximum number of semaphores in CMSIS compliant application. |
|
Mention max stack size threads can be allocated in CMSIS RTOS application. |
|
Mention maximum number of timers in CMSIS compliant application. |
|
Mention maximum number of event flags in CMSIS RTOS V2 compliant application. |
|
Mention maximum number of memory slabs in CMSIS RTOS V2 compliant application. |
|
Mention maximum dynamic size of memory slabs/pools in CMSIS RTOS V2 compliant application. |
|
Mention maximum number of message queues in CMSIS RTOS V2 compliant application. |
|
Mention maximum dynamic size of message queues in CMSIS RTOS V2 compliant application. |
|
Mention max number of mutexes in CMSIS RTOS V2 compliant application. |
|
Mention max number of semaphores in CMSIS RTOS V2 compliant application. |
|
Mention max number of dynamic threads in CMSIS RTOS V2 compliant application. There’s a limitation on the number of threads due to memory related constraints. Dynamic threads are a subset of all other CMSIS threads i.e. they also count towards that maximum too. |
|
Mention dynamic stack size threads are allocated in CMSIS RTOS V2 application. |
|
Mention max number of threads in CMSIS RTOS V2 compliant application. There’s a limitation on the number of threads due to memory related constraints. |
|
Mention max stack size threads can be allocated in CMSIS RTOS V2 application. |
|
Mention maximum number of timers in CMSIS RTOS V2 compliant application. |
|
Set this option to use the internal high frequency RC oscillator as high frequency clock. |
|
Set this option to use the external high frequency crystal oscillator as high frequency clock. |
|
Set this option to use the external low frequency crystal oscillator as high frequency clock. |
|
Set the external high frequency oscillator frequency in Hz. This should be set by the board’s defconfig. |
|
Set the external low frequency oscillator frequency in Hz. This should be set by the board’s defconfig. |
|
This option enables the CoAP implementation. |
|
This option enables the parsing of extended CoAP options length. CoAP extended options length can be 2 byte value, which requires more memory. User can save memory by disabling this. That means only length of maximum 12 bytes are supported by default. Enable this if length field going to bigger that 12. |
|
This option specifies the maximum value of length field when COAP_EXTENDED_OPTIONS_LEN is enabled. Define the value according to user requirement. |
|
This value is used as a base value to retry pending CoAP packets. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Do not enable this for normal use. |
|
This option enables the block wise support of CoAP response to ./well-known/core request. Without this option all resource’s information will be sent in a single IP packet (can be multiple fragments depends on MTU size). This will be useful in mesh kind of networks. |
|
Maximum size of CoAP block. Valid values are 16, 32, 64, 128, 256, 512 and 1024. |
|
When selected this will relocate .text, data and .bss sections from the specified files and places it in the required memory region. The files should be specified in the CMakeList.txt file with a cmake API zephyr_code_relocate(). |
|
Enable code density option to get better code density |
|
Link code into external FlexSPI-controlled memory |
|
Link code into internal FlexSPI-controlled memory |
|
Link code into internal instruction tightly coupled memory (ITCM) |
|
Suppress any warnings from the pre-processor when including deprecated header files. |
|
This option is a free-form string that is passed to the compiler when building all parts of a project (i.e. kernel). The compiler options specified by this string supplement the predefined set of compiler supplied by the build system, and can be used to change compiler optimization, warning and error messages, and so on. |
|
Console drivers |
|
Character by character input and output |
|
Buffer size for console_getchar(). The default is optimized to save RAM. You may need to increase it e.g. to support large host-side clipboard pastes. Set to 0 to disable interrupt-driven operation and use busy-polling. |
|
Line by line input |
|
This option enables console input handler allowing to write simple interaction between serial console and the OS. |
|
This is an option to be enabled by console drivers to signal that some kind of console exists. |
|
This option can be used to modify the maximum length a console input can be. |
|
Buffer size for console_putchar(). The default is optimized to save RAM. You may need to increase it e.g. to support large host-side clipboard pastes. Set to 0 to disable interrupt-driven operation and use busy-polling. |
|
Console subsystem and helper functions |
|
This module implements a kernel device driver for the Cortex-M processor SYSTICK timer and provides the standard “system clock driver” interfaces. |
|
Enable support for counter and timer. |
|
Counter driver for x86 CMOS/RTC clock |
|
Enable counter driver based on RTCC module for Silicon Labs Gecko chips. |
|
Enable the IMX EPIT driver. |
|
Enable Counter 1. |
|
Enable Counter 2. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable support for mcux General Purpose Timer (GPT) driver. |
|
Enable Counter on GPT1 |
|
Enable Counter on GPT2 |
|
Enable support for mcux rtc driver. |
|
Enable Counter on RTC0 |
|
Enable Counter on RTC1 |
|
Enable Counter on RTC2 |
|
Build RTC driver for STM32 SoCs. Tested on STM32 F3, F4, L4, F7, G4 series |
|
Use LSE as RTC clock |
|
Use LSI as RTC clock |
|
Xtal mode higher driving capability |
|
Xtal mode lower driving capability |
|
Xtal mode medium high driving capability |
|
Xtal mode medium low driving capability |
|
Enable the SAM0 series timer counter (TC) driver in 32-bit wide mode. |
|
clock / 1 |
|
clock / 1024 |
|
clock / 16 |
|
clock / 2 |
|
clock / 256 |
|
clock / 4 |
|
clock / 64 |
|
clock / 8 |
|
clock / 1 |
|
clock / 1024 |
|
clock / 16 |
|
clock / 2 |
|
clock / 256 |
|
clock / 4 |
|
clock / 64 |
|
clock / 8 |
|
clock / 1 |
|
clock / 1024 |
|
clock / 16 |
|
clock / 2 |
|
clock / 256 |
|
clock / 4 |
|
clock / 64 |
|
clock / 8 |
|
clock / 1 |
|
clock / 1024 |
|
clock / 16 |
|
clock / 2 |
|
clock / 256 |
|
clock / 4 |
|
clock / 64 |
|
clock / 8 |
|
Enable Counter on TIMER0 |
|
Enable Counter on TIMER1 |
|
Enable Counter on TIMER2 |
|
Enable Counter on TIMER3 |
|
Enable Counter on TIMER4 |
|
Enable counter driver for Microchip XEC MCU series. Such driver will expose the basic timer devices present on the MCU. |
|
This option will build your application with the -coverage option which will generate data that can be used to create coverage reports. For more information see https://docs.zephyrproject.org/latest/guides/coverage.html |
|
Dump collected coverage information to console on exit. |
|
This option will select the custom gcov library. The reports will be available over serial. This serial dump can be passed to gen_gcov_files.py which creates the required .gcda files. These can be read by gcov utility. For more details see gcovr.com . |
|
This option enables the use of applications built with C++. |
|
This option signifies the use of a CPU from the Apollo Lake family. |
|
This option signifies the use of an ARC EM CPU |
|
This option signifies the use of an ARC HS CPU |
|
This option signifies the use of a CPU of the ARCv2 family. |
|
This option signifies the use of a CPU from the Atom family. |
|
This option signifies the use of a CPU of the Cortex family. |
|
This option signifies the use of a CPU of the Cortex-A family. |
|
This option signifies the use of a Cortex-A53 CPU |
|
This option signifies the use of a CPU of the Cortex-M family. |
|
This option signifies the use of a Cortex-M0 CPU |
|
This option signifies the use of a Cortex-M0+ CPU |
|
This option signifies the Cortex-M0 has some mechanisms that can map the vector table to SRAM |
|
This option signifies the use of a Cortex-M23 CPU |
|
This option signifies the use of a Cortex-M3 CPU |
|
This option signifies the use of a Cortex-M33 CPU |
|
This option signifies the use of a Cortex-M4 CPU |
|
This option signifies the use of a Cortex-M7 CPU |
|
This option signifies the CPU has the BASEPRI register. The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Always present in CPUs that implement the ARMv7-M or ARM8-M Mainline architectures. |
|
This option signifies the Cortex-M CPU has the CMSE intrinsics. |
|
This option signifies that the CPU implements the Data Watchpoint and Trace (DWT) unit specified by the ARMv7-M and above. While ARMv6-M does define a “DWT” unit, this is significantly different from the DWT specified by the ARMv7-M and above in terms of both feature set and register mappings. |
|
This option signifies the CPU may trigger system faults (other than HardFault) with configurable priority, and, therefore, it needs to reserve a priority level for them. |
|
This option signifies the CPU has the MSPLIM, PSPLIM registers. The stack pointer limit registers, MSPLIM, PSPLIM, limit the extend to which the Main and Process Stack Pointers, respectively, can descend. MSPLIM, PSPLIM are always present in ARMv8-M MCUs that implement the ARMv8-M Main Extension (Mainline). In an ARMv8-M Mainline implementation with the Security Extension the MSPLIM, PSPLIM registers have additional Secure instances. In an ARMv8-M Baseline implementation with the Security Extension the MSPLIM, PSPLIM registers have only Secure instances. |
|
This option is enabled when the CPU implements the SysTick timer. |
|
This option signifies the CPU has the VTOR register. The VTOR indicates the offset of the vector table base address from memory address 0x00000000. Always present in CPUs implementing the ARMv7-M or ARMv8-M architectures. Optional in CPUs implementing ARMv6-M, ARMv8-M Baseline architectures (except for Cortex-M0, where it is never implemented). |
|
This option signifies the use of a CPU of the Cortex-R family. |
|
This option signifies the use of a Cortex-R4 CPU |
|
This option signifies the use of a Cortex-R5 CPU |
|
If y, the SoC uses an ARC EM4 CPU |
|
If y, the SoC uses an ARC EM4 DMIPS CPU |
|
If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision floating-point and double assist instructions |
|
If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision floating-point extension |
|
If y, the SoC uses an ARC EM6 CPU |
|
This option is enabled when the CPU has a Memory Protection Unit (MPU) in ARM flavor. |
|
MCU implements the ARM Security Attribution Unit (SAU). |
|
If enabled, this option signifies that the SoC will define and configure its own fixed MPU regions in the SoC definition. These fixed MPU regions are currently used to set Flash and SRAM default access policies and they are programmed at boot time. |
|
This option is enabled when the processor hardware is configured in Dual-redundant Core Lock-step (DCLS) topology. |
|
This option is enabled when the CPU has hardware floating point unit. |
|
When enabled, indicates that the SoC has a double floating point precision unit. |
|
This option is enabled when the CPU has a Memory Protection Unit (MPU). |
|
MCU implements the nRF (vendor-specific) Security Attribution Unit. (IDAU: “Implementation-Defined Attribution Unit”, in accordance with ARM terminology). |
|
This option is enabled when the CPU has a Memory Protection Unit (MPU) in NXP flavor. |
|
This option is enabled when the CPU has support for Trusted Execution Environment (e.g. when it has a security attribution unit). |
|
This option signifies the use of a CPU from the Minute IA family. |
|
This option signifies the use of a Nios II Gen 2 CPU |
|
Crypto Drivers [EXPERIMENTAL] |
|
Enable Atmel ATAES132A 32k AES Serial EEPROM support. |
|
Name for the ATAES132A driver which will be used for binding. |
|
ATAES132A chip’s I2C address. |
|
Master I2C port name through which ATAES132A chip is accessed. |
|
Fast bus speed of up to 400KHz. |
|
Standard bis speed of up to 100KHz. |
|
Crypto devices initialization priority. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable mbedTLS shim layer compliant with crypto APIs. You will need to fill in a relevant value to CONFIG_MBEDTLS_HEAP_SIZE. |
|
Device name for mbedTLS Pseudo device. |
|
This can be used to tweak the amount of sessions the driver can handle in parallel. |
|
Enable STM32 HAL-based Cryptographic Accelerator driver. |
|
This can be used to tweak the amount of sessions the driver can handle in parallel. |
|
Enable TinyCrypt shim layer compliant with crypto APIs. |
|
Device name for TinyCrypt Pseudo device. |
|
This can be used to tweak the amount of sessions the driver can handle in parallel. |
|
Personalization data can be provided in addition to the entropy source to make the initialization of the CTR-DRBG as unique as possible. |
|
Enables the CTR-DRBG pseudo-random number generator. This CSPRNG shall use the entropy API for an initialization seed. The CTR-DRBG is a a FIPS140-2 recommended cryptographically secure random number generator. |
|
Path to the linker script to be used instead of the one define by the board. The linker script must be based on a version provided by Zephyr since the kernel can expect a certain layout/certain regions. This is useful when an application needs to add sections into the linker script and avoid having to change the script provided by Zephyr. |
|
Note: This is deprecated, use Cmake function zephyr_linker_sources() instead. Include a customized linker script fragment for inserting additional data and linker directives into the rodata section. |
|
Note: This is deprecated, use Cmake function zephyr_linker_sources() instead. Include a customized linker script fragment for inserting additional data and linker directives into the data section. |
|
Note: This is deprecated, use Cmake function zephyr_linker_sources() instead. Include a customized linker script fragment for inserting additional arbitrary sections. |
|
MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT(ARMv7-M) sometimes cause memory wasting in linker scripts defined memory sections. Use this symbol to guarantee user custom section align size to avoid more memory used for respect alignment. But that needs carefully configure MPU region and sub-regions(ARMv7-M) to cover this feature. |
|
Custom align size of memory section in linker scripts. Usually it should consume less alignment memory. Although this alignment size is configured by users, it must also respect the power of two regulation if hardware requires. |
|
Link data into internal data tightly coupled memory (DTCM) |
|
Link data into On-Chip RAM memory |
|
Link data into external SEMC-controlled memory |
|
Build a kernel suitable for debugging. Right now, this option only disables optimization, more debugging variants can be selected from here to allow more debugging. |
|
This option enables the addition of various information that can be used by debuggers in debugging the system, or enable additional debugging information to be reported at runtime. |
|
Compiler optimizations will be set to -Og independently of other options. |
|
Device configuration data (DCD) provides a sequence of commands to the boot ROM to initialize components such as an SDRAM. |
|
Enable device Idle Power Management to save power. With device Idle PM enabled, devices can be suspended or resumed based on the device usage even while the CPU or system is running. |
|
This option enables the device power management interface. The interface consists of hook functions implemented by device drivers that get called by the power manager application when the system is going to suspend state or resuming from suspend state. This allows device drivers to do any necessary power management operations like turning off device clocks and peripherals. The device drivers may also save and restore states in these hook functions. |
|
This shell provides access to basic device data. |
|
Enable driver for the DHT temperature and humidity sensor family. |
|
This option will disable Speculative Store Bypass in order to mitigate against certain kinds of side channel attacks. Quoting the “Speculative Execution Side Channels” document, version 2.0:
If enabled, this applies to all threads in the system. Even if enabled, will have no effect on CPUs that do not require this feature. |
|
Enable disk access over a supported media backend like FLASH or RAM |
|
Flash device is used for the file system. |
|
RAM buffer used to emulate storage disk. This option can be used to test the file system. |
|
File system on a SDHC card. |
|
File system on a SDHC card accessed over SPI. |
|
File system on a SDHC card accessed over NXP USDHC. |
|
File system on a SDHC card accessed over USDHC instance 1. |
|
File system on a SDHC card accessed over USDHC instance 2. |
|
This is typically the minimum block size that is erased at one time in flash storage. Typically it is equal to the flash memory page size. |
|
Flash device name to be used as storage backend |
|
This is the start address alignment required by the flash component. |
|
This is the maximum number of bytes that the flash_write API can accept per invocation. API. |
|
This is start address of the flash to be used as storage backend. |
|
Disk name as per file system naming guidelines. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Disk name as per file system naming guidelines. |
|
Size of the RAM Disk. |
|
Disk name as per file system naming guidelines. |
|
This is the file system volume size in bytes. |
|
Enable display drivers |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable support for mcux eLCDIF driver. |
|
DMA driver Configuration |
|
IRQ Priority for the DMA Controller. |
|
Device name for DMA Controller 0. |
|
Device name for DMA Controller 1. |
|
Device name for DMA Controller 2. |
|
DesignWare DMA driver. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable Nios-II Modular Scatter-Gather DMA(MSGDMA) driver. |
|
DMA driver for Atmel SAM0 series MCUs. |
|
Enable Atmel SAM MCU Family Direct Memory Access (XDMAC) driver. |
|
DMA driver for STM32 series SoCs. |
|
Enable DMA support on F2/F4/F7 series SoCs. |
|
Enable DMA support on F0/F1/F3/L0/L4 series SoCs. |
|
This defines how many concurrent DNS queries can be generated using same DNS context. Normally 1 is a good default value. |
|
This option enables the DNS client side support for Zephyr |
|
Number of additional buffers available for the DNS resolver. The DNS resolver requires at least one buffer. This option enables additional buffers required for multiple concurrent DNS connections. |
|
Number of additional DNS queries that the DNS resolver may generate when the RR ANSWER only contains CNAME(s). The maximum value of this variable is constrained to avoid ‘alias loops’. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Max number of DNS servers that we can connect to. Normally one DNS server is enough. Each connection to DNS server will use one network context. |
|
DNS server IP address 1. The address can be either IPv4 or IPv6 address. An optional port number can be given. Following syntax is supported: 192.0.2.1 192.0.2.1:5353 2001:db8::1 [2001:db8::1]:5353 It is not mandatory to use this Kconfig option at all. The one calling dns_resolve_init() can use this option or not to populate the server list. If the DNS server addresses are set here, then we automatically create default DNS context for the user. |
|
See help in “DNS server 1” option. |
|
See help in “DNS server 1” option. |
|
See help in “DNS server 1” option. |
|
See help in “DNS server 1” option. |
|
Allow DNS IP addresses to be set in config file for networking applications. |
|
Enable dummy display driver compliant with display driver API. |
|
Dummy display device name |
|
X resolution for dummy display |
|
Y resolution for dummy display |
|
Designware Interrupt Controller can be used as a 2nd level interrupt controller which combines several sources of interrupt into one line that is then routed to the 1st level interrupt controller. |
|
DesignWare Interrupt Controller initialization priority. |
|
Give a name for the instance of Designware Interrupt Controller |
|
Parent interrupt number to which DW_ICTL maps |
|
This indicates the offset in the SW_ISR_TABLE beginning from where the ISRs for Designware Interrupt Controller are assigned. |
|
Direct interrupts are designed for performance-critical interrupt handling and do not go through all of the common interrupt handling code. This option enables the installation of interrupt service routines for direct interrupts at runtime. Note: this requires enabling support for dynamic interrupts in the kernel. |
|
Enable installation of interrupts at runtime, which will move some interrupt-related data structures to RAM instead of ROM, and on some architectures increase code size. |
|
Enabling this option allows for kernel objects to be requested from the calling thread’s resource pool, at a slight cost in performance due to the supplemental run-time tables required to validate such objects. Objects allocated in this way can be freed with a supervisor-only API call, or when the number of references to that object drops to zero. |
|
This hidden option unconditionally saves/restores the FPU/SIMD register state on every context switch. Mitigates CVE-2018-3665, but incurs a performance hit. For vulnerable systems that process sensitive information in the FPU register set, should be used any time CONFIG_FLOAT is enabled, regardless if the FPU is used by one thread or multiple. |
|
This option will enable stdout as early as possible, for debugging purpose. For instance, in case of STDOUT_CONSOLE being set it will initialize its driver earlier than normal, in order to get the stdout sent through the console at the earliest stage possible. |
|
Enable support for EEPROM hardware. |
|
Enable support for Atmel AT24 (and compatible) I2C EEPROMs. |
|
Enable support for Atmel AT25 (and compatible) SPI EEPROMs. |
|
Enable support for Atmel AT2x (and compatible) I2C/SPI EEPROMs. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable the EEPROM shell with EEPROM related commands. |
|
Size of the buffer used for EEPROM read/write commands in the EEPROM shell. |
|
Enable Simulated EEPROM driver. |
|
Minimum read time (µS) |
|
Minimum write time (µS) |
|
Enable Simulated hardware timing. |
|
Enable EEPROM support on the STM32 L0, L1 family of processors. |
|
This option will enable the Extended Indirect Branch Restricted Speculation ‘always on’ feature. This mitigates Indirect Branch Control vulnerabilities (aka Spectre V2). |
|
Enable USB HID Device Interrupt OUT Endpoint. |
|
Enable driver for ENS210 Digital Temperature and Humidity sensor. |
|
Check the crc value after data reading. |
|
Number of retries when value reading failed, value not valid or crc not ok. |
|
Number of retries when status reading failed or device not ready. |
|
The number of samples detected with repeating patterns before an alarm event is triggered. The associated FRO is automatically shut down. |
|
The size in bytes of the buffer used to store entropy generated by the hardware. Should be a power of two for high performance. |
|
This option enables the driver for the True Random Number Generator (TRNG) for TI SimpleLink CC13xx / CC26xx SoCs. |
|
The number of samples used to generate entropy. The time required to generate 64 bits of entropy is determined by the number of FROs enabled, the sampling (system) clock frequency, and this value. |
|
The number of FROs allowed to be shutdown before the driver attempts to take corrective action. |
|
Enables a random number generator that uses the enabled hardware entropy gathering driver to generate random numbers. Should only be selected if hardware entropy driver is designed to be a random number generator source. |
|
This option enables the entropy number generator for ESP32 SoCs. With Wi-Fi and Bluetooth disabled, this will produce pseudo-entropy numbers: noise from these radios are used to feed entropy in this generator. |
|
Include entropy drivers in system config. |
|
This is an option to be enabled by individual entropy driver to signal that there is a true entropy driver. |
|
This option enables the RNG module, which is an entropy number generator, based on Pseudo-Random Binary Sequences (PRBS) for LiteX SoC builder |
|
This option enables the random number generator accelerator (RNGA) driver based on the MCUX RNGA driver. |
|
This option enables the true random number generator (TRNG) driver based on the MCUX TRNG driver. |
|
Specify the device name to be used for the ENTROPY driver. |
|
This option enables the RNG bias correction, which guarantees a uniform distribution of 0 and 1. When this option is enabled, the time to generate a byte cannot be guaranteed. |
|
Buffer length in bytes used to store entropy bytes generated by the hardware to make them ready for ISR consumers. Please note, that size of the pool must be a power of 2. |
|
Low water-mark threshold in bytes to trigger entropy generation for ISR consumers. As soon as the number of available bytes in the buffer goes below this number hardware entropy generation will be started. |
|
nRF5X RNG IRQ priority. |
|
This option enables the RNG peripheral, which is a random number generator, based on internal thermal noise, that provides a random 8-bit value to the host when read. |
|
Buffer length in bytes used to store entropy bytes generated by the hardware to make them ready for thread mode consumers. Please note, that size of the pool must be a power of 2. |
|
Low water-mark threshold in bytes to trigger entropy generation for thread mode consumers. As soon as the number of available bytes in the buffer goes below this number hardware entropy generation will be started. |
|
This option can be enabled to force an alternative implementation of the entropy driver. |
|
This option enables the true random number generator (TRNG) driver based on the RV32M1 TRNG driver. |
|
Enable True Random Number Generator (TRNG) driver for Atmel SAM MCUs. |
|
This option enables the RNG processor, which is a entropy number generator, based on a continuous analog noise, that provides a entropy 32-bit value to the host when read. It is available for F4 (except STM32F401 & STM32F411), L4, F7 and G4 series. |
|
Enable per-thread errno in the kernel. Application and library code must include errno.h provided by the C library (libc) to use the errno symbol. The C library must access the per-thread errno via the _get_errno() symbol. |
|
Enable ESPI Driver. |
|
Enable automatic acknowledge from eSPI slave towards eSPI host whenever it receives suspend or reset warning. If this is disabled, it means the app wants to be give the opportunity to prepare for either HOST suspend or reset. |
|
eSPI Controller supports flash channel. |
|
Driver initialization priority for eSPI driver. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
eSPI Controller supports OOB channel. |
|
Enables 8042 keyboard controller over eSPI peripheral channel. |
|
eSPI Controller supports peripheral channel. |
|
Enables debug Port 80 over eSPI peripheral channel. |
|
Enables ACPI Host I/O over eSPI peripheral channel. |
|
Enables legacy Port 92 over eSPI peripheral channel. |
|
Enables UART over eSPI peripheral channel. |
|
This tells the driver to which SoC UART to direct the UART traffic send over eSPI from host. |
|
Enables eSPI driver in slave mode. |
|
eSPI Controller supports virtual wires channel. |
|
Enable the Microchip XEC ESPI driver. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Enable Intel(R) PRO/1000 Gigabit Ethernet driver. |
|
Enabling this will turn on the hexdump of the received and sent frames. Do not leave on for production. |
|
ENC28J60C Stand-Alone Ethernet Controller with SPI Interface |
|
Include port 0 driver |
|
Enable Full Duplex. Device is configured half duplex when disabled. |
|
This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic. |
|
Priority level for internal thread which is ran for incoming packet processing. |
|
Size of the stack used for internal thread which is ran for incoming packet processing. |
|
Given timeout in milliseconds. Maximum amount of time that the driver will wait from the IP stack to get a memory buffer before the Ethernet frame is dropped. |
|
ENC424J600C Stand-Alone Ethernet Controller with SPI Interface |
|
This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic. |
|
Priority level for internal thread which is ran for incoming packet processing. |
|
Size of the stack used for internal thread which is ran for incoming packet processing. |
|
Given timeout in milliseconds. Maximum amount of time that the driver will wait from the IP stack to get a memory buffer before the Ethernet frame is dropped. |
|
Enable Ethernet driver for Silicon Labs Gecko chips. |
|
Set the RX idle timeout period in milliseconds after which the PHY’s carrier status is re-evaluated. |
|
IRQ priority of Ethernet device |
|
MAC Address Byte 0 |
|
MAC Address Byte 1 |
|
MAC Address Byte 2 |
|
MAC Address Byte 3 |
|
MAC Address Byte 4 |
|
MAC Address Byte 5 |
|
Assign an arbitrary MAC address. |
|
Device name allows user to obtain a handle to the device object required by all driver API functions. Device name has to be unique. |
|
Generate a random MAC address dynamically. |
|
RX thread priority |
|
RX thread stack size |
|
Ethernet device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
|
LiteEth Ethernet core driver |
|
LiteEth Ethernet port 0 |
|
IRQ priority |
|
Generate a random MAC address dynamically. |
|
Enable MCUX Ethernet driver. Note, this driver performs one shot PHY setup. There is no support for PHY disconnect, reconnect or configuration change. |
|
Include port 0 driver |
|
Manual MAC address |
|
Generate a random MAC address dynamically on each reboot. Note that using this choice and rebooting a board may leave stale MAC address in peers’ ARP caches and lead to issues and delays in communication. (Use “ip neigh flush all” on Linux peers to clear ARP cache.) |
|
Generate MAC address from MCU’s unique identification register. |
|
Enable hardware acceleration for the following: - IPv4, UDP and TCP checksum (both Rx and Tx) |
|
Enable additional PHY related debug information related to PHY status polling. |
|
Set the PHY status polling period. |
|
Place the Ethernet receiver in promiscuous mode. This may be useful for debugging and not needed for normal work. |
|
Set the frequency in Hz sourced to the PTP timer. If the value is set properly, the timer will be accurate. |
|
Set the number of RX buffers provided to the MCUX driver to store timestamps. |
|
Set the number of TX buffers provided to the MCUX driver to store timestamps. |
|
Set the number of RX buffers provided to the MCUX driver. |
|
Set the number of TX buffers provided to the MCUX driver. |
|
Enable native posix ethernet driver. Note, this driver is run inside a process in your host system. |
|
This option sets the TUN/TAP device name in your host system. |
|
This option sets the driver name and name of the network interface in your host system. |
|
Specify a MAC address for the ethernet interface in the form of six hex 8-bit chars separated by colons (e.g.: aa:33:cc:22:e2:c0). The default is an empty string, which means the code will make 00:00:5E:00:53:XX, where XX will be random. |
|
Enable PTP clock support. |
|
Generate a random MAC address dynamically. |
|
This option sets the name of the script that is run when the host TAP network interface is created. The script should setup IP addresses etc. for the host TAP network interface. The default script accepts following options: -i|–interface <network interface name>, default is zeth -f|–file <config file name>, default is net_setup_host.conf If needed, you can add these options to this script name option. Note that the driver will add -i option with the value of CONFIG_ETH_NATIVE_POSIX_DRV_NAME option to the end of the options list when calling the host setup script. |
|
If set, the native_posix ethernet driver will set up the network
interface, requiring |
|
This option sets the name of the script that is run when the host TAP network interface is created and setup script has been run. The startup script could launch e.g., wireshark to capture the network traffic for the freshly started network interface. Note that the network interface name CONFIG_ETH_NATIVE_POSIX_DRV_NAME is appended at the end of this startup script name. Example script for starting wireshark is provided in ${ZEPHYR_BASE}/samples/net/eth_native_posix/net_start_wireshark.sh file. |
|
By default the startup script is run as a root user. Set here the username to run the script if running it as a root user is not desired. Note that this setting is only for startup script and not for the setup script. The setup script needs to be run always as a root user. |
|
Native posix ethernet driver will strip of VLAN tag from Rx Ethernet frames and sets tag information in net packet metadata. |
|
Tells what Qemu network model to use. This value is given as a parameter to -nic qemu command line option. |
|
Enable Atmel SAM MCU Family Ethernet driver. |
|
Number of network buffers that will be permanently allocated by the Ethernet driver. These buffers are used in receive path. They are preallocated by the driver and made available to the GMAC module to be filled in with incoming data. Their number has to be large enough to fit at least one complete Ethernet frame. SAM ETH driver will always allocate that amount of buffers for itself thus reducing the NET_BUF_RX_COUNT which is a total amount of RX data buffers used by the whole networking stack. One has to ensure that NET_PKT_RX_COUNT is large enough to fit at least two Ethernet frames: one being received by the GMAC module and the other being processed by the higher layer networking stack. |
|
Which queue to force the routing to. This affects both the TX and RX queues setup. |
|
This option is meant to be used only for debugging. Use it to force all traffic to be routed through a specific hardware queue. With this enabled it is easier to verify whether the chosen hardware queue actually works. This works only if there are four or fewer RX traffic classes enabled, as the SAM GMAC hardware supports screening up to four traffic classes. |
|
IRQ priority of Ethernet device |
|
MAC Address Byte 0 |
|
MAC Address Byte 1 |
|
MAC Address Byte 2 |
|
MAC Address Byte 3 |
|
MAC Address Byte 4 |
|
MAC Address Byte 5 |
|
Device name, e.g. I2C_0, of an I2C bus driver device. It is required to obtain handle to the I2C device object. |
|
Read MAC address from an I2C EEPROM. |
|
Internal address of the EEPROM chip where the MAC address is stored. Chips with 1 to 4 byte internal address size are supported. Address size has to be configured in a separate Kconfig option. |
|
Size (in bytes) of the internal EEPROM address. |
|
I2C 7-bit address of the EEPROM chip. |
|
Assign an arbitrary MAC address. |
|
MII |
|
Device name allows user to obtain a handle to the device object required by all driver API functions. Device name has to be unique. |
|
GMAC PHY Address as used by IEEE 802.3, Section 2 MII compatible PHY transceivers. If you have a single PHY on board it is safe to leave it at 0 which is the broadcast address. |
|
Select the number of hardware queues used by the driver. Packets will be routed to appropriate queues based on their priority. |
|
Generate a random MAC address dynamically. |
|
RMII |
|
Enable driver for SMSC/LAN911x/9220 family of chips. |
|
Stellaris on-board Ethernet Controller |
|
Set the RX idle timeout period in milliseconds after which the PHY’s carrier status is re-evaluated. |
|
Enable STM32 HAL based Ethernet driver. It is available for all Ethernet enabled variants of the F2, F4 and F7 series. |
|
IRQ priority |
|
This is the byte 3 of the MAC address. |
|
This is the byte 4 of the MAC address. |
|
This is the byte 5 of the MAC address. |
|
Use the MII physical interface instead of RMII. |
|
Device name |
|
The phy address to use. |
|
Generate a random MAC address dynamically. |
|
RX thread priority |
|
RX thread stack size |
|
When this option is activated, the buffers for DMA transfer are moved from SRAM to the DTCM (Data Tightly Coupled Memory). |
|
This option enables support of C++ exceptions. |
|
Install handlers for various CPU exception/trap vectors to make debugging them easier, at a small expense in code size. This prints out the specific exception vector and any associated error codes. |
|
The exception stack(s) (one per CPU) are used both for exception processing and early kernel/CPU initialization. They need only support limited call-tree depth and must fit into the low core, so they are typically smaller than the ISR stacks. |
|
If the architecture fatal handling code supports it, attempt to print a stack trace of function memory addresses when an exception is reported. |
|
When enabled, will enforce that a writable page isn’t executable and vice versa. This might not be acceptable in all scenarios, so this option is given for those unafraid of shooting themselves in the foot. If unsure, say Y. |
|
This option enables the tracking of various times inside the kernel the exact set of metrics being tracked is board-dependent. All timing measurements are enabled for X86 and ARM based architectures. In other architectures only a subset is enabled. |
|
Build with external/user provided C library. |
|
Enable EXTI driver for STM32 line of MCUs |
|
IRQ priority of EXTI0 interrupt |
|
IRQ priority of EXTI10 interrupt |
|
IRQ priority of EXTI11 interrupt |
|
IRQ priority of EXTI12 interrupt |
|
IRQ priority of EXTI13 interrupt |
|
IRQ priority of EXTI14 interrupt |
|
IRQ priority of EXTI15:10 interrupt |
|
IRQ priority of EXTI15:4 interrupt |
|
IRQ priority of EXTI15 interrupt |
|
IRQ priority of EXTI1:0 interrupt |
|
IRQ priority of EXTI1 interrupt |
|
IRQ priority of EXTI2 interrupt |
|
IRQ priority of EXTI3:2 interrupt |
|
IRQ priority of EXTI3 interrupt |
|
IRQ priority of EXTI4 interrupt |
|
IRQ priority of EXTI5 interrupt |
|
IRQ priority of EXTI6 interrupt |
|
IRQ priority of EXTI7 interrupt |
|
IRQ priority of EXTI8 interrupt |
|
IRQ priority of EXTI9:5 interrupt |
|
IRQ priority of EXTI9 interrupt |
|
IRQ priority of LPTIM1 interrupt |
|
IRQ priority of USB OTG FS Wake interrupt |
|
IRQ priority of RVD Through interrupt |
|
IRQ priority of RTC Wake Up interrupt |
|
IRQ priority of Tamper and Timestamp interrupt |
|
Have exceptions print additional useful debugging information in human-readable form, at the expense of code size. For example, the cause code for an exception will be supplemented by a string describing what that cause code means. |
|
This option enables the test random number generator for the native_posix board (ARCH_POSIX). This is based on the host random() API. Note that this entropy generator is only meant for test purposes and does not generate real entropy. It actually generates always the same sequence of random numbers if initialized with the same seed. |
|
Use the ELM FAT File system implementation. |
|
Different levels for display information when a fault occurs.
0: Off. |
|
Enable support of Flash Circular Buffer. |
|
Enables support for file system. |
|
Enables LittleFS file system support. |
|
This shell provides basic browsing of the contents of the file system. |
|
Enable support for the flash hardware. |
|
This option specifies the base address of the flash on the board. It is normally set by the board’s defconfig file and the user should generally avoid modifying it via the menu configuration. |
|
This option is enabled when any flash driver is enabled. |
|
This option is enabled when the SoC flash driver supports retrieving the layout of flash memory pages. |
|
This option specifies the byte offset from the beginning of flash that the kernel should be loaded into. Changing this value from zero will affect the Zephyr image’s link, and will decrease the total amount of flash available for use by application code. If unsure, leave at the default value 0. |
|
If non-zero, this option specifies the size, in bytes, of the flash area that the Zephyr image will be allowed to occupy. If zero, the image will be able to occupy from the FLASH_LOAD_OFFSET to the end of the device. If unsure, leave at the default value 0. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable support of flash map abstraction. |
|
This option enables custom flash map description. User must provide such a description in place of default on if had enabled this option. |
|
This enables shell commands to list and test flash maps. |
|
This option can be enabled to force an alternative implementation of the flash driver. |
|
Enables API for retrieving the layout of flash memory pages. |
|
Enable the flash shell with flash related commands such as test, write, read and erase. |
|
Enable the flash simulator. |
|
If selected, writing to a non-erased program unit will succeed, otherwise, it will return an error. Keep in mind that write operations can only pull bits to zero, regardless. |
|
If selected, turning on write protection will also prevent erasing. |
|
Minimum erase time (µS) |
|
Minimum read time (µS) |
|
Minimum write time (µS) |
|
Enable hardware timing simulation |
|
Only up to this number of beginning pages will be tracked while catching dedicated flash operations and thresholds. This number is not automatic because implementation uses UNTIL_REPEAT() macro, which is limited to take explicitly number of iterations. This is why it’s not possible to calculate the number of pages with preprocessor using DT properties. |
|
If selected, the reading operation does not check if access is aligned. Disable this option only if you want to simulate a specific FLASH interface that requires aligned read access. |
|
This option specifies the size of the flash in kB. It is normally set by the board’s defconfig file and the user should generally avoid modifying it via the menu configuration. |
|
Enable output for FLEXPWM1_PWM0 in the driver. Say y here if you want to use FLEXPWM1_PWM0 output. |
|
Enable output for FLEXPWM1_PWM1 in the driver. Say y here if you want to use FLEXPWM1_PWM1 output. |
|
Enable output for FLEXPWM1_PWM2 in the driver. Say y here if you want to use FLEXPWM1_PWM2 output. |
|
Enable output for FLEXPWM1_PWM3 in the driver. Say y here if you want to use FLEXPWM1_PWM3 output. |
|
Enable output for FLEXPWM2_PWM0 in the driver. Say y here if you want to use FLEXPWM2_PWM0 output. |
|
Enable output for FLEXPWM2_PWM1 in the driver. Say y here if you want to use FLEXPWM2_PWM1 output. |
|
Enable output for FLEXPWM2_PWM2 in the driver. Say y here if you want to use FLEXPWM2_PWM2 output. |
|
Enable output for FLEXPWM2_PWM3 in the driver. Say y here if you want to use FLEXPWM2_PWM3 output. |
|
Enable output for FLEXPWM3_PWM0 in the driver. Say y here if you want to use FLEXPWM3_PWM0 output. |
|
Enable output for FLEXPWM3_PWM1 in the driver. Say y here if you want to use FLEXPWM3_PWM1 output. |
|
Enable output for FLEXPWM3_PWM2 in the driver. Say y here if you want to use FLEXPWM3_PWM2 output. |
|
Enable output for FLEXPWM3_PWM3 in the driver. Say y here if you want to use FLEXPWM3_PWM3 output. |
|
Enable output for FLEXPWM4_PWM0 in the driver. Say y here if you want to use FLEXPWM4_PWM0 output. |
|
Enable output for FLEXPWM4_PWM1 in the driver. Say y here if you want to use FLEXPWM4_PWM1 output. |
|
Enable output for FLEXPWM4_PWM2 in the driver. Say y here if you want to use FLEXPWM4_PWM2 output. |
|
Enable output for FLEXPWM4_PWM3 in the driver. Say y here if you want to use FLEXPWM4_PWM3 output. |
|
FlexSPI configuration block consists of parameters regarding specific flash devices including read command sequence, quad mode enablement sequence (optional), etc. The boot ROM expectes FlexSPI configuration parameter to be presented in serail nor flash. |
|
This option allows threads to use the floating point registers. By default, only a single thread may use the registers. Disabling this option means that any thread that uses a floating point register will get a fatal exception. |
|
This option enables the fnmatch library |
|
This boolean option disables Zephyr assertion testing even in circumstances (sanitycheck) where it is enabled via CFLAGS and not Kconfig. Added solely to be able to work around compiler bugs for specific tests. |
|
This option selects the Floating point ABI in which hardware floating point instructions are generated and uses FPU-specific calling conventions |
|
This option allows multiple threads to use the floating point registers. |
|
This option selects the Floating point ABI in which hardware floating point instructions are generated but soft-float calling conventions. |
|
Enable framebuffer-based display ‘helper’ driver. |
|
Valid code page values: 1 - ASCII (No extended character. Non-LFN cfg. only) 437 - U.S. 720 - Arabic 737 - Greek 771 - KBL 775 - Baltic 850 - Latin 1 852 - Latin 2 855 - Cyrillic 857 - Turkish 860 - Portuguese 861 - Icelandic 862 - Hebrew 863 - Canadian French 864 - Arabic 865 - Nordic 866 - Russian 869 - Greek 2 932 - Japanese (DBCS) 936 - Simplified Chinese (DBCS) 949 - Korean (DBCS) 950 - Traditional Chinese (DBCS) |
|
Without long filenames enabled, file names are limited to 8.3 format. This option increases working buffer size. |
|
Enable LFN with static working buffer on the BSS. Always NOT thread-safe. |
|
Enable LFN with dynamic working buffer on the HEAP. |
|
Enable LFN with dynamic working buffer on the STACK. |
|
The working buffer occupies (FS_FATFS_MAX_LFN + 1) * 2 bytes and additional 608 bytes at exFAT enabled. It should be set 255 to support full featured LFN operations. |
|
Maximum number of opened directories |
|
Maximum number of opened files |
|
For dynamic wear leveling, the number of erase cycles before data is moved to another block. Set to a non-positive value to disable leveling. |
|
Each cache buffers a portion of a block in RAM. The littlefs needs a read cache, a program cache, and one additional cache per file. Larger caches can improve performance by storing more data and reducing the number of disk accesses. Must be a multiple of the read and program sizes of the underlying flash device, and a factor of the block size. |
|
littlefs requires a per-file buffer to cache data. For applications that use the default configuration parameters a memory slab is reserved to support up to FS_LITTLE_FS_NUM_FILES blocks of FS_LITTLEFS_CACHE_SIZE bytes. When applications customize littlefs configurations and support different cache sizes for different partitions this preallocation is inadequate. Select this feature to enable a memory pool allocator for littlefs file caches. |
|
Maximum block size for littlefs file cache memory pool |
|
Minimum block size for littlefs file cache memory pool |
|
Number of maximum sized blocks in littlefs file cache memory pool |
|
A larger lookahead buffer increases the number of blocks found during an allocation pass. The lookahead buffer is stored as a compact bitmap, so each byte of RAM can track 8 blocks. Must be a multiple of 8. |
|
This is a global maximum across all mounted littlefs filesystems. |
|
This is a global maximum across all mounted littlefs filesystems. |
|
All program operations will be a multiple of this value. |
|
All read operations will be a multiple of this value. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Limits the maximum chunk size for file downloads, in bytes. A buffer of this size gets allocated on the stack during handling of a file download command. |
|
Limits the maximum path length for file operations, in bytes. A buffer of this size gets allocated on the stack during handling of file upload and download commands. |
|
Limits the maximum chunk size for file uploads, in bytes. A buffer of this size gets allocated on the stack during handling of a file upload command. |
|
Expose file system partitions to the host system through FUSE. |
|
Enable driver for the FXAS21002 gyroscope |
|
Selects the output data rate 0: 800 Hz 1: 400 Hz 2: 200 Hz 3: 100 Hz 4: 50 Hz 5: 25 Hz 6: 12.5 Hz 7: 12.5 Hz |
|
Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin. |
|
Selects the full scale range 0: +/-2000 dps (62.5 mdps/LSB) 1: +/-1000 dps (31.25 mdps/LSB) 2: +/-500 dps (15.625 mdps/LSB) 3: +/-250 dps (7.8125 mdps/LSB) |
|
Own thread priority |
|
Own thread stack size |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
The datasheet defines the value of the WHOAMI register, but some pre-production devices can have a different value. It is unlikely you should need to change this configuration option from the default. |
|
Enable driver for the FXOS8700 accelerometer/magnetometer. The driver also supports MMA8451Q, MMA8652FC and MMA8653FC accelerometers. If the driver is used with one of these accelerometers then the Accelerometer-only mode should be selected.” |
|
Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin. |
|
Accelerometer-only mode |
|
Hybrid (accel+mag) mode |
|
Magnetometer-only mode |
|
Enable motion detection |
|
Say Y to route motion interrupt to INT1 pin. Say N to route to INT2 pin. |
|
High resolution power mode |
|
Low noise low power mode |
|
Low power mode |
|
Normal power mode |
|
Enable pulse detection |
|
Pulse configuration register |
|
Say Y to route pulse interrupt to INT1 pin. Say N to route to INT2 pin. |
|
The time interval that starts after the first pulse detection where the pulse-detection function ignores the start of a new pulse. The resolution depends upon the sample rate (ODR) and the high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and pls_hpf_en=0, the resolution is 1.25 ms/LSB. |
|
Threshold to start the pulse-event detection procedure on the X-axis. Threshold values for each axis are unsigned 7-bit numbers with a fixed resolution of 0.063 g/LSB, corresponding to an 8g acceleration full-scale range. |
|
Threshold to start the pulse-event detection procedure on the Y-axis. Threshold values for each axis are unsigned 7-bit numbers with a fixed resolution of 0.063 g/LSB, corresponding to an 8g acceleration full-scale range. |
|
Threshold to start the pulse-event detection procedure on the Z-axis. Threshold values for each axis are unsigned 7-bit numbers with a fixed resolution of 0.063 g/LSB, corresponding to an 8g acceleration full-scale range. |
|
The maximum time interval that can elapse between the start of the acceleration on the selected channel exceeding the specified threshold and the end when the channel acceleration goes back below the specified threshold. The resolution depends upon the sample rate (ODR) and the high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and pls_hpf_en=0, the resolution is 0.625 ms/LSB. |
|
The maximum interval of time that can elapse after the end of the latency interval in which the start of the second pulse event must be detected provided the device has been configured for double pulse detection. The detected second pulse width must be shorter than the time limit constraint specified by the PULSE_TMLT register, but the end of the double pulse need not finish within the time specified by the PULSE_WIND register. The resolution depends upon the sample rate (ODR) and the high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and pls_hpf_en=0, the resolution is 1.25 ms/LSB. |
|
2g (0.244 mg/LSB) |
|
4g (0.488 mg/LSB) |
|
8g (0.976 mg/LSB) |
|
Enable the temperature sensor. Note that the temperature sensor is uncalibrated and its output for a given temperature may vary from one device to the next. |
|
Own thread priority |
|
Own thread stack size |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for GD7965 compatible controller. |
|
This option stores the GDT in RAM instead of ROM, so that it may be modified at runtime at the expense of some memory. |
|
On some architectures, part of the vector table may be reserved for system exceptions and is declared separately from the tables created by gen_isr_tables.py. When creating these tables, this value will be subtracted from CONFIG_NUM_IRQS to properly size them. This is a hidden option which needs to be set per architecture and left alone. |
|
This option controls whether a platform using gen_isr_tables needs an interrupt vector table created. Only disable this if the platform does not use a vector table at all, or requires the vector table to be in a format that is not an array of function pointers indexed by IRQ line. In the latter case, the vector table must be supplied by the application or architecture code. |
|
This option controls whether a platform uses the gen_isr_tables script to generate its interrupt tables. This mechanism will create an appropriate hardware vector table and/or software IRQ table. |
|
This option controls whether a platform using gen_isr_tables needs a software ISR table table created. This is an array of struct _isr_table_entry containing the interrupt service routine and supplied parameter. |
|
The ARM Generic Interrupt Controller v1 (e.g. PL390) works with the ARM Cortex-family processors. |
|
The ARM Generic Interrupt Controller v2 (e.g. GIC-400) works with the ARM Cortex-family processors. |
|
The ARM Generic Interrupt Controller v3 (e.g. GIC-500 and GIC-600) works with the ARM Cortex-family processors. |
|
Include GPIO drivers in system config |
|
GPIO as pin reset (reset button) |
|
Enable GPIO port A support |
|
Enable GPIO port B support |
|
Enable the TI SimpleLink CC13xx / CC26xx GPIO driver. |
|
Enable the GPIO driver on TI SimpleLink CC32xx boards |
|
Include support for the GPIO port A0. |
|
Include support for the GPIO port A1. |
|
Include support for the GPIO port A2. |
|
Include support for the GPIO port A3. |
|
Enable config options to support the ARM CMSDK GPIO controllers. Says n if not sure. |
|
Build the driver to utilize GPIO controller Port 0. |
|
Device name for Port 0. |
|
Interrupt priority for Port 0. |
|
Build the driver to utilize GPIO controller Port 1. |
|
Device name for Port 1. |
|
Interrupt priority for Port 1. |
|
Build the driver to utilize GPIO controller Port 2. |
|
Device name for Port 2. |
|
Interrupt priority for Port 2. |
|
Build the driver to utilize GPIO controller Port 3. |
|
Device name for Port 3. |
|
Interrupt priority for Port 3. |
|
Enable GPIO port C support |
|
Enable driver for Designware GPIO |
|
Include Designware GPIO driver |
|
Clock controller’s subsystem |
|
When interrupts fire, the driver’s ISR function is being called directly. |
|
IRQ priority |
|
When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers. |
|
Driver name |
|
Include Designware GPIO driver |
|
Clock controller’s subsystem |
|
When interrupts fire, the driver’s ISR function is being called directly. |
|
IRQ priority |
|
When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers. |
|
Driver name |
|
Include Designware GPIO driver |
|
Clock controller’s subsystem |
|
When interrupts fire, the driver’s ISR function is being called directly. |
|
IRQ priority |
|
When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers. |
|
Driver name |
|
Include Designware GPIO driver |
|
Clock controller’s subsystem |
|
When interrupts fire, the driver’s ISR function is being called directly. |
|
IRQ priority |
|
When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers. |
|
Driver name |
|
Enable clock gating |
|
Device driver initialization priority. |
|
Enable GPIO port D support |
|
Enables the ESP32 GPIO driver |
|
Include support for GPIO pins 0-31 on the ESP32. |
|
Include support for GPIO pins 32-39 on the ESP32. |
|
Select the IRQ line to be used for GPIO interrupts. Edge-triggered interrupts are supported on lines: 10, 22, 28, 30. Level-triggered interrupts are supported on lines: 0-5, 8, 9, 12, 13, 17-21, 23-27, 31. |
|
Enable GPIO port E support |
|
Enable GPIO port F support |
|
Enable the Gecko gpio driver. |
|
Common initialization priority |
|
Enable Port A. |
|
Enable Port B. |
|
Enable Port C. |
|
Enable Port D. |
|
Enable Port E. |
|
Enable Port F. |
|
Enable Port G. |
|
Enable Port H. |
|
Enable Port I. |
|
Enable Port J. |
|
Enable Port K. |
|
Enable GPIO port G support |
|
Enable keyscan driver for HT16K33. The HT16K33 is a memory mapping, multifunction LED controller driver. The controller supports matrix key scan circuit of up to 13x3 keys. The keyscan functionality is exposed as up to 3 GPIO controller drivers, each supporting GPIO callbacks for keyscan event notifications. |
|
Device driver initialization priority. This driver must be initialized after the HT16K33 LED driver. |
|
Enable the IMX GPIO driver. |
|
Enable Port 1. |
|
Enable Port 2. |
|
Enable Port 3. |
|
Enable Port 4. |
|
Enable Port 5. |
|
Enable Port 6. |
|
Enable Port 7. |
|
Enable driver for Intel Apollo Lake SoC GPIO |
|
This option enables the checks to make sure the GPIO pin can be manipulated. Only if the pin is owned by the host software and its functioning as GPIO, then the driver allows manipulating the pin. Say y if unsure. |
|
Enable Litex GPIO driver. |
|
Enable GPIO driver for LMP90xxx. The LMP90xxx is a multi-channel, low power sensor analog frontend (AFE). The GPIO port of the LMP90xxx (D6 to D0) is exposed as a GPIO controller driver with read/write support. |
|
Device driver initialization priority. This driver must be initialized after the LMP90xxx ADC driver. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable the MCUX pinmux driver. |
|
Enable the MCUX IGPIO driver. |
|
Enable Port 1. |
|
Enable Port 2. |
|
Enable Port 3. |
|
Enable Port 4. |
|
Enable Port 5. |
|
Enable the MCUX LPC pinmux driver. |
|
Enable Port 0. |
|
Port 0 driver name |
|
Enable Port 1. |
|
Port 1 driver name |
|
Enable Port A. |
|
Enable Port B. |
|
Enable Port C. |
|
Enable Port D. |
|
Enable Port E. |
|
This is a driver for accessing a simple, fixed purpose, 32-bit memory-mapped i/o register using the same APIs as GPIO drivers. This is useful when an SoC or board has registers that aren’t part of a GPIO IP block and these registers are used to control things that Zephyr normally expects to be specified using a GPIO pin, e.g. for driving an LED, or chip-select line for an SPI device. |
|
Enable GPIO driver for nRF line of MCUs. |
|
Initialization priority for nRF GPIO. |
|
Enable nRF GPIO port P0 config options. |
|
Enable nRF GPIO port P1 config options. |
|
Enable driver for PCA95XX I2C-based GPIO chip. |
|
Device driver initialization priority. |
|
Enable the RV32M1 GPIO driver. |
|
Enable Port A. |
|
Enable Port B. |
|
Enable Port C. |
|
Enable Port D. |
|
Enable Port E. |
|
Enable support for the Atmel SAM ‘PORT’ GPIO controllers. |
|
Enable support for the Atmel SAM0 ‘PORT’ GPIO controllers. |
|
Enable GPIO Shell for testing. |
|
Enable driver for the SiFive Freedom GPIO controller. Says n if not sure. |
|
GPIO 0 interrupt priority |
|
GPIO 10 interrupt priority |
|
GPIO 11 interrupt priority |
|
GPIO 12 interrupt priority |
|
GPIO 13 interrupt priority |
|
GPIO 14 interrupt priority |
|
GPIO 15 interrupt priority |
|
GPIO 16 interrupt priority |
|
GPIO 17 interrupt priority |
|
GPIO 18 interrupt priority |
|
GPIO 19 interrupt priority |
|
GPIO 1 interrupt priority |
|
GPIO 20 interrupt priority |
|
GPIO 21 interrupt priority |
|
GPIO 22 interrupt priority |
|
GPIO 23 interrupt priority |
|
GPIO 24 interrupt priority |
|
GPIO 25 interrupt priority |
|
GPIO 26 interrupt priority |
|
GPIO 27 interrupt priority |
|
GPIO 28 interrupt priority |
|
GPIO 29 interrupt priority |
|
GPIO 2 interrupt priority |
|
GPIO 30 interrupt priority |
|
GPIO 31 interrupt priority |
|
GPIO 3 interrupt priority |
|
GPIO 4 interrupt priority |
|
GPIO 5 interrupt priority |
|
GPIO 6 interrupt priority |
|
GPIO 7 interrupt priority |
|
GPIO 8 interrupt priority |
|
GPIO 9 interrupt priority |
|
Enable support for the Stellaris GPIO controllers. |
|
Enable GPIO driver for STM32 line of MCUs |
|
Enable GPIO port A support |
|
Enable GPIO port B support |
|
Enable GPIO port C support |
|
Enable GPIO port D support |
|
Enable GPIO port E support |
|
Enable GPIO port F support |
|
Enable GPIO port G support |
|
Enable GPIO port H support |
|
Enable GPIO port I support |
|
Enable GPIO port J support |
|
Enable GPIO port K support |
|
JTAG-DP Disabled and SW-DP Disabled |
|
Full SWJ (JTAG-DP + SW-DP): Reset State |
|
JTAG-DP Disabled and SW-DP Enabled |
|
Full SWJ (JTAG-DP + SW-DP) but without NJTRST |
|
Enable driver for SX1509B I2C GPIO chip. |
|
Device driver initialization priority. |
|
Enable the Microchip XEC gpio driver. |
|
Enable GPIO 000-036 or what would be equivalent to PortA. |
|
Enable GPIO 040-076 or what would be equivalent to Port B |
|
Enable GPIO 100-136 or what would be equivalent to Port C |
|
Enable GPIO 140-176 or what would be equivalent to Port C |
|
Enable GPIO 200-236 or what would be equivalent to Port D |
|
Enable GPIO 240-276 or what would be equivalent to Port E |
|
Use GP relative access for all data in the program, not just small data. Use this if your board has 64K or less of RAM. |
|
Use global pointer relative offsets for small globals declared anywhere in the executable. Note that if any small globals that are put in alternate sections they must be declared in headers with proper __attribute__((section)) or the linker will error out. |
|
Use global pointer relative offsets for small globals declared in the same C file as the code that uses it. |
|
Do not use global pointer relative offsets at all |
|
Setting this value will enable driver support for the Groove-LCD RGB Backlight. |
|
Specify the device name of the I2C master device to which the Grove LCD is connected. |
|
Setting this value will enable driver support for the Grove Light Sensor. |
|
Setting this value will enable driver support for the Grove Temperature Sensor. |
|
Enables a cryptographically secure random number generator that uses the enabled hardware random number driver to generate random numbers. |
|
The ARC CPU can be configured to have two busses; one for instruction fetching and another that serves as a data bus. |
|
Altera HAL drivers support |
|
Has the divider for ARM |
|
The code coverage report generation is only available on boards with enough spare RAM to buffer the coverage data, or on boards based on the POSIX ARCH. |
|
This option specifies that the target platform supports device tree configuration. |
|
This option specifies that the target platform supports device tree configuration for entropy/random number. |
|
This option specifies that the target platform supports device tree configuration for GPIO. |
|
This option specifies that the target platform supports device tree configuration for I2c. |
|
This option specifies that the target platform supports device tree configuration for WDT. |
|
This option is selected by targets having a FLASH_LOAD_OFFSET and FLASH_LOAD_SIZE. |
|
Set if the EPIT module is present in the SoC. |
|
Set if the GPIO module is present in the SoC. |
|
Set if the I2C module is present in the SoC. |
|
Set if the multipurpose clock generator (MCG) module is present in the SoC. |
|
Set if the 12-bit ADC (ADC12) module is present in the SoC. |
|
Set if the 16-bit ADC (ADC16) module is present in the SoC. |
|
Set if the L1 or L2 cache is present in the SoC. |
|
Set if the clock control module (CCM) module is present in the SoC. |
|
Set if the CMOS Sensor Interface module is present in the SoC. |
|
Set if the enhanced LCD interface (eLCDIF) module is present in the SoC. |
|
Set if the ethernet (ENET) module is present in the SoC. |
|
Set if the FlexCAN module is presents in the SoC. |
|
Set if the flexcomm (FLEXCOMM) module is present in the SoC. |
|
Set if the flash memory (FTFA, FTFE, or FTFL) module is present in the SoC. |
|
Set if the FlexTimer (FTM) module is present in the SoC. |
|
Set if the general purpose timer (GPT) module is present in the SoC. |
|
Set if the flash memory In Applcation Programming is present in the LPC family SoCs. |
|
Set if the iMX GPIO (IGPIO) module is present in the SoC. |
|
Set if the low power I2C (LPI2C) module is present in the SoC. |
|
Set if the low power uart (LPSCI) module is present in the SoC. |
|
Set if the low power SPI (LPSPI) module is present in the SoC. |
|
Set if the low power uart (LPUART) module is present in the SoC. |
|
Set if the peripheral clock controller module (PCC) module is present in the SoC. |
|
Set if the PWM module is present in the SoC. |
|
Set if the random number generator accelerator (RNGA) module is present in the SoC. |
|
Set if the real time clock (RTC) modules is present in the SoC. |
|
Set if the system clock generator (SCG) module is present in the SoC. |
|
Set if the system integration module (SIM) module is present in the SoC. |
|
Set if the SMC module is present in the SoC. |
|
Set if the true random number generator (TRNG) module is present in the SoC. |
|
Set if the USB controller EHCI module is present in the SoC. |
|
Set if the USDHC instance 1 module is present in the SoC. |
|
Set if the USDHC2 instance 2 module is present in the SoC. |
|
Set if the watchdog (WDOG32) module is present in the SoC. |
|
Microchip MEC HAL drivers support |
|
Set if the oscillator (OSC) module is present in the SoC. |
|
Set if the flash memory (FTFA, FTFE, or FTFL) module is present in the SoC. |
|
Set if the low power i2c (LPI2C) module is present in the SoC. |
|
Set if the low power spi (LPSPI) module is present in the SoC. |
|
Set if the low power uart (LPUART) module is present in the SoC. |
|
Set if the Timer/PWM (TPM) module is present in the SoC. |
|
This option specifies that the target board has SDL support |
|
Indicates that the platform supports SEGGER J-Link RTT. |
|
This option enables the use of Semtech’s LoRaMac stack |
|
This option enables the use of Semtech’s Radio drivers |
|
Signifies whether DesignWare SPI compatible HW is available |
|
When enabled, indicates that SoC has an SWO output |
|
This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_1 configuration option. |
|
This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_2 configuration option. |
|
This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_3 configuration option. |
|
This option signifies that the target supports the SYS_POWER_STATE_SLEEP_1 configuration option. |
|
This option signifies that the target supports the SYS_POWER_STATE_SLEEP_2 configuration option. |
|
This option signifies that the target supports the SYS_POWER_STATE_SLEEP_3 configuration option. |
|
Selected when CCFG (Customer Configuration) registers appear at the end of flash |
|
Set this option if you have a custom linker script which needed to be define in CUSTOM_LINKER_SCRIPT. |
|
This option specifies the size of the smallest block in the pool. Option must be a power of 2 and lower than or equal to the size of the entire pool. |
|
This option specifies the size of the heap memory pool used when dynamically allocating memory using k_malloc(). Supported values are: 256, 1024, 4096, and 16384. A size of zero means that no heap memory pool is defined. |
|
USB HID Device interrupt endpoint size |
|
Enable driver for HMC5883L I2C-based magnetometer. |
|
Magnetometer full-scale range. An X value for the config represents a range of +/- X gauss. Valid values are 0.88, 1.3, 1.9, 2.5, 4, 4.7, 5.6 and 8.1. |
|
Magnetometer output data rate expressed in samples per second. Data rates supported by the chip are 0.75, 1.5, 3, 7.5, 15, 30 and 75. |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable HopeRF HP206C barometer and altimeter support. |
|
Value, in cm, that will be used to compensate altitude calculation. For more info on how to choose this value, consult section 6.1.1 in the datasheet. |
|
Altitude offset set at runtime |
|
Allowed values: 4096, 2048, 1024, 512, 256, 128 |
|
Oversampling rate set at runtime |
|
This option selects High Precision Event Timer (HPET) as a system timer. |
|
Enable LED driver for HT16K33. The HT16K33 is a memory mapping, multifunction LED controller driver. The controller supports up to 128 LEDs (up to 16 rows and 8 commons). |
|
Enable keyscan child device support in the HT16K33 LED driver. The keyscan functionality itself is handled by the HT16K33 GPIO driver. |
|
Keyscan debounce interval in milliseconds. |
|
Priority level for internal thread for keyscan interrupt processing. |
|
Size of the stack used for internal thread for keyscan interrupt processing. |
|
Keyscan poll interval in milliseconds. Polling is only used if no interrupt line is present. |
|
Enable driver for HTS221 I2C-based temperature and humidity sensor. |
|
Sensor output data rate expressed in samples per second. Data rates supported by the chip are 1, 7 and 12.5. |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
HTTP client API |
|
This option enables the http_parser library from nodejs. This parser requires some string-related routines commonly provided by a libc implementation. |
|
This option enables the strict parsing option |
|
This option enables the URI parser library based on source from nodejs. This parser requires some string-related routines commonly provided by a libc implementation. |
|
Enable hwinfo driver. |
|
Enable ESP32 hwinfo driver. |
|
Enable NXP i.mx RT hwinfo driver. |
|
Enable LiteX hwinfo driver |
|
Enable NXP kinetis mcux hwinfo driver. |
|
Enable Nordic NRF hwinfo driver. |
|
Enable Atmel SAM hwinfo driver. |
|
Enable Atmel SAM0 hwinfo driver. |
|
Enable hwinfo Shell for testing. |
|
Enable STM32 hwinfo driver. |
|
Select this option to enable hardware-based platform features to catch stack overflows when the system is running in privileged mode. If CONFIG_USERSPACE is not enabled, the system is always running in privileged mode. Note that this does not necessarily prevent corruption and assertions about the overall system state when a fault is triggered cannot be made. |
|
Enable I2C Driver Configuration |
|
Enable I2C Port 0 |
|
IRQ priority. |
|
Enable nRF TWI Master without EasyDMA on port 0. |
|
Enable nRF TWI Master with EasyDMA on port 0. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail. |
|
Enable I2C Port 1 |
|
Enable nRF TWI Master without EasyDMA on port 1. |
|
Enable nRF TWI Master with EasyDMA on port 1. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail. |
|
Enable I2C Port 2 |
|
Enable nRF TWI Master with EasyDMA on port 2. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail. |
|
Enable I2C Port 3 |
|
Enable nRF TWI Master with EasyDMA on port 3. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail. |
|
Enable I2C Port 4 |
|
Enable I2C Port 5 |
|
Enable I2C Port 6 |
|
Enable I2C Port 7 |
|
Enable library used for software driven (bit banging) I2C support |
|
Enable support for I2C on the TI SimpleLink CC13xx / CC26xx series. |
|
Enable the CC32XX I2C driver. |
|
Enable the Design Ware I2C driver |
|
Set the clock speed for I2C |
|
Enable virtual I2C Slave EEPROM driver |
|
Enables the ESP32 I2C driver |
|
Port 0 IRQ line |
|
Port 0 Receive LSB first |
|
Port 0 Transmit LSB first |
|
Port 1 IRQ line |
|
Port 1 Receive LSB first |
|
Port 1 Transmit LSB first |
|
I2C timeout to receive a data bit in APB clock cycles |
|
Enable the SiLabs Gecko I2C bus driver. |
|
Enable software driven (bit banging) I2C support using GPIO pins |
|
This tells the driver to configure the I2C device at boot, depending on the additional configuration options below. |
|
This is the name of the GPIO device that controls the I2C lines. |
|
This is the device name for the I2C device, and is included in the device struct. |
|
This is the GPIO pin number for the I2S SCL line |
|
This is the GPIO pin number for the I2S SDA line |
|
This tells the driver to configure the I2C device at boot, depending on the additional configuration options below. |
|
This is the name of the GPIO device that controls the I2C lines. |
|
This is the device name for the I2C device, and is included in the device struct. |
|
This is the GPIO pin number for the I2S SCL line |
|
This is the GPIO pin number for the I2S SDA line |
|
This tells the driver to configure the I2C device at boot, depending on the additional configuration options below. |
|
This is the name of the GPIO device that controls the I2C lines. |
|
This is the device name for the I2C device, and is included in the device struct. |
|
This is the GPIO pin number for the I2S SCL line |
|
This is the GPIO pin number for the I2S SDA line |
|
This tells the driver to configure the I2C device at boot, depending on the additional configuration options below. |
|
This is the name of the GPIO device that controls the I2C lines. |
|
This is the device name for the I2C device, and is included in the device struct. |
|
This is the GPIO pin number for the I2C SCL line |
|
This is the GPIO pin number for the I2C SDA line |
|
Enable the i.MX I2C driver. |
|
I2C device driver initialization priority. |
|
Enable support for Litex I2C driver |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable the mcux I2C driver. |
|
Enable the mcux LPI2C driver. |
|
Enable the Nios-II I2C driver. |
|
Enable support for nrfx TWI drivers for nRF MCU series. Peripherals with the same instance ID cannot be used together, e.g. I2C_0 and SPI_0. You may need to disable SPI_0 or SPI_1. |
|
Enable the RV32M1 LPI2C driver. |
|
Enable the SAM0 series SERCOM I2C driver. |
|
This enables DMA driven transactions for the I2C peripheral. DMA driven mode requires fewer interrupts to handle the transaction and ensures that high speed modes are not delayed by data reloading. |
|
Enable Atmel SAM MCU Family (TWI) I2C bus driver. |
|
Enable Atmel SAM MCU Family (TWIHS) I2C bus driver. |
|
I2C driver for ARM’s SBCon two-wire serial bus interface |
|
Enable I2C Shell. The I2C shell currently support scanning. |
|
Enable I2C support on SiFive Freedom |
|
Enable I2C Slave Driver Configuration |
|
I2C Slave device driver initialization priority. |
|
Enable I2C support on the STM32 SoCs |
|
Enable Interrupt support for the I2C Driver |
|
Enable I2C support on the STM32 F1 and F4X family of processors. This driver also supports the F2 and L1 series. |
|
Enable I2C support on the STM32 F0, F3, F7, L4, WBX, MP1, G0 and G4 family of processors. This driver also supports the L0 series. If I2C_SLAVE is enabled it selects I2C_STM32_INTERRUPT, since slave mode is only supported by this driver with interrupts enabled. |
|
Enable the Microchip XEC I2C driver. |
|
Enable support for the I2S (Inter-IC Sound) hardware bus. |
|
Enable I2S controller port 1. |
|
Enable I2S controller port 2. |
|
Enable I2S controller port 3. |
|
Enable I2S controller port 4. |
|
Enable I2S controller port 5. |
|
Enable Inter Sound (I2S) bus driver for Intel_S1000 based on Synchronous Serial Port (SSP) module. |
|
DMA channel number to use for I2S1 RX transfer. |
|
DMA channel number to use for I2S1 TX transfer. |
|
I2S 1 device name |
|
DMA channel number to use for I2S2 RX transfer. |
|
DMA channel number to use for I2S2 TX transfer. |
|
I2S 2 device name |
|
DMA channel number to use for I2S3 RX transfer. |
|
DMA channel number to use for I2S3 TX transfer. |
|
I2S 3 device name |
|
Name of the DMA device this device driver can use. |
|
Interrupt priority |
|
Device driver initialization priority. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable Inter Sound (I2S) bus driver for Atmel SAM MCU family based on Synchronous Serial Controller (SSC) module. |
|
DMA channel number to use for RX transfers. |
|
DMA channel number to use for TX transfers. |
|
Interrupt priority |
|
I2S 0 device name |
|
If enabled RF signal is connected to RF pin. It will be configured as an output or an input depending on whether the receiver is working in master or slave mode. If disabled RF signal is disconnected from RF pin and connected internally to TF (Transmitter Frame Synchro signal). |
|
If enabled RK signal is connected to RK pin. It will be configured as an output or an input depending on whether the receiver is working in master or slave mode. If disabled RK signal is disconnected from RK pin and connected internally to TK (Transmitter Clock signal). |
|
PB5 |
|
PD10 |
|
PD26 |
|
Name of the DMA device this device driver can use. |
|
RX queue length |
|
TX queue length |
|
Enable I2S support on the STM32 family of processors. (Tested on the STM32F4 series) |
|
Division factor for the audio PLL (PLLI2S) VCO input clock. PLLM factor should be selected to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63 |
|
Multiply factor for the audio PLL (PLLI2S) VCO output clock. PLLN factor should be selected to ensure that the VCO output frequency ranges from 100 to 432 MHz. Allowed values: 50-432 |
|
Division factor for the I2S clock. PLLR factor should be selected to ensure that the I2S clock frequency is less than or equal to 192MHz. Allowed values: 2-7 |
|
RX queue length |
|
TX queue length |
|
Enable it if I2S clock should be provided by the PLLI2S. If not enabled the clock will be provided by HSI/HSE. |
|
Number of retries when reading failed or device not ready. |
|
Depending on the work that the idle task must do, most likely due to power management but possibly to other features like system event logging (e.g. logging when the system goes to sleep), the idle thread may need more stack space than the default value. |
|
This option specifies the number of interrupt vector entries in the Interrupt Descriptor Table (IDT). By default all 256 vectors are supported in an IDT requiring 2048 bytes of memory. |
|
IEEE 802.15.4 drivers options |
|
TI CC1200 Driver support |
|
Set the CCA threshold. See datasheet’s AGC_CS_THR register for more information. Do not touch this unless you know what you are doing. |
|
This option sets the driver name |
|
This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic. |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware cc1200 requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack. |
|
This is the byte 4 of the MAC address. |
|
This is the byte 5 of the MAC address. |
|
This is the byte 6 of the MAC address. |
|
This is the byte 7 of the MAC address. |
|
Generate a random MAC address dynamically. |
|
Use TI CC1200 RF pre-sets |
|
868MHz - 50Kbps - 2-GFSK - IEEE 802.15.4g compliant - ETSI |
|
920MHz - 50Kbps - 2-GFSK - IEEE 802.15.4g compliant - ARIB |
|
434MHz - 50Kbps - 2-GFSK - IEEE 802.15.4g compliant - ETSI |
|
Set the gain adjustment. See datasheet’s AGC_GAIN_ADJUST register for more information. Do not touch this unless you know what you are doing. |
|
This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size. |
|
This sets the XOSC value, it must be between 38400 and 40000. This value should follow what has been set in the RF settings via SmartRF tool. Do not touch this unless you know what you are doing. |
|
TI CC13xx / CC26xx IEEE 802.15.4 driver support |
|
This option sets the driver name. |
|
Set the initialization priority number. |
|
This option sets the driver’s stack size for its internal RX thread. |
|
TI CC2520 Driver support |
|
This option will expose the hardware AES encryption from CC2520. Such feature should not be used for anything but 802.15.4 security. The crypto device exposed will only support synchronous CCM operation. |
|
This option sets the driver name for the crypto part found on CC2520. |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. It should be initialized after CC2520 as it shares the same runtime context. |
|
This option sets the driver name |
|
This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic. |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware cc2520 requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack. |
|
This is the byte 4 of the MAC address. |
|
This is the byte 5 of the MAC address. |
|
This is the byte 6 of the MAC address. |
|
This is the byte 7 of the MAC address. |
|
Generate a random MAC address dynamically. |
|
This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
NXP KW41Z Driver support |
|
This option sets the driver name. Do not change it unless you know what you are doing. |
|
Set the initialization priority number. Do not change it unless you know what you are doing. It has to start before the net stack. |
|
NXP MCR20A Driver support |
|
This option sets the driver name |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware mcr20a requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack. |
|
This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size. |
|
nRF52 series IEEE 802.15.4 Driver |
|
This option sets the driver name |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. |
|
This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size. |
|
This option enables using the drivers in a so-called “raw” mode, i.e. without a MAC stack (the net L2 layer for 802.15.4 will not be built). Used only for very specific cases, such as wpan_serial and wpanusb samples. |
|
ATMEL RF2XX Driver support |
|
This option sets the driver name |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware rf2xx requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack. |
|
This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size. |
|
UART PIPE fake radio driver support for QEMU |
|
UART PIPE Driver name |
|
This option assure the driver will process just frames addressed to him. |
|
This is the byte 4 of the MAC address. |
|
This is the byte 5 of the MAC address. |
|
This is the byte 6 of the MAC address. |
|
This is the byte 7 of the MAC address. |
|
Generate a random MAC address dynamically. |
|
Enable driver for IIS3DHHC SPI-based accelerometer sensor. |
|
Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin. |
|
Enable Sensor at 1KHz |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for ILI9340 display driver. |
|
Adafruit 2.2” TFT 1480 |
|
Seeed 2.8” TFT v2.0 |
|
RGB565 |
|
RGB888 |
|
The Image Vector Table (IVT) provides the boot ROM with pointers to the application entry point and device configuration data. The boot ROM requires a fixed IVT offset for each type of boot device. |
|
Size (in Bytes) of buffer for image writer. Must be a multiple of the access alignment required by used flash driver. |
|
If enabled, flash is erased as necessary when receiving new firmware, instead of erasing the whole image slot at once. This is necessary on some hardware that has long erase times, to prevent long wait times at the beginning of the DFU process. |
|
Enable support for managing DFU image. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Limits the maximum chunk size for image uploads, in bytes. A buffer of this size gets allocated on the stack during handling of a image upload command. |
|
Include the reset vector stub, which enables instruction/data caches and then jumps to __start. This code is typically located at the very beginning of flash memory. You may need to omit this if using the nios2-download tool since it refuses to load data anywhere other than RAM. |
|
Initialize ARM PLL |
|
If y, the Ethernet PLL is initialized. Always enabled on e.g. MIMXRT1021 - see commit 17f4d6bec7 (“soc: nxp_imx: fix ENET_PLL selection for MIMXRT1021”). |
|
This option instructs the kernel to initialize stack areas with a known value (0xaa) before they are first used, so that the high water mark can be easily determined. This applies to the stack areas for threads, as well as to the interrupt stack. |
|
Initialize SYS PLL |
|
Initialize USB1 PLL |
|
Initialize Video PLL |
|
Enable support for Intel’s GMM and Neural Network Accelerator |
|
Device driver initialization priority. |
|
Max. number of unique neural network models required in the system |
|
Maximum number of pending inference requests in the driver |
|
Name of the GNA device this device driver can use. |
|
Sets GNA operation mode for power saving Levels are: 0 ALWAYS_ON, GNA is always on with very minimal power save 1 CLOCK_GATED, GNA clock is gated when not active 2 POWER_GATED, GNA clock and power are gated when not active 3 ALWAYS_OFF, GNA is tuned off and never used in the system |
|
This option signifies that the target has an IO-APIC device. This capability allows IO-APIC-dependent code to be included. |
|
At boot, mask all IOAPIC RTEs if they may be in an undefined state. You don’t need this if the RTEs are either all guaranteed to be masked when the OS starts up, or a previous boot stage has done some IOAPIC configuration that needs to be preserved. |
|
This option indicates the maximum number of Redirection Table Entries (RTEs) (one per IRQ available to the IO-APIC) made available to the kernel, regardless of the number provided by the hardware itself. For most efficient usage of memory, it should match the number of IRQ lines needed by devices connected to the IO-APIC. |
|
IPG clock divider |
|
Include interrupt-based inter-processor mailboxes drivers in system configuration |
|
Enable the receiving side of IPM console |
|
Enable the sending side of IPM console |
|
Each instance of the IPM console receiver driver creates a worker thread to print out incoming messages from the remote CPU. Specify the stack size for these threads here. |
|
Driver for NXP i.MX messaging unit |
|
There will be a single message type with id 0 and a maximum size of 16 bytes. |
|
There will be four message types with ids 0, 1, 2 or 3 and a maximum size of 4 bytes each. |
|
There will be two message types with ids 0 or 1 and a maximum size of 8 bytes each. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Driver for MCUX mailbox |
|
Driver for SSE 200 MHU (Message Handling Unit) |
|
Enable IPM Message Channel 0 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 10 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 11 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 12 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 13 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 14 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 15 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 1 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 2 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 3 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 4 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 5 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 6 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 7 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 8 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 9 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Driver for Nordic nRF messaging unit, based on nRF IPC peripheral HW. |
|
Enable this option if the IPM device should have a single instance, instead of one per IPC message channel. |
|
Driver for stm32 IPCC mailboxes |
|
use to define the Processor ID for IPCC access |
|
Enable irq_offload() API which allows functions to be synchronously run in interrupt context. Only useful for test cases that need to validate the correctness of kernel objects in IRQ context. |
|
The index of the software interrupt to be used for IRQ offload. Please note that in order for IRQ offload to work correctly the selected interrupt shall have its priority shall not exceed XCHAL_EXCM_LEVEL. |
|
IDT vector to use for IRQ offload |
|
From: https://developer.arm.com/products/architecture/instruction-sets/a32-and-t32-instruction-sets A32 instructions, known as Arm instructions in pre-Armv8 architectures, are 32 bits wide, and are aligned on 4-byte boundaries. A32 instructions are supported by both A-profile and R-profile architectures. A32 was traditionally used in applications requiring the highest performance, or for handling hardware exceptions such as interrupts and processor start-up. Much of its functionality was subsumed into T32 with the introduction of Thumb-2 technology. |
|
From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php Thumb-2 technology is the instruction set underlying the ARM Cortex architecture which provides enhanced levels of performance, energy efficiency, and code density for a wide range of embedded applications. Thumb-2 technology builds on the success of Thumb, the innovative high code density instruction set for ARM microprocessor cores, to increase the power of the ARM microprocessor core available to developers of low cost, high performance systems. The technology is backwards compatible with existing ARM and Thumb solutions, while significantly extending the features available to the Thumb instructions set. This allows more of the application to benefit from the best in class code density of Thumb. For performance optimized code Thumb-2 technology uses 31 percent less memory to reduce system cost, while providing up to 38 percent higher performance than existing high density code, which can be used to prolong battery-life or to enrich the product feature set. Thumb-2 technology is featured in the processor, and in all ARMv7 architecture-based processors. |
|
Enable driver for the ISL29035 light sensor. |
|
105 ms |
|
0.0256 ms |
|
0.41 ms |
|
6.5 ms |
|
1 |
|
16 |
|
4 |
|
8 |
|
16000 |
|
1000 |
|
4000 |
|
64000 |
|
Sensing mode for ambient light spectrum. |
|
Sensing mode for infrared spectrum. |
|
Priority of thread used to handle the timer and threshold triggers. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable ISO TP support for CAN |
|
As (sender transmit timeout) and Ar (receiver transmit timeout). ISO 15765-2: 1000ms |
|
Timeout for the reception of the next FC frame. ISO 15765-2: 1000ms |
|
This value defines the size of the memory pool where the buffers for sending are allocated from. |
|
Cr (receiver consecutive frame) timeout. ISO 15765-2: 1000ms |
|
This option enables buffered sending contexts. This makes send and forget possible. A memory slab is used to buffer the context. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Each data buffer will occupy ISOTP_RX_BUF_SIZE + smallish header (sizeof(struct net_buf)) amount of data. |
|
This value defines the size of a single block in the pool. The number of blocks is given by ISOTP_RX_BUF_COUNT. To be efficient use a multiple of CAN_DL - 1 (for classic can : 8 - 1 = 7). |
|
This buffer is used for first and single frames. It is extra because the buffer has to be ready for the first reception in isr context and therefor is allocated when binding. Each buffer will occupy CAN_DL - 1 byte + header (sizeof(struct net_buf)) amount of data. |
|
Each data buffer will occupy CONFIG_NET_BUF_DATA_SIZE + smallish header (sizeof(struct net_buf)) amount of data. If context buffers are used, use the same size here. |
|
This defines the size of the memory slab where the buffers are allocated from. |
|
Copy the outgoing data to a net buffer so that the calling function can discard the data. |
|
This value defines the maximum number of WAIT frames before the transmission is aborted. |
|
This value defines the priority level of the work queue thread that handles flow control, consecutive sending, receiving and callbacks. |
|
This value defines the stack size of the work queue thread that handles flow control, consecutive sending, receiving and callbacks. |
|
The more nesting allowed, the more room is required for IRQ stacks. |
|
This option specifies the size of the stack used by interrupt service routines (ISRs), and during kernel initialization. |
|
Number of bytes from the ISR stack to reserve for each nested IRQ level. Must be a multiple of 16 to main stack alignment. Note that CONFIG_ISR_SUBSTACK_SIZE * CONFIG_ISR_DEPTH must be equal to CONFIG_ISR_STACK_SIZE. |
|
This option indicates that Zephyr will act as a bootloader to execute a separate Zephyr image payload. |
|
Enable IWDG driver for STM32 line of MCUs |
|
Enable this setting to allow IWDG to be automatically started during device initialization. Note that once IWDG is started it must be reloaded before the counter reaches 0, otherwise the MCU will be reset. |
|
Set timeout value for IWDG in microseconds. The min timeout supported is 0.1ms, the max timeout is 26214.4ms. |
|
Build a minimal JSON parsing/encoding library. Used by sample applications such as the NATS client. |
|
Enable creation of JWT tokens |
|
Use ECDSA signature (ES-256) |
|
Use RSA signature (RS-256) |
|
This option specifies the divide value for the K22 bus clock from the system clock. |
|
This option specifies the divide value for the K22 processor core clock from the system clock. |
|
This option specifies the divide value for the K64 flash clock from the system clock. |
|
This option specifies the divide value for the K22 FlexBus clock from the system clock. |
|
This option specifies the divide value for the K64 bus clock from the system clock. |
|
This option specifies the divide value for the K64 processor core clock from the system clock. |
|
This option specifies the divide value for the K64 flash clock from the system clock. |
|
This option specifies the divide value for the K64 FlexBus clock from the system clock. |
|
This option specifies the divide value for the K8x bus clock from the system clock. |
|
This option specifies the divide value for the K8x processor core clock from the system clock. |
|
This option specifies the divide value for the K8x flash clock from the system clock. |
|
This option specifies the divide value for the K8x FlexBus clock from the system clock. |
|
This option sets the name of the generated kernel binary. |
|
Enable kernel debugging. Note that debugging the kernel internals can be very verbose. |
|
Code entry symbol, to be set at linking phase. |
|
Default minimal init priority for each init level. |
|
Device driver, that depends on common components, such as interrupt controller, but does not depend on other devices, uses this init priority. |
|
Kernel objects use this priority for initialization. This priority needs to be higher than minimal default initialization priority. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
This shell provides access to basic kernel data like version, uptime and other useful information. |
|
Include the 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the FTFx module. |
|
Configures the reset value of the FDPROT register for FlexNVM devices. For program flash only devices, this byte is reserved. |
|
Configures the reset value of the FEPROT register for FlexNVM devices. For program flash only devices, this byte is reserved. |
|
Configures the reset value of the FOPT register, which includes boot, NMI, and EzPort options. |
|
Configures the reset value of the FSEC register, which includes backdoor key access, mass erase, factory access, and flash security options. |
|
Kinetis flash configuration field offset |
|
Enable the code cache |
|
Size of kernel object text area. Used in linker script. |
|
Include Keyboard scan drivers in system config. |
|
Enable driver for the FT5336 capacitive touch panel controller. |
|
Sample period (ms) |
|
Keyboard scan device driver initialization priority. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable the Microchip XEC Kscan IO driver. |
|
Adjust the value to your keyboard columns. The maximum column size for the Microchip XEC family is 18 (from 0 to 17). |
|
Determines the time in msecs for debouncing a key press. |
|
Determines the time in msecs for debouncing a key release. |
|
Defines the poll period in msecs between between matrix scans. |
|
Adjust the value to your keyboard rows. The maximum column size for the Microchip XEC family is 8 (from 0 to 7). |
|
This option specifies the divide value for the KV5X bus clock from the system clock. |
|
This option specifies the divide value for the KV5X processor core clock from the system clock. |
|
This option specifies the divide value for the KV5X flash clock from the system clock. |
|
This option specifies the divide value for the KV5X FlexBus clock from the system clock. |
|
This option specifies the divide value for the KW2xD bus clock from the system clock. |
|
This option specifies the divide value for the KW2xD processor core clock from the system clock. |
|
This option specifies the divide value for the KW2xD flash clock from the system clock. |
|
The value depends on your debugging needs. This generates an encoded trace of events without going to debug logging to avoid timing impact on running code. The buffer is post analyzed via the debugger. |
|
This hidden option allows multiple threads to use the floating point registers, using logic to lazily save/restore the floating point register state on context switch. On Intel Core processors, may be vulnerable to exploits which allows malware to read the contents of all floating point registers, see CVE-2018-3665. |
|
Include LED drivers in the system configuration. |
|
System initialization priority for LED drivers. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Include LED strip drivers in the system configuration. |
|
System initialization priority for LED strip drivers. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable the Gecko leuart driver. |
|
This option enables the libmetal HAL abstraction layer |
|
This option specifies the path to the source for the libmetal library |
|
Link with STD C++ Library. |
|
Linker exits with error when an orphan section is found. |
|
Linker puts orphan sections in place without warnings or errors. |
|
Linker places the orphan sections in output and issues warning about those sections. |
|
This turns on the linker flag to sort sections by alignment in decreasing size of symbols. This helps to minimize padding between symbols. |
|
Enable SPI/I2C-based driver for LIS2DH, LIS3DH, LSM303DLHC, LIS2DH12, LSM303AGR triaxial accelerometer sensors. |
|
+/-16g |
|
+/-2g |
|
+/-4g |
|
+/-8g |
|
Set at runtime |
|
1Hz |
|
10Hz |
|
25Hz |
|
50Hz |
|
100Hz |
|
200Hz |
|
400Hz |
|
1.6KHz |
|
5KHz |
|
1.25KHz |
|
Set at runtime |
|
high resolution (12 bit) |
|
low power (8 bit) |
|
normal (10 bit) |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LIS2DS12 accelerometer sensor driver |
|
Enable/disable temperature |
|
Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are: 0: Full Scale selected at runtime 2: +/- 2g 4: +/- 4g 8: +/- 8g 16: +/- 16g |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 25Hz 3: 50Hz 4: 100Hz 5: 200Hz 6: 400Hz 7: 800Hz |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LIS2DW12 accelerometer sensor driver |
|
16G |
|
2G |
|
4G |
|
8G |
|
Set at runtime (Default 2G) |
|
int1 |
|
int2 |
|
100 Hz |
|
12.5 Hz |
|
1600 Hz |
|
1.6 Hz |
|
200 Hz |
|
25 Hz |
|
400 Hz |
|
50 Hz |
|
800 Hz |
|
Set at runtime (Default 100 Hz) |
|
single |
|
Specify the sensor power mode 0: Low Power M1 1: Low Power M2 2: Low Power M3 3: Low Power M4 4: High Performance |
|
Enable pulse (single/double tap) detection |
|
When double-tap recognition is enabled, this register expresses the maximum time between two successive detected taps to determine a double-tap event. Where 0 equals 16*1/ODR and 1LSB = 32*1/ODR. |
|
Expected quiet time after a tap detection: this register represents the time after the first detected tap in which there must not be any overthreshold event. Where 0 equals 2*1/ODR and 1LSB = 4*1/ODR. |
|
Maximum duration of over-threshold event: this register represents the maximum time of an over-threshold signal detection to be recognized as a tap event. Where 0 equals 4*1/ODR and 1LSB = 8*1/ODR. |
|
Threshold to start the pulse-event detection procedure on the X-axis. Threshold values for each axis are unsigned 5-bit corresponding to an 2g acceleration full-scale range. |
|
Threshold to start the pulse-event detection procedure on the Y-axis. Threshold values for each axis are unsigned 5-bit corresponding to an 2g acceleration full-scale range. |
|
Threshold to start the pulse-event detection procedure on the Z-axis. Threshold values for each axis are unsigned 5-bit corresponding to an 2g acceleration full-scale range. |
|
Enable X axis for pulse |
|
Enable Y axis for pulse |
|
Enable Z axis for pulse |
|
single/double |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LIS2MDL I2C-based magnetometer sensor. |
|
Set magnetometer sampling frequency (ODR) at runtime (default: 10 Hz) |
|
Enable SPI 4wire mode (separated MISO and MOSI lines) |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LIS3MDL I2C-based magnetometer. |
|
Magnetometer full-scale range. An X value for the config represents a range of +/- X gauss. Valid values are 4, 8, 12 and 16. |
|
Magnetometer output data rate expressed in samples per second. Data rates supported by the chip are 0.625, 1.25, 2.5, 5, 10, 20, 40, 80, 155, 300, 560 and 1000. |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
This module implements a kernel device driver for LiteX Timer. |
|
This option enables link local multicast name resolution client side support. See RFC 4795 for details. LLMNR is typically used by Windows hosts. If you enable this option, then the DNS requests are ONLY sent to LLMNR well known multicast address 224.0.0.252:5355 or [ff02::1:3]:5355 and other DNS server addresses are ignored. |
|
Number of additional buffers available for the LLMNR responder. |
|
This option enables the LLMNR responder support for Zephyr. It will listen well-known address ff02::1:3 and 224.0.0.252. Currently this only returns IP address information. You must set CONFIG_NET_HOSTNAME to some meaningful value and then LLMNR will start to respond to <hostname> LLMNR queries. Note that LLMNR queries should only contain single-label names so there should be NO dot (“.”) in the name (RFC 4795 ch 3). Current implementation does not support TCP. See RFC 4795 for more details about LLMNR. |
|
Note that if NET_CONFIG_AUTO_INIT is enabled, then this value should be bigger than its value. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
DNS answers will use the TTL (in seconds). A default value is 30 seconds as recommended by RFC 4795 chapter 2.8 |
|
This option selects local APIC as the interrupt controller. |
|
This option specifies the base address of the Local APIC device. |
|
A special situation may occur when a processor raises its task priority to be greater than or equal to the level of the interrupt for which the processor INTR signal is currently being asserted. If at the time the INTA cycle is issued, the interrupt that was to be dispensed has become masked (programmed by software), the local APIC will deliver a spurious-interrupt vector. Dispensing the spurious-interrupt vector does not affect the ISR, so the handler for this vector should return without an EOI. From x86 manual Volume 3 Section 10.9. |
|
IDT vector to use for spurious LOAPIC interrupts. Note that some arches (P6, Pentium) ignore the low 4 bits and fix them at 0xF. If this value is left at -1 the last entry in the IDT will be used. |
|
This option selects LOAPIC timer as a system timer. |
|
This option specifies the IRQ used by the LOAPIC timer. |
|
This options specifies the IRQ priority used by the LOAPIC timer. |
|
Global switch for the logger, when turned off log calls will not be compiled in. |
|
Enable backend in APL ADSP using memory mailbox |
|
Address of the ring buffer in the memory. |
|
Size of the ring buffer. |
|
When enabled timestamp is formatted to hh:mm:ss:ms,us. |
|
Enable backend in native_posix |
|
Send syslog messages to network server. See RFC 5424 (syslog protocol) and RFC 5426 (syslog over UDP) specifications for details. |
|
Each syslog message should fit into a network packet that will be sent to server. This number tells how many syslog messages can be in transit to the server. |
|
As each syslog message needs to fit to UDP packet, set this value so that messages are not truncated. The RFC 5426 recommends that for IPv4 the size is 480 octets and for IPv6 the size is 1180 octets. As each buffer will use RAM, the value should be selected so that typical messages will fit the buffer. |
|
This can be either IPv4 or IPv6 address. Server listen UDP port number can be configured here too. Following syntax is supported: 192.0.2.1:514 192.0.2.42 [2001:db8::1]:514 [2001:db8::2] 2001:db::42 |
|
When enabled backend is using networking to output syst format logs. |
|
When enabled, backend will use RTT for logging. This backend works on a per message basis. Only a whole message (terminated with a carriage return: ‘r’) is transferred to up-buffer at once depending on available space and selected mode. In panic mode backend always blocks and waits until there is space in up-buffer for a message and message is transferred to host. |
|
Select index of up-buffer used for logger output, by default it uses terminal up-buffer and its settings. |
|
Specify reserved size of up-buffer used for logger output. |
|
This option defines maximum message size transferable to up-buffer. |
|
Waits until there is enough space in the up-buffer for a message. |
|
If there is not enough space in up-buffer for a message, drop it. Number of dropped messages will be logged. Increase up-buffer size helps to reduce dropping of messages. |
|
Buffer is used by log_output module for preparing output data (e.g. string formatting). |
|
Number of TX retries before dropping the data and assuming that RTT session is inactive. |
|
Sleep period between TX retry attempts. During RTT session, host pulls data periodically. Period starts from 1-2 milliseconds and can be increased if traffic on RTT increases (also from host to device). In case of heavy traffic data can be lost and it may be necessary to increase delay or number of retries. |
|
When enabled backend is using RTT to output syst format logs. |
|
When enabled selected backend prints errors in red and warning in yellow. |
|
When enabled, backend will use SWO for logging. |
|
Set SWO output frequency. Value 0 will select maximum frequency supported by the given MCU. Not all debug probes support high frequency SWO operation. In this case the frequency has to be set manually. SWO value defined by this option will be configured at boot. Most SWO viewer programs will configure SWO frequency when attached to the debug probe. Such configuration will persist only until the device reset. To ensure flawless operation the frequency configured here and by the SWO viewer program has to match. |
|
When enabled backend is using SWO to output syst format logs. |
|
When enabled backend is using UART to output logs. |
|
When enabled backend is using UART to output syst format logs. |
|
Buffer is used by log_output module for preparing output data (e.g. string formatting). |
|
Enable backend in xtensa simulator |
|
When enabled logger will block (if in the thread context) when internal logger buffer is full and new message cannot be allocated. |
|
If new buffer for a log message cannot be allocated in that time, log message is dropped. Forever blocking (-1) is possible however may lead to the logger deadlock if logging is enabled in threads used for logging (e.g. logger or shell thread). |
|
Number of bytes dedicated for the logger internal buffer. |
|
Enable shell commands |
|
Sets log level for modules which don’t specify it explicitly. When set to 0 it means log will not be activated for those modules. Levels are:
|
|
If enabled, logger will assert and log error message is it detects that string format specifier (%s) and string address which is not from read only memory section and not from pool used for string duplicates. String argument must be duplicated in that case using log_strdup(). Detection is performed during log processing thus it does not impact logging timing. |
|
In multicore system each application/core must have unique domain ID. |
|
Selecting this option will choose more robust _prf() function from minimal libc for handling format strings instead of the _vprintk() function. Choosing this option adds around ~3K flash and ~250 bytes on stack. |
|
When enabled, logs are redirected to a custom frontend instead of being processed by the logger. |
|
Debug messages prepended |
|
Error messages prepended |
|
Info messages prepended |
|
Warning messages prepended |
|
When enabled log is processed in the context of the call. It impacts performance of the system since time consuming operations are performed in the context of the log entry (e.g. high priority interrupt).Logger backends must support exclusive access to work flawlessly in that mode because one log operation can be interrupted by another one in the higher priority context. |
|
If enabled, interrupts are locked during whole log message processing. As a result, processing on one log message cannot be interrupted by another one and output is clean, not interleaved. However, enabling this option is causing interrupts locking for significant amount of time (up to multiple milliseconds). |
|
Forces a maximal log level for all modules. Modules saturates their specified level if it is greater than this option, otherwise they use the level specified by this option instead of their default or whatever was manually set. Levels are:
|
|
Enable minimal logging implementation. This has very little footprint overhead on top of the printk() implementation for standard logging macros. Hexdump macros are also supported, with a small amount of code pulled in if used. Build time filtering is supported, but not runtime filtering. There are no timestamps, prefixes, colors, or asynchronous logging, and all messages are simply sent to printk(). |
|
Enable mipi syst format output for the logger system. |
|
New logs are dropped |
|
Oldest logs are discarded |
|
Forces a minimum log level for all modules. Modules use their specified level if it is greater than this option, otherwise they use the level specified by this option instead of their default or whatever was manually set. Levels are:
|
|
LOG_PRINTK messages are formatted in place and logged unconditionally. |
|
Array is allocated on the stack. |
|
When enabled thread is created by the logger subsystem. Thread is waken up periodically (see LOG_PROCESS_THREAD_SLEEP_MS) and whenever number of buffered messages exceeds the threshold (see LOG_PROCESS_TRIGGER_THR). |
|
Log processing thread sleeps for requested period given in milliseconds. When waken up, thread process any buffered messages. |
|
Set the internal stack size for log processing thread. |
|
When number of buffered messages reaches the threshold thread is waken up. Log processing thread ID is provided during log initialization. Set 0 to disable the feature. If LOG_PROCESS_THREAD is enabled then this threshold is used by the internal thread. |
|
Allow runtime configuration of maximal, independent severity level for instance. |
|
Number of calls to log_strdup() which can be pending before flushed to output. If “<log_strdup alloc failed>” message is seen in the log output, it means this value is too small and should be increased. Each entry takes CONFIG_LOG_STRDUP_MAX_STRING bytes of memory plus some additional fixed overhead. |
|
Longer strings are truncated. |
|
When enabled, maximal utilization of the pool is tracked. It can be read out using shell command. |
|
Loopback Function bulk endpoint size |
|
Include LoRa drivers in the system configuration. |
|
System initialization priority for LoRa drivers. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable LoRa driver for Semtech SX1276. |
|
Enable LED driver for LP3943. LP3943 LED driver has 16 channels each with multi-programmable states at a specified rate. Each channel can drive up to 25 mA per LED. |
|
Enable LED driver for LP5562. LP5562 LED driver has 4 channels (RGBW). Each channel can drive up to 25.5 mA per LED. |
|
Enable LED strip driver for daisy chains of LPD880x (LPD8803, LPD8806, or compatible) devices. Each LPD880x LED driver chip has some output channels (3 channels for LPD8803, 6 for LPD8806), whose PWM duty cycle can be set at 7 bit resolution via a reduced SPI interface (MOSI and CLK lines only). Each chip also includes data and clock out pins for daisy chaining LED strips. |
|
Enable driver for LPS22HB I2C-based pressure and temperature sensor. |
|
Sensor output data rate expressed in samples per second. Data rates supported by the chip are 1, 10, 25, 50, 75. |
|
Enable driver for LPS22HH I2C-based pressure and temperature sensor. |
|
Sensor output data rate expressed in samples per second. Data rates supported by the chip are: 0: ODR selected at runtime 1: 1Hz 2: 10Hz 3: 25Hz 4: 50Hz 5: 75Hz 6: 100Hz 7: 200Hz |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LPS25HB I2C-based pressure and temperature sensor. |
|
Sensor output data rate expressed in samples per second. Data rates supported by the chip are 1, 7, 13, 25. |
|
Enable support for LPUART1 port in the driver. Say y here if you want to use LPUART1 device. |
|
Enable driver for LSM303DLHC I2C-based triaxial magnetometer sensor. |
|
0: 0.75Hz 1: 1.5 Hz 2: 3Hz 3: 7.5Hz 4: 15Hz 5: 30Hz 6: 75Hz 7: 220Hz |
|
1: +/-1.3 gauss 2: +/-1.9 gauss 3: +/-2.5 gauss 4: +/-4 gauss 5: +/-4.7 gauss 6: +/-5.6 gauss 7: +/-8.1 gauss |
|
Enable driver for LSM6DS0 I2C-based accelerometer and gyroscope sensor. |
|
Enable/disable accelerometer X axis totally by stripping everything related in driver. |
|
Enable/disable accelerometer Y axis totally by stripping everything related in driver. |
|
Enable/disable accelerometer Z axis totally by stripping everything related in driver. |
|
Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are 2, 4, 8 and 16. |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). Data rates supported by the chip are 0, 10, 50, 119, 238, 476, 952. |
|
Enable/disable temperature totally by stripping everything related in driver. |
|
Enable/disable gyroscope X axis totally by stripping everything related in driver. |
|
Enable/disable gyroscope Y axis totally by stripping everything related in driver. |
|
Enable/disable gyroscope Z axis totally by stripping everything related in driver. |
|
Specify the default gyroscope full-scale range. An X value for the config represents a range of +/- X degree per second. Valid values are 245, 500 and 2000. |
|
Specify the default gyroscope output data rate expressed in samples per second (Hz). Data rates supported by the chip are 0, 15, 60, 119, 238, 476, 952. |
|
Enable driver for LSM6DSL accelerometer and gyroscope sensor. |
|
Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are: 0: Full Scale selected at runtime 2: +/- 2g 4: +/- 4g 8: +/- 8g 16: +/- 16g |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz |
|
Enable/disable temperature |
|
LIS2MDL |
|
LPS22HB |
|
Specify the default gyroscope full-scale range. An X value for the config represents a range of +/- X degree per second. Valid values are: 0: Full Scale selected at runtime 125: +/- 125dps 245: +/- 245dps 500: +/- 500dps 1000: +/- 1000dps 2000: +/- 2000dps |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz |
|
Enable/disable internal sensorhub |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LSM6DSO accelerometer and gyroscope sensor. |
|
Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are: 0: Full Scale selected at runtime 2: +/- 2g 4: +/- 4g 8: +/- 8g 16: +/- 16g |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz |
|
Enable/disable temperature |
|
Enable HTS221 as external sensor |
|
Enable LIS2MDL as external sensor |
|
Enable LPS22HB as external sensor |
|
Enable LPS22HH as external sensor |
|
Specify the default gyroscope full-scale range. An X value for the config represents a range of +/- X degree per second. Valid values are: 0: Full Scale selected at runtime 125: +/- 125dps 250: +/- 250dps 500: +/- 500dps 1000: +/- 1000dps 2000: +/- 2000dps |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz |
|
int1 |
|
int2 |
|
Enable/disable internal sensorhub. You can enable a maximum of two external sensors (if more than two are enabled the system would enumerate only the first two found) |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LSM9DS0 I2C-based gyroscope sensor. |
|
2000 DPS |
|
245 DPS |
|
500 DPS |
|
Enable alteration of full-scale attribute at runtime. |
|
190 Hz |
|
380 Hz |
|
760 Hz |
|
95 Hz |
|
Enable alteration of sampling rate frequency at runtime. |
|
Specify the internal thread stack size. |
|
Enable triggers |
|
Enable data ready trigger |
|
Enable driver for LSM9DS0 I2C-based MFD sensor. |
|
Enable/disable accelerometer totally by stripping everything related in driver. |
|
Enable accelerometer X axis |
|
Enable accelerometer Y axis |
|
Enable accelerometer Z axis |
|
16G |
|
2G |
|
4G |
|
6G |
|
8G |
|
Enable alteration of accelerometer full-scale attribute at runtime. |
|
0 Hz (power down) |
|
100 Hz |
|
12.5 Hz |
|
1600 Hz |
|
200 Hz |
|
25 Hz |
|
3.125 Hz |
|
400 Hz |
|
50 Hz |
|
6.25 Hz |
|
800 Hz |
|
Enable alteration of accelerometer sampling rate attribute at runtime. |
|
Enable/disable magnetometer totally by stripping everything related in driver. |
|
12 Gauss |
|
2 Gauss |
|
4 Gauss |
|
8 Gauss |
|
Enable alteration of magnetometer full-scale attribute at runtime. |
|
100 Hz |
|
12.5 Hz |
|
25 Hz |
|
3.125 Hz |
|
50 Hz |
|
6.25 Hz |
|
Enable alteration of magnetometer sampling rate attribute at runtime. |
|
Enable/disable temperature sensor totally by stripping everything related in driver. |
|
This option enables the LittlevGL GUI library. |
|
Enable animations |
|
Enable anti-aliasing |
|
Number of bits per pixel. |
|
Rendering buffers are dynamically allocated based on the actual display parameters |
|
Rendering buffers are statically allocated based on the following configuration parameters: * Horizontal screen resolution * Vertical screen resolution * Rendering buffer size * Bytes per pixel |
|
Enable build-in font support, size 12 pixels |
|
Enable build-in font support with sub-pixel rendering, size 12 pixels |
|
Enable build-in font support, size 16 pixels |
|
Enable build-in font support, size 22 pixels |
|
Enable build-in font support, size 28 pixels |
|
Enable build-in compressed font support, size 28 pixels |
|
Enable build-in monospace font support, size 8 pixels |
|
Blue |
|
Custom |
|
Green |
|
Red |
|
Swap the 2 bytes of a RGB565 pixel. |
|
1-bit |
|
16-bit |
|
32-bit |
|
8-bit |
|
Enable screen transparency. Useful for OSD or other overlapping GUISs. |
|
Value of the color blue to be used in the chroma key |
|
Value of the color green to be used in the chroma key |
|
Value of the color red to be used in the chroma key |
|
Build-in font size 12 |
|
Build-in font size 12 with sub-pixel rendering |
|
Build-in font size 16 |
|
Build-in font size 22 |
|
Build-in font size 28 |
|
Build-in compressed font size 28 |
|
Build-in monospace font |
|
Use a none build-in font as default font. A pointer named lv_default_font_custom_ptr should exists as a global variable and point to a valid font structure |
|
Name of the display device to use for rendering. |
|
Use two buffers to render and flush data in parallel |
|
Dots per inch (DPI) |
|
Full flexibility |
|
Disabled |
|
Only horizontally and vertical |
|
Enable LittlevGL file system |
|
User BGR pixel format instead of RGB for sub-pixel rendering |
|
Enable GPU support |
|
Enable group support. Used by keyboard and button input |
|
Horizontal screen resolution in pixels |
|
Default image cache size, image caching keeps the images open. If only the built-in image formats are used there is no real advantage of caching. With complex image decoders (e.g. PNG or JPG) caching can save the continuous decoding of images. However the opened images might consume additional RAM. |
|
Enable support for alpha indexed images |
|
Enable support for indexed images |
|
Enable chroma keying for indexed images |
|
Threshold in pixels before entering drag mode |
|
Percentage of slow down of a throw following a drag. Greater percentage means faster slow-down. |
|
Period in milliseconds before a press is seen as a long press |
|
Period in milliseconds after which a new trigger is generated for a long press |
|
Refresh period for input devices in milliseconds |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Use k_malloc and k_free to allocate objects on the kernel heap |
|
Use C library malloc and free to allocate objects on the C library heap |
|
Use a dedicated memory pool in kernel space to allocate lvgl objects on |
|
Size of the largest block in the memory pool in bytes |
|
Size of the smallest block in the memory pool in bytes |
|
Number of maximum sized blocks in the memory pool. |
|
Use a dedicated memory pool in user space to allocate lvgl objects on |
|
Enable arc object support |
|
Enable bar object support |
|
Enable button object support |
|
Enable ink, press, effect for buttons |
|
Enable button matrix object support |
|
Enable calendar object support |
|
Enabled canvas object support |
|
Enable chart object support |
|
Maximum length of axis label |
|
Enable check box object support |
|
Enable color picker object support |
|
Enable container object support |
|
Enable drop down list object support |
|
Drop down list animation time in milliseconds |
|
Enable gauge object support |
|
Enable image object support |
|
Enable image button object support |
|
Enable tile support for image button |
|
Enable keyboard object support |
|
Enable label support |
|
Enable support for long text hints |
|
Scroll speed in pixels per second if scroll mode is enabled for a label |
|
Enable label text selection |
|
Waiting period at beginning/end of the label animation cycle |
|
Enable LED object support |
|
Enable line object support |
|
Enable line meter object support |
|
Enable list object support |
|
List focus animation time in milliseconds |
|
Enable message box object support |
|
Enable page object support |
|
Default page focus animation time in milliseconds |
|
Enabled pre-load object support |
|
Fill |
|
Spinning Arc |
|
Default arc length for pre-load in degrees |
|
Default spin time for pre-load in ms |
|
Enable object realign support |
|
Enable roller object support |
|
Roller animation time in milliseconds |
|
Number of extra pages in case the roller is infinite |
|
Enable slider object support |
|
Enable spinbox object support |
|
Enable switch object support |
|
Enable table object support |
|
Maximum number of columns to support in a table |
|
Enable tab view object support |
|
Tab view animation time in milliseconds |
|
Enable text area object support |
|
Text area cursor blink time in milliseconds |
|
Password character show time in milliseconds |
|
Enable tile view object support |
|
Tile view animation time in milliseconds |
|
Enable window object support |
|
Enable keyboard scan pointer input |
|
Name of the keyboard scan device to use for pointer input. |
|
Maximum number of items in the keyboard scan message queue. |
|
Screen refresh period in milliseconds |
|
Enable shadows |
|
Automatically detect direction |
|
Left-to-right |
|
Right-to-left |
|
Characters on which a text break can take place |
|
Control character to use for signalling text recoloring |
|
If a word is at least this long, a line break is allowed in the word. If the length is 0, no line break is allowed in the middle of a word. |
|
Minimal number of characters to place on a line after a line break occurred in the middle of a word. |
|
Minimal number of characters to place on a line before a line break in the middle of a word can occur. |
|
Enable bidirectional text support The direction of the text will be processed according to the Unicode Bidirectional Algorithm: https://www.w3.org/International/articles/inline-bidi-markup/uba-basics*/ |
|
Enable build-in themes |
|
Enable alien theme, dark futuristic, support |
|
Enable default theme support. Low RAM footprint theme. |
|
Enable runtime theme switching, this will consume 8 to 10kB of RAM. |
|
Enable material theme, flat theme with bold colors and light shadow, support |
|
Enable mono theme, monochrome, support |
|
Enable water-like theme based on the movie “Finding Nemo” |
|
Enable night theme, dark elegant, support |
|
Enable zen theme, peaceful light theme, support |
|
ASCII string encoding |
|
UTF-8 string encoding |
|
Enable memory allocation assertion Check if memory allocation is successful (Quite fast) |
|
Enable null pointer assertion Check if a null pointer is passed as a parameter (Quite fast) |
|
Enable object assertion Check if an object is not a NULL pointer, has the correct type and does exists. (Quite Slow) If this option is disabled and NULL pointer checking is enabled, the NULL pointer check is executed instead. |
|
Enable string assertion Check if the string is not a NULL pointer, unusually long string, contains invalid characters or contains unusual repetitions. (Slow) If this option is disabled and NULL pointer checking is enabled, the NULL pointer check is executed instead. |
|
Enable style assertion Check if a used style is correctly initialized. (Fast) |
|
Enable debug support. If debug support is enabled LVGL will validate the parameters of any function call made and if an invalid parameter is found __ASSERT is called. |
|
Size of the buffer used for rendering screen content as a percentage of total display size. |
|
Vertical screen resolution in pixels |
|
This option adds logic for managing OMA LWM2M data |
|
CoAP block size used by LWM2M when performing block-wise transfers. Possible values: 16, 32, 64, 128, 256, 512 and 1024. |
|
This value sets the maximum number of APN resource instances. These are displayed via the “Connection Monitoring” object /4/0/7. |
|
This value sets the maximum number of available network bearer resource instances. These are displayed via the “Connection Monitoring” object /4/0/1. |
|
Include support for LWM2M Connectivity Monitoring Object (ID 4) |
|
This value sets the maximum number of error codes that the device object will store before ignoring new values. |
|
This value sets the maximum number of power source data that a device can store. These are displayed via the “Device” object /3/0/6, /3/0/7 and /3/0/8 resources. |
|
Enable DNS support in the LWM2M client |
|
Enable DTLS support in the LwM2M client |
|
Set the default lifetime (in seconds) for the LWM2M library engine |
|
Set the maximum message objects for the LWM2M library client |
|
This value sets the maximum number of resources which can be added to the observe notification list. |
|
Set the maximum pending objects for the LWM2M library client |
|
Set the maximum reply objects for the LWM2M library client |
|
Extra room allocated to handle CoAP header data |
|
Set the stack size for the LWM2M library engine (used for handling OBSERVE and NOTIFY events) |
|
Include support for LWM2M Firmware Update Object (ID 5) |
|
Network address of the CoAP proxy server. |
|
Include support for pulling firmware file via a CoAP-CoAP/HTTP proxy. |
|
Include support for pulling a file from a remote server via block transfer and “FIRMWARE PACKAGE URI” resource. This option adds another UDP context and packet handling. |
|
This Object is used to used to represent a 1-3 axis accelerometer. |
|
This setting establishes the total count of IPSO Accelerometer instances available to the LWM2M client. |
|
Add a non-standard timestamp resource to each accelerometer object. |
|
This Object is used to actuate an audible alarm such as a buzzer, beeper, or vibration alarm. |
|
This setting establishes the total count of IPSO Buzzer instances available to the LWM2M client. |
|
This Object is used to control a light source, such as a LED or other light. It allows a light to be turned on or off and its dimmer setting to be controlled as a % between 0 and 100. An optional color setting enables a string to be used to indicate the desired color. |
|
This setting establishes the total count of IPSO Light Control instances available to the LWM2M client. |
|
This object is used with an On/Off switch to report it’s state. |
|
This setting establishes the total count of IPSO On/Off Switch instances available to the LWM2M client. |
|
Add a non-standard timestamp resource to each on/off switch object. |
|
This Object is used to report the state of a momentary action push button control and to count the number of times the control has been operated since the last observation. |
|
This setting establishes the total count of IPSO Push Button instances available to the LWM2M client. |
|
Add a non-standard timestamp resource to each Push Button object. |
|
This option adds general support for IPSO objects |
|
This IPSO object should be used with a temperature sensor to report a temperature measurement. It also provides resources for minimum/maximum measured values and the minimum/maximum range that can be measured by the temperature sensor. |
|
This setting establishes the total count of IPSO Temperature Sensor instances available to the LWM2M client. |
|
Add a non-standard timestamp resource to each temperature object. |
|
This Object is used to time events / actions |
|
This setting establishes the total count of IPSO Timer instances available to the LWM2M client. |
|
If you enable this option, various IPSO objects supported below will optionally include timestamp resources (ID 5518). This is an LWM2M protocol extension which can be useful to associate times with events. If unsure, leave at the default n. |
|
Include support for LWM2M Location Object (ID 6) |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
This value sets up the maximum number of LwM2M attributes that we can handle at the same time. |
|
This value sets up the maximum number of block1 contexts for CoAP block-wise transfer we can handle at the same time. |
|
This is the default server port to connect to for LWM2M communication |
|
Client will use registration state machine to locate and connect to LWM2M servers (including bootstrap server support) |
|
Enabling this setting allows the RD client to support bootstrap mode. |
|
Include support for writing JSON data |
|
This setting establishes the total count of LWM2M Security instances available to the client. |
|
This setting establishes the size of the key (pre-shared / public) resources in the security object instances. |
|
Default maximum amount of time in seconds the client may wait between notifications. When this time period expires a notification must be sent. |
|
Default minimum amount of time in seconds the client must wait between notifications. If a resource has to be notified during this minimum time period, the notification must be sent after the time period expires. |
|
This setting establishes the total count of LWM2M Server instances available to the client (including: bootstrap and regular servers). |
|
When the initialization is complete, the thread executing it then executes the main() routine, so as to reuse the stack used by the initialization, which would be wasted RAM otherwise. After initialization is complete, the thread runs main(). |
|
Priority at which the initialization thread runs, including the start of the main() function. main() can then change its priority if desired. |
|
Generates a file with build information that can be read by third party Makefile-based build systems. |
|
Mass storage device class bulk endpoints size |
|
Mass storage device disk or drive name |
|
MAX30101 Pulse Oximeter and Heart Rate Sensor |
|
Set the ADC’s full-scale range. 0 = 7.81 pA/LSB 1 = 15.63 pA/LSB 2 = 31.25 pA/LSB 3 = 62.5 pA/LSB |
|
Set the trigger for the FIFO_A_FULL interrupt |
|
Controls the behavior of the FIFO when the FIFO becomes completely filled with data. If set, the FIFO address rolls over to zero and the FIFO continues to fill with new data. If not set, then the FIFO is not updated until FIFO_DATA is read or the WRITE/READ pointer positions are changed. |
|
Set to operate in heart rate only mode. The red LED channel is active. |
|
Set the pulse amplitude to control the LED1 (red) current. The actual measured LED current for each part can vary significantly due to the trimming methodology. 0x00 = 0.0 mA 0x01 = 0.2 mA 0x02 = 0.4 mA 0x0f = 3.1 mA 0xff = 50.0 mA |
|
Set the pulse amplitude to control the LED2 (IR) current. The actual measured LED current for each part can vary significantly due to the trimming methodology. 0x00 = 0.0 mA 0x01 = 0.2 mA 0x02 = 0.4 mA 0x0f = 3.1 mA 0xff = 50.0 mA |
|
Set the pulse amplitude to control the LED3 (green) current. The actual measured LED current for each part can vary significantly due to the trimming methodology. 0x00 = 0.0 mA 0x01 = 0.2 mA 0x02 = 0.4 mA 0x0f = 3.1 mA 0xff = 50.0 mA |
|
Set to operate in multi-LED mode. The green, red, and/or IR LED channels are active. |
|
Set which LED and pulse amplitude are active in time slot 1. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA |
|
Set which LED and pulse amplitude are active in time slot 2. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA |
|
Set which LED and pulse amplitude are active in time slot 3. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA |
|
Set which LED and pulse amplitude are active in time slot 4. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA |
|
To reduce the amount of data throughput, adjacent samples (in each individual channel) can be averaged and decimated on the chip by setting this register. Set to 0 for no averaging. 0 = 1 sample (no averaging) 1 = 2 samples 2 = 4 samples 3 = 8 samples 4 = 16 samples 5 = 32 samples 6 = 32 samples 7 = 32 samples |
|
Set to operate in SpO2 mode. The red and IR LED channels are active. |
|
Set the effective sampling rate with one sample consisting of one pulse/conversion per active LED channel. In SpO2 mode, these means one IR pulse/conversion and one red pulse/conversion per sample period. 0 = 50 Hz 1 = 100 Hz 2 = 200 Hz 3 = 400 Hz 4 = 800 Hz 5 = 1000 Hz 6 = 1600 Hz 7 = 3200 Hz |
|
Enable driver for MAX44009 light sensors. |
|
Configure the maximum number of partitions per memory domain. |
|
This option specifies the number of IRQ lines in the system. It determines the size of the _irq_to_interrupt_vector_table, which is used to track the association between vectors and IRQ numbers. |
|
The maximum number of interrupt inputs to any aggregator in the system. |
|
Maximum number of simultaneously active threads in a POSIX application. |
|
Every kernel object will have an associated bitfield to store thread permissions for that object. This controls the size of the bitfield (in bytes) and imposes a limit on how many threads can be created in the system. |
|
Mention maximum number of timers in POSIX compliant application. |
|
This option specifies the maximum numbers of translation tables excluding the base translation table. Based on this, translation tables are allocated at compile time and used at runtime as needed. If the runtime need exceeds preallocated numbers of translation tables, it will result in assert. Number of translation tables required is decided based on how many discrete memory regions (both normal and device memory) are present on given platform and how much granularity is required while assigning attributes to these memory regions. |
|
This option enables the mbedTLS cryptography library. |
|
Use precomputed AES tables stored in ROM. |
|
Link with local mbedTLS sources instead of external library. |
|
Use a specific mbed TLS configuration file. The default config file file can be tweaked with Kconfig. The default configuration is suitable to communicate with majority of HTTPS servers on the Internet, but has relatively many features enabled. To optimize resources for special TLS usage, use available Kconfig options, or select an alternative config. |
|
Enable the ChaCha20-Poly1305 AEAD algorithm |
|
Enable the AES block cipher |
|
Enable all available ciphers |
|
Enable the ARC4 stream cipher |
|
Enable the Blowfish block cipher |
|
Enable the Camellia block cipher |
|
Enable Cipher Block Chaining mode (CBC) for symmetric ciphers |
|
Enable the Counter with CBC-MAC (CCM) mode for 128-bit block cipher |
|
Enable the ChaCha20 stream cipher |
|
Enable the DES block cipher |
|
Enable the Galois/Counter Mode (GCM) for AES |
|
Enable Xor-encrypt-xor with ciphertext stealing mode (XTS) for AES |
|
Enable the CTR_DRBG AES-256-based random generator |
|
Enable debugging activation for mbed TLS configuration. If you use mbedTLS/Zephyr integration (e.g. net_app), this will activate debug logging (of the level configured by MBEDTLS_DEBUG_LEVEL). If you use mbedTLS directly instead, you will need to perform additional configuration yourself: call mbedtls_ssl_conf_dbg(&mbedtls.conf, my_debug, NULL); mbedtls_debug_set_threshold(level); functions in your application, and create the my_debug() function to actually print something useful. |
|
Default mbed TLS debug logging level for Zephyr integration code (from ext/lib/crypto/mbedtls/include/mbedtls/debug.h): 0 No debug 1 Error 2 State change 3 Information 4 Verbose |
|
Enable support for DTLS |
|
Enable deterministic ECDSA (RFC 6979) |
|
Enable all available elliptic curves |
|
Enable BP256R1 elliptic curve |
|
Enable BP384R1 elliptic curve |
|
Enable BP512R1 elliptic curve |
|
Enable CURVE25519 elliptic curve |
|
Enable CURVE448 elliptic curve |
|
Enable SECP192K1 elliptic curve |
|
Enable SECP192R1 elliptic curve |
|
Enable SECP224K1 elliptic curve |
|
Enable SECP224R1 elliptic curve |
|
Enable SECP256K1 elliptic curve |
|
Enable SECP256R1 elliptic curve |
|
Enable SECP384R1 elliptic curve |
|
Enable SECP521R1 elliptic curve |
|
Enable NSIT curves optimization |
|
This option enables the mbedtls to use the heap. This setting must be global so that various applications and libraries in Zephyr do not try to do this themselves as there can be only one heap defined in mbedtls. If this is enabled, then the Zephyr will, during the device startup, initialize the heap automatically. |
|
Enable mbedTLS generic entropy pool |
|
Enable the prime-number generation code. |
|
Enable use of assembly code in mbedTLS. This improves the performances of asymmetric cryptography, however this might have an impact on the code size. |
|
The mbedtls routines will use this heap if enabled. See ext/lib/crypto/mbedtls/include/mbedtls/config.h and MBEDTLS_MEMORY_BUFFER_ALLOC_C option for details. That option is not enabled by default. Default value for the heap size is not set as it depends on the application. For streaming communication with arbitrary (HTTPS) servers on the Internet, 32KB + overheads (up to another 20KB) may be needed. For some dedicated and specific usage of mbedtls API, the 1000 bytes might be ok. |
|
Enable the HMAC_DRBG random generator |
|
This option holds the path where the mbedTLS libraries and headers are installed. Make sure this option is properly set when MBEDTLS_LIBRARY is enabled otherwise the build will fail. |
|
Enable all available ciphersuite modes |
|
Enable the DHE-PSK based ciphersuite modes |
|
Enable the DHE-RSA based ciphersuite modes |
|
Enable the ECDHE-ECDSA based ciphersuite modes |
|
Enable the ECDHE-PSK based ciphersuite modes |
|
Enable the ECDHE-RSA based ciphersuite modes |
|
Enable the ECDH-ECDSA based ciphersuite modes |
|
Enable the ECDH-RSA based ciphersuite modes |
|
Enable the ECJPAKE based ciphersuite modes |
|
Enable the PSK based ciphersuite modes |
|
Enable the RSA-only based ciphersuite modes |
|
Enable the RSA-PSK based ciphersuite modes |
|
This option enables mbedTLS library. |
|
Enable all available MAC methods |
|
Enable the CMAC (Cipher-based Message Authentication Code) mode for block ciphers. |
|
Enable the MD4 hash algorithm |
|
Enable the MD5 hash algorithm |
|
Enable the Poly1305 MAC algorithm |
|
Enable the SHA1 hash algorithm |
|
Enable the SHA-224 and SHA-256 hash algorithms |
|
Enable the SHA-384 and SHA-512 hash algorithms |
|
Enable some OpenThread specific mbedTLS optimizations that allows to save some RAM/ROM when OpenThread is used. Note, that when application aims to use other mbedTLS services on top of OpenThread (e.g. secure sockets), it’s advised to disable this option. |
|
By default only DER (binary) format of certificates is supported. Enable this option to enable support for PEM format. |
|
Enable an implementation of SHA-256 that has lower ROM footprint but also lower performance |
|
Enable support for exporting SSL key block and master secret |
|
The TLS standards mandate max payload size of 16384 bytes. So, for maximum operability and for general-purpose usage, that value must be used. For specific usages, that value can be largely decreased. E.g. for DTLS, payload size is limited by UDP datagram size, and even for HTTPS REST API, the payload can be limited to max size of (REST request, REST response, server certificate(s)). mbedTLS uses this value separate for input and output buffers, so twice this value will be allocated (on mbedTLS own heap, so the value of MBEDTLS_HEAP_SIZE should accommodate that). |
|
Enable self test function for the crypto algorithms |
|
Enable support for TLS 1.0 |
|
Enable support for TLS 1.1 (DTLS 1.0) |
|
Enable support for TLS 1.2 (DTLS 1.2) |
|
Enable user mbedTLS config file that will be included at the end of the generic config file. |
|
User config file that can contain mbedTLS configs that were not covered by the generic config file. |
|
Selects the amount to divide down the fast internal reference clock. The resulting frequency must be in the range 31.25 kHz to 4 MHz. |
|
Selects the amount to divide down the external reference clock for the FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. |
|
Selects the amount to divide down the external reference clock for the PLL. The resulting frequency must be in the range of 2 MHz to 4 MHz. |
|
Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits establish the multiplication factor (M) applied to the reference clock frequency. |
|
This module implements a kernel device driver for the Microchip XEC series RTOS timer and provides the standard “system clock driver” interfaces. |
|
Enable driver for MCP9808 temperature sensor. |
|
MCP9808 thread priority |
|
Sensor delayed work thread stack size |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
16 MHz |
|
1 MHz |
|
250 kHz |
|
32768 Hz |
|
32 MHz |
|
4 MHz |
|
62500 Hz |
|
8 MHz |
|
Disabled |
|
If this option is set, the driver does not perform a hardware reset and the CLK_OUT frequency is not set, instead these settings are performed during the initialization of the SoC. |
|
Enable support for managing DFU image downloaded using mcuboot. |
|
Enables usage swap type field which is required after “Fix double swap on interrupted revert” mcuboot patch (https://github.com/JuulLabs-OSS/mcuboot/pull/485) Disable this option if need to be compatible with earlier version of MCUBoot. |
|
This option enables the mcumgr management library. |
|
The number of net_bufs to allocate for mcumgr. These buffers are used for both requests and responses. |
|
The size, in bytes, of each mcumgr buffer. This value must satisfy the following relation: MCUMGR_BUF_SIZE >= transport-specific-MTU + transport-overhead |
|
The size, in bytes, of user data to allocate for each mcumgr buffer. Different mcumgr transports impose different requirements for this setting. A value of 4 is sufficient for UART, shell, and bluetooth. |
|
Enables mcumgr handlers for file management |
|
Enables mcumgr handlers for image management |
|
Enables mcumgr handlers for OS management |
|
Enables mcumgr handlers for statistics management. |
|
Enables handling of SMP commands received over Bluetooth. |
|
Enables encrypted and authenticated connection requirement to Bluetooth SMP transport. |
|
Enables handling of SMP commands received over shell. This allows the shell to be use for both mcumgr commands and shell commands. |
|
Maximum size of SMP frames sent and received over shell. This value must satisfy the following relation: MCUMGR_SMP_SHELL_MTU <= MCUMGR_BUF_SIZE + 2 |
|
Enables handling of SMP commands received over UART. This is a lightweight alternative to MCUMGR_SMP_SHELL. It allows mcumgr commands to be received over UART without requiring an additional thread. |
|
Maximum size of SMP frames sent and received over UART, in bytes. This value must satisfy the following relation: MCUMGR_SMP_UART_MTU <= MCUMGR_BUF_SIZE + 2 |
|
Rocktech rk043fn02h-ct |
|
Byte alignment in the frame buffer memory pool. |
|
Maximum block size in the frame buffer memory pool. |
|
Minimum block size in the frame buffer memory pool. |
|
Number of blocks in the frame buffer memory pool. |
|
This option enables multicast DNS client side support. See RFC 6762 for details. |
|
Number of additional buffers available for the mDNS responder. |
|
This option enables the mDNS responder support for Zephyr. It will listen well-known address ff02::fb and 224.0.0.251. Currently this only returns IP address information. You must set CONFIG_NET_HOSTNAME to some meaningful value and then mDNS will start to respond to <hostname>.local mDNS queries. See RFC 6762 for more details about mDNS. |
|
Note that if NET_CONFIG_AUTO_INIT is enabled, then this value should be bigger than its value. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
DNS answers will use the TTL (in seconds). |
|
This option is enabled when Memory Protection features are supported. Memory protection support is currently available on ARC, ARM, and x86 architectures. |
|
Enable this to be able to display images and text on the 5x5 LED matrix display on the BBC micro:bit. |
|
This value specifies the maximum length of strings that can be displayed using the mb_display_string() and mb_display_print() APIs. |
|
Build with minimal C library. |
|
Enable the minimal libc’s trivial implementation of calloc, which forwards to malloc and memset. |
|
Build with long long printf enabled. This will increase the size of the image. |
|
Enable the minimal libc’s implementation of malloc, free, and realloc. Disable if you wish to provide your own implementations of these functions. |
|
Indicate the size of the memory arena used for minimal libc’s malloc() implementation. This size value must be compatible with a sys_mem_pool definition with nmax of 1 and minsz of 16. |
|
Enable the minimal libc’s trivial implementation of reallocarray, which forwards to realloc. |
|
This option enables the MIPI SyS-T Library |
|
Causes the source code to build in “MISRA” mode, which disallows some otherwise-permitted features of the C standard for safety reasons. Specifically variable length arrays are not permitted (and gcc will enforce this). |
|
Enable config options for modem drivers. |
|
This generic command handler uses a modem interface to process incoming data and hand it back to the modem driver via callbacks defined for: - modem responses - unsolicited messages - specified handlers for current operation To configure this layer for use, create a modem_cmd_handler_data object and pass it’s reference to modem_cmd_handler_init() along with the modem_cmd_handler reference from your modem_context object. |
|
This option sets the maximum number of parameters which may be parsed by the command handler. This is also limited by the length of the match_buf (match_buf_len) field as it needs to be large enough to hold a single line of data (ending with /r). |
|
This driver allows modem drivers to communicate with an interface using custom defined protocols. Driver doesn’t inspect received data and all aspects of received protocol data are handled by application work method provided. This driver combines abstractions for: modem interface, command handler, pin config and socket handling each of which will need to be configured. |
|
Maximum number of modem contexts to handle. For most purposes this should stay at 1. |
|
Enabling this setting will turn on VERY heavy debugging from the modem context helper. Do NOT leave on for production. |
|
Specify Access Point Name, i.e. the name to identify Internet IP GPRS cellular data context. |
|
The GSM modem is initialized in POST_KERNEL using priority in the range 0-99. |
|
This setting is used in the AT+COPS command to set the MCC/MNO for the network connection context. This value is specific to the network provider and may need to be changed if auto is not selected. |
|
Enable GSM modems that support standard AT commands and PPP. |
|
UART device name the modem is connected to |
|
To configure this layer for use, create a modem_iface_uart_data object and pass it’s reference to modem_iface_uart_init() along with the modem_iface reference from your modem_context object and the UART device name. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
This driver allows modem drivers to communicate over UART with custom defined protocols. Driver doesn’t inspect received data and all aspects of received protocol data are handled by application via work method provided. This driver differs from the pipe UART driver in that callbacks are executed in a different work queue and data is passed around in k_pipe structures. |
|
Maximum number of modem receiver contexts to handle. For most purposes this should stay at 1. |
|
Activate shell module that provides modem utilities like sending a command to the modem UART. |
|
This layer provides much of the groundwork for keeping track of modem “sockets” throughout their lifecycle (from the initial offload API calls through the command handler call back layers). To configure this layer for use, create a modem_socket_config object with your socket data and pass it’s reference to modem_socket_init(). |
|
As the modem indicates more data is available to be received, these values are organized into “packets”. This setting limits the maximum number of packet sizes the socket can keep track of. |
|
Choose this setting to enable u-blox SARA-R4 LTE-CatM1/NB-IoT modem driver. |
|
Enable support for SARA-R4 modem |
|
This setting is used in the AT+CGDCONT command to set the APN name for the network connection context. This value is specific to the network provider and may need to be changed. |
|
u-blox SARA-R4 device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
|
This setting is used in the AT+COPS command to set the MCC/MNO for the network connection context. This value is specific to the network provider and may need to be changed if auto is not selected. |
|
Driver name |
|
Choose this setting to use a modem GPIO pin as network indication. |
|
This setting is used to configure one of the modem’s GPIO pins as a network status indication. See the manual for the gpio ids and how they map to pin numbers. |
|
This stack is used by the u-blox SARA-R4 RX thread. |
|
This stack is used by the work queue to pass off net_pkt data to the rest of the network stack, letting the rx thread continue processing data. |
|
Enable support for SARA-U2 modem |
|
Choose this setting to enable Wistron WNC-M14A2A LTE-M modem driver. NOTE: Currently the pin settings only work with FRDM K64F shield. |
|
This setting is used in the AT%PDNSET command to set the APN name for the network connection context. Normally, don’t need to change this value. |
|
WNC-M14A2A device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
|
This stack is used by the WNCM14A2A RX thread. |
|
This stack is used by the work queue to pass off net_pkt data to the rest of the network stack, letting the rx thread continue processing data. |
|
Enable driver for MPU6050 I2C-based six-axis motion tracking device. |
|
Magnetometer full-scale range. An X value for the config represents a range of +/- X g. Valid values are 2, 4, 8 and 16. |
|
Gyroscope full-scale range. An X value for the config represents a range of +/- X degrees/second. Valid values are 250, 500, 1000, 2000. |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable this config option if the AK8975 sensor is part of a MPU9150 chip. |
|
I2C address of the MPU9150. If the driver for MPU6050 is enabled, its address will be used and this option made unavailable. |
|
Enable this to allow MPU RWX access to flash memory |
|
This Kconfig option instructs the MPU driver to enforce a full kernel SRAM partitioning, when it programs the dynamic MPU regions (user thread stack, PRIV stack guard and application memory domains) during context-switch. We allow this to be a configurable option, in order to be able to switch the option off and have an increased number of MPU regions available for application memory domain programming. Notes: An increased number of MPU regions should only be required, when building with USERSPACE support. As a result, when we build without USERSPACE support, gap filling should always be required. When the option is switched off, access to memory areas not covered by explicit MPU regions is restricted to privileged code on an ARCH-specific basis. Refer to ARCH-specific documentation for more information on how this option is used. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
This option is enabled when the MPU requires the active (i.e. enabled) MPU regions to be non-overlapping with each other. |
|
This option is enabled when the MPU requires a power of two alignment and size for MPU regions. |
|
Enable thread stack guards via MPU. ARC supports built-in stack protection. If your core supports that, it is preferred over MPU stack guard |
|
Minimum size (and alignment when applicable) of an ARM MPU region, which guards the stack of a thread that is using the Floating Point (FP) context. The width of the guard is set to 128, to accommodate the length of a Cortex-M exception stack frame when the floating point context is active. The FP context is only stacked in sharing FP registers mode, therefore, the option is applicable only when FP_SHARING is selected. |
|
Number of multiprocessing-capable cores available to the multicpu API and SMP features. |
|
Keep alive time for MQTT (in seconds). Sending of Ping Requests to keep the connection alive are governed by this value. |
|
Enable the Zephyr MQTT Library |
|
Enable TLS support for socket MQTT Library |
|
Enable Websocket support for socket MQTT Library. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Mention length of message queue name in number of characters. |
|
Enable driver for MS5607 pressure and temperature sensor. |
|
x1024 |
|
x2048 |
|
x256 |
|
x4096 |
|
x512 |
|
x1024 |
|
x2048 |
|
x256 |
|
x4096 |
|
x512 |
|
Enable driver for MS5837 pressure and temperature sensor. |
|
Mention maximum number of messages in message queue in POSIX compliant application. |
|
Mention maximum size of message in bytes. |
|
Embed a multiboot header in the output executable. This is used by some boot loaders (e.g., GRUB) when loading Zephyr. It is safe to leave this option on if you’re not sure. It only expands the text segment by 12-16 bytes and is typically ignored if not needed. |
|
Multiboot framebuffer support |
|
Multiboot framebuffer X pixels |
|
Multiboot framebuffer Y pixels |
|
Multiboot passes a pointer to an information structure to the kernel entry point. Some drivers (e.g., the multiboot framebuffer display driver) need to refer to information in this structure, and so set this option to preserve the data in a permanent location. |
|
Use the multiboot memory map if the loader provides one. |
|
If disabled, only the main thread is available, so a main() function must be provided. Interrupts are available. Kernel objects will most probably not behave as expected, especially with regards to pending, since the main thread cannot pend, it being the only thread in the system. Many drivers and subsystems will not work with this option set to ‘n’; disable only when you REALLY know what you are doing. |
|
Multiple levels of interrupts are normally used to increase the number of addressable interrupts in a system. For example, if two levels are used, a second level interrupt aggregator would combine all interrupts routed to it into one IRQ line in the first level interrupt controller. If three levels are used, a third level aggregator combines its input interrupts into one IRQ line at the second level. The number of interrupt levels is usually determined by the hardware. (The term “aggregator” here means “interrupt controller”.) |
|
Build as a native application that can run on the host and using resources and libraries provided by the host. |
|
Use the host terminal (where the native_posix binary was launched) for the Zephyr console |
|
Device driver initialization priority. |
|
When selected the execution of the process will be slowed down to real time. (if there is a lot of load it may be slower than real time) If deselected, the process will run as fast as possible. Note that this only decouples simulated time from real/wall time. In either case the zephyr kernel and application cannot tell the difference unless they interact with some other driver/device which runs at real time. |
|
No current use. Kept only as there is plans to start using these drivers with the shell |
|
Zephyr’s printk messages will be directed to the host terminal stdout. |
|
This module implements a kernel device driver for the native_posix HW timer model |
|
In ms, polling period for stdin |
|
Connect this UART to its own pseudoterminal. This is the preferred option for users who want to use Zephyr’s shell. Moreover this option does not conflict with any other native_posix backend which may use the calling shell standard input/output. |
|
Connect this UART to the stdin & stdout of the calling shell/terminal which invoked the native_posix executable. This is good enough for automated testing, or when feeding from a file/pipe. Note that other, non UART messages, will also be printed to the terminal. This option should NOT be used in conjunction with NATIVE_POSIX_STDIN_CONSOLE It is strongly discouraged to try to use this option with the new shell interactively, as the default terminal configuration is NOT appropriate for interactive use. |
|
If the native_posix executable is called with the –attach_uart command line option, this will be the default command which will be run to attach a new terminal to the 1st UART. Note that this command must have one, and only one, ‘%s’ as placeholder for the pseudoterminal device name (e.g. /dev/pts/35) This is only applicable if the UART_0 is configured to use its own PTY with NATIVE_UART_0_ON_OWN_PTY. The 2nd UART will not be affected by this option. |
|
This option enables support for nested interrupts. |
|
This option enabled generic link layer and IP networking support. |
|
6lowpan compression and fragmentation. It is enabled by default if 802.15.4 is present, since using IPv6 on it requires it. |
|
Enables 6lowpan context based compression based on information received in RA(Router Advertisement) message. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Enable ARP support. This is necessary on hardware that requires it to get IPv4 working (like Ethernet devices). |
|
Gratuitous in this case means a ARP request or reply that is not normally needed according to the ARP specification but could be used in some cases. A gratuitous ARP request is a ARP request packet where the source and destination IP are both set to the IP of the machine issuing the packet and the destination MAC is the broadcast address ff:ff:ff:ff:ff:ff. Ordinarily, no reply packet will occur. A gratuitous ARP reply is a reply to which no request has been made. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Each entry in the ARP table consumes 22 bytes of memory. |
|
This option enables support for generic network protocol buffers. |
|
This value tell what is the size of the memory pool where each network buffer is allocated from. |
|
This value tells what is the fixed size of each network buffer. |
|
Each buffer comes with a built time configured size. If runtime requested is bigger than that, it will allocate as many net_buf as necessary to reach that request. |
|
Enable logs and checks for the generic network buffers. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable network buffer pool tracking. This means that: * amount of free buffers in the pool is remembered * total size of the pool is calculated * pool name is stored and can be shown in debugging prints |
|
Each data buffer will occupy CONFIG_NET_BUF_DATA_SIZE + smallish header (sizeof(struct net_buf)) amount of data. |
|
Enable extra debug logs and checks for the generic network buffers. |
|
Each data buffer will occupy CONFIG_NET_BUF_DATA_SIZE + smallish header (sizeof(struct net_buf)) amount of data. |
|
Amount of memory reserved in each network buffer for user data. In most cases this can be left as the default value. |
|
The buffer is dynamically allocated from runtime requested size. |
|
Interval in seconds of Network buffer allocation warnings which are generated when a buffer cannot immediately be allocated with K_FOREVER which may lead to deadlocks. Setting it to 0 makes warnings to be printed only once per allocation. |
|
If this option is set, then the networking system is automatically initialized when the device is started. If you do not wish to do this, then disable this and call net_config_init() in your application. |
|
Enables application to operate in node mode which requires GATT service to be registered and start advertising as peripheral. |
|
Perform an SNTP request over networking to get and absolute wall clock time, and initialize system time from it, so functions like time(), gettimeofday(), etc. returned the correct absolute time (no just time since system startup). Requires networking. |
|
The channel to use by default in the sample application. |
|
The device name to get bindings from in the sample application. |
|
The PAN ID to use by default in the sample. |
|
The TX power to use by default in the sample application. See NET_L2_IEEE802154_RADIO_DFLT_TX_POWER for more info. |
|
The key string to use for the link-layer security part. |
|
The key mode to use for the link-layer security part. Only implicit mode is supported, thus 0. |
|
The security level to use for the link-layer security part. 0 means no security 1 authentication only with a 4 bytes length tag 2 authentication only with a 8 bytes length tag 3 authentication only with a 16 bytes length tag 4 encryption only 5 encryption/authentication with a 4 bytes length tag 6 encryption/authentication with a 8 bytes length tag 7 encryption/authentication with a 16 bytes length tag |
|
Startup priority for the network application init |
|
The value is in seconds. If for example IPv4 address from DHCPv4 is not received within this limit, then the net_config_init() call will fail during the device startup. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Use 192.0.2.1 here if uncertain. |
|
Static gateway to use if not overridden by DHCP. Use empty value to skip setting static value. |
|
Static netmask to use if not overridden by DHCP. Use empty value to skip setting static value. |
|
Use 2001:db8::1 here if uncertain. |
|
The network application needs IPv4 support to function properly. This option makes sure the network application is initialized properly in order to use IPv4. |
|
The network application needs IPv6 support to function properly. This option makes sure the network application is initialized properly in order to use IPv6. |
|
The network application needs IPv6 router to exists before continuing. What this means that the application wants to wait until it receives IPv6 router advertisement message before continuing. |
|
This is only applicable in client side applications that try to establish a connection to peer host. Use 192.0.2.2 here if uncertain. |
|
This is only applicable in client side applications that try to establish a connection to peer host. Use 2001:db8::2 here if uncertain. |
|
Allow IP addresses to be set in config file for networking client/server sample applications, or some link-layer dedicated settings like the channel. Beware this is not meant to be used for proper provisioning but quick sampling/testing. |
|
Zephyr does not provide default setting for this option. Each application and vendor should choose a suitable setting based on their locality, needs, and server’s terms of service. See e.g. server information at https://support.ntp.org/bin/view/Servers/NTPPoolServers |
|
SNTP timeout to init system clock (ms) |
|
When enabled, this will start the connection manager that will listen to network interface and IP events in order to verify whether an interface is connected or not. It will then raise L4 events “connected” or “disconnected” depending on the result. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
This sets the starting priority of the connection manager thread. |
|
Sets the stack size which will be used by the connection manager thread. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
If you know that the options passed to net_context…() functions are ok, then you can disable the checks to save some memory. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
If enabled, then it is possible to fine-tune network packet pool for each context when sending network data. If this setting is enabled, then you should define the context pools in your application using NET_PKT_TX_POOL_DEFINE() and NET_PKT_DATA_POOL_DEFINE() macros and tie these pools to desired context using the net_context_setup_pools() function. |
|
It is possible to prioritize network traffic. This requires also traffic class support to work as expected. |
|
You can disable sync support to save some memory if you are calling net_context_recv() in async way only when timeout is set to 0. |
|
It is possible to timestamp outgoing packets and get information about these timestamps. |
|
It is possible to add information when the outgoing network packet should be sent. The TX time information should be placed into ancillary data field in sendmsg call. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Enable printing out in/out 802.15.4 packets. This is extremely verbose, do not enable this unless you know what you are doing. |
|
This will print-out both received and transmitted packets. |
|
This will print-out received packets only. |
|
This will print-out transmitted packets only. |
|
Add debug messages output on how much Net MGMT event stack is used. |
|
Enables printing of network packet and buffer allocations and frees for each allocation. This can produce lot of output so it is disabled by default. |
|
How many external net_pkt objects are there in user specific pools. This value is used when allocating space for tracking the memory allocations. |
|
This MUST not be used unless you have an hard to catch bug. This will reset the pkt cursor when it’s freed, so any subsequent r/w operations will not segfault, but just bail out and hopefully it will enable you to know who/where the packet was freed already. Do not set this, by any means, unless you are actively debugging. |
|
Bluetooth |
|
6LoCAN (IPv6 over CAN) interface |
|
Socket CAN interface |
|
Dummy testing interface |
|
Ethernet |
|
First available interface |
|
IEEE 802.15.4 |
|
Offloaded interface |
|
PPP interface |
|
Enable DHCPv4 client |
|
As per RFC2131 4.1.1, we wait a random period between 1 and 10 seconds before sending the initial discover. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Enable gPTP driver that send and receives gPTP packets and handles network packet timestamps. |
|
Defines the number of announce intervals to wait without receiving an Announce message before assuming that the master is no longer transmitting Announce messages. |
|
100ms |
|
100ns |
|
100us |
|
10ms |
|
10s |
|
10us |
|
1ms |
|
1s |
|
1us |
|
250ms |
|
250ns |
|
250us |
|
25ms |
|
25ns |
|
25us |
|
1.5ms |
|
2.5us |
|
> 10s |
|
Unknown |
|
Enable to mark the whole system as Grand Master Capable. |
|
Defines the interval at which an Announce message will be sent. The value is the converted in nanoseconds as follow: nanoseconds = (10^9) * 2^(value) |
|
Defines the interval at which a Path Delay Request will be sent. The value is the converted in nanoseconds as follow: nanoseconds = (10^9) * 2^(value) |
|
Defines the interval at which a Sync message will be sent. The value is the converted in nanoseconds as follow: nanoseconds = (10^9) * 2^(value) |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Defines the neighbor propagation delay threshold in nanoseconds. This is the propagation time threshold, above which a port is not considered capable of participating in the IEEE 802.1AS protocol. See IEEE 802.1AS chapter 11.2.12.6 for details. |
|
Configures the gPTP stack to work with the given number of ports. The port concept is the same thing as network interface. |
|
This tells the number of time-aware systems that transmits the Announce message. Each array element takes 8 bytes. If this value is set to 8, then 8 * 8 = 64 bytes of memory is used. |
|
This option is helpful if the driver does not fully support the ClockSourceTime.invoke function. If this is enabled, the clock source is probed when it is actually needed instead of being updated on each tick. See IEEE 802.1AS-2011, chapter 9.2 for more details. |
|
Enable this if you need to collect gPTP statistics. The statistics can be seen in net-shell if needed. |
|
Defines the number of sync intervals to wait without receiving synchronization information before assuming that the master is no longer transmitting synchronization information. |
|
Use a default internal function to update port local clock. |
|
This setting allows gPTP to run over VLAN link. Currently only one port can have VLAN tag set. Note that CONFIG_NET_GPTP_VLAN_TAG setting must have a proper tag value set, otherwise the gPTP over VLAN will not work. |
|
The VLAN tag to use when sending and receiving gPTP messages. The default value 4095 (0x0fff) means unspecified tag which is not a valid value. This means that you need to set the tag to a valid value. |
|
This a hidden option, which one should use with a lot of care. NO bug reports will be accepted if that option is enabled! You are warned. If you are 100% sure the headers memory space is always in a contiguous space, this will save stack usage and ROM in net core. This is a possible case when using IPv4 only, with NET_BUF_FIXED_DATA_SIZE enabled and NET_BUF_DATA_SIZE of 128 for instance. |
|
The string should be a valid hostname. |
|
This is used for example in mDNS to respond to <hostname>.local mDNS queries. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
This will append link address to hostname to create a unique hostname. For example, zephyr00005e005357 could be the hostname if this setting is enabled. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
If set, then respond to ICMPv4 echo-request that is sent to broadcast address. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Max number of IPv6 prefixes per network interface |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
This tells how many network interfaces there will be in the system that will have IPv4 enabled. |
|
This tells how many network interfaces there will be in the system that will have IPv6 enabled. |
|
Max number of multicast IPv4 addresses per network interface |
|
Max number of multicast IPv6 addresses per network interface |
|
Max number of unicast IPv4 addresses per network interface |
|
Max number of unicast IPv6 addresses per network interface |
|
Only enable this if you want a userspace application to manipulate network interface. Currently this is limited to add or remove IP addresses. By default this is not allowed. |
|
The value should be > 0 |
|
The value should be > 0 |
|
Network initialization priority level. This number tells how early in the boot the network stack is initialized. |
|
Enable IPv4 support. If this is enabled then the device is able to send and receive IPv4 network packets. |
|
If set, then accept UDP packets destined to non-standard 0.0.0.0 broadcast address as described in RFC 1122 ch. 3.3.6 |
|
Enables IPv4 auto IP address configuration (see RFC 3927) |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Enables IPv4 header options support. Current support for only ICMPv4 Echo request. Only RecordRoute and Timestamp are handled. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Enable IPv6 support. This should be selected by default as there is limited set of network bearers provided that support IPv4. |
|
The value depends on your network needs. DAD should normally be active. |
|
IPv6 fragmentation is disabled by default. This saves memory and should not cause issues normally as we support anyway the minimum length IPv6 packets (1280 bytes). If you enable fragmentation support, please increase amount of RX data buffers so that larger than 1280 byte packets can be received. |
|
How many fragmented IPv6 packets can be waiting reassembly simultaneously. Each fragment count might use up to 1280 bytes of memory so you need to plan this and increase the network buffer count. |
|
How long to wait for IPv6 fragment to arrive before the reassembly will timeout. RFC 2460 chapter 4.5 tells to wait for 60 seconds but this might be too long in memory constrained devices. This value is in seconds. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
The value depends on your network needs. |
|
The value depends on your network needs. MLD should normally be active. Currently we support only MLDv2. See RFC 3810 for details. |
|
The value depends on your network needs. Neighbor cache should normally be active. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
The value depends on your network needs. ND should normally be active. |
|
Support Router Advertisement Recursive DNS Server option. See RFC 6106 for details. The value depends on your network needs. |
|
Check that either the source or destination address is correct before sending either IPv4 or IPv6 network packet. |
|
Enable Bluetooth driver that send and receives IPv6 packets, does header compression on it and writes it to the Bluetooth stack via L2CAP channel. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Enable Bluetooth Network Management support |
|
Security level of Bluetooth Link: Level 1 (BT_SECURITY_LOW) = No encryption or authentication required Level 2 (BT_SECURITY_MEDIUM) = Only encryption required Level 3 (BT_SECURITY_HIGH) = Encryption and authentication required Level 4 (BT_SECURITY_FIPS) = Secure connection required |
|
This can be used for testing Bluetooth management commands through the console via a shell module named “net_bt”. |
|
This workaround is necessary to interoperate with Linux up to 4.10 but it might not be compliant with RFC 7668 as it cause the stack to skip Neighbor Discovery cache causing the destination link address to be omitted. For more details why this is needed see: https://github.com/zephyrproject-rtos/zephyr/issues/3111 |
|
Add a CANBUS L2 layer driver. This is the layer for IPv6 over CAN (6loCAN). It uses IPHC to compress the IP header and ISO-TP for flow control and reassembling. |
|
Number of CF (Contiguous Frame) PDUs before next FC (Flow Control) frame is sent. Zero value means all frames are sent consecutive without an additional FC frame. A BS counter at the sender counts from one to BS. When BS is reached, the sender waits for a FC frame again an BS is reset. See also: ISO 15765-2:2016 |
|
Number of retries for Duplicate Address Detection. Greater than one only makes sense for random link layer addresses. |
|
Enable a 6LoCAN Ethernet translator. With this translator it is possible to connect a 6LoCAN network to a Ethernet network directly, via a Switch or trough a router. Messages that goes through the translator have a special address and the MAC address is carried inline. The packet is forwarded with uncompressed IPv6 header. |
|
L2 address |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Add a CANBUS L2 layer driver. This is the layer for SOCKET CAN. |
|
Minimal separation time between frames in ms. The timer starts when the frame is queued and the next frame is transmitted after expiration. STmin is chosen by the receiver and transmitted in the FC (Flow Control) frame. See also: ISO 15765-2:2016 |
|
Use a fixed L2 address for 6LoCAN instead of a random chosen one. |
|
Add a dummy L2 layer driver. This is usually only needed when simulating a network interface when running network stack inside QEMU. |
|
Add support for Ethernet, enabling selecting relevant hardware drivers. If NET_SLIP_TAP is selected, NET_L2_ETHERNET will enable to fully simulate Ethernet through SLIP. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Enable support net_mgmt Ethernet interface which can be used to configure at run-time Ethernet drivers and L2 settings. |
|
Add support for low rate WPAN IEEE 802.15.4 technology. |
|
Enable inner stack’s logic on handling ACK request. Note that if the hw driver has an AUTOACK feature, this is then unnecessary. |
|
If IPv6 packets size more than 802.15.4 MTU, packet is fragmented and reassemble incoming packets according to RFC4944/6282. |
|
Simultaneously reassemble 802.15.4 fragments depending on cache size. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Use Aloha mechanism to transmit packets. This is a simplistic way of transmitting packets and fits contexts where radio spectrum is not too heavily loaded. |
|
Use CSMA-CA mechanism to transmit packets. This is the most common way of transmitting packets and fits most of all the usage. At least until the version 2011 of the specification. |
|
The maximum value of the backoff exponent (BE) in the CSMA-CA algorithm. |
|
The maximum number of backoffs the CSMA-CA algorithm will attempt before declaring a channel access failure. |
|
The minimum value of the backoff exponent (BE) in the CSMA-CA algorithm. |
|
TX power in dbm. Valid setting are: -18, -7, -4, -2, 0, 1, 2, 3, 5 If wrongly set, it will silently fail. |
|
Number of transmission attempts radio driver should do, before replying it could not send the packet. |
|
Reassembly timer will start as soon as first packet received from peer. Reassembly should be finished within a given time. Otherwise all accumulated fragments are dropped. |
|
This is the level for PAN device, not PAN coordinator. This will make possible to do active and/or passive scans, as well as associating and disassociating to/from a PAN. Current support is very fragile, thus it is not set as the default level. |
|
Enable 802.15.4 frame security handling, in order to bring data confidentiality and authenticity. |
|
This option should be used to set the crypto device name that IEEE 802.15.4 soft MAC will use to run authentication, encryption and decryption operations on incoming/outgoing frames. |
|
This can be used for testing 15.4 through the console via exposing a shell module named “ieee15_4”. |
|
Enable support for Sub-GHz devices. This will add a tiny bit more logic in L2 code for channel management. This option is automatically selected when relevant device driver is enabled. |
|
OpenThread L2 |
|
Add support for PPP. |
|
If the PPP starts too fast, it is possible to delay it a bit. This is mostly useful in debugging if you want the device be fully up before PPP handshake is started. Wait amount of milliseconds before starting PPP. Value 0 disables the wait. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
How many times to resend Configure-Req messages before deciding the link is not working properly. |
|
How many times to accept NACK loops. |
|
How many options we support. This is used to allocate space for each option. The default (8) is a reasonably small value. |
|
How many times to resend Terminate-Req messages before terminating the link. |
|
Enable support net_mgmt ppp interface which can be used to configure at run-time ppp drivers and L2 settings. |
|
Try to negotiate with peer for MRU (MTU) for the link. |
|
How long to wait Configure-Req. |
|
Add support for Wi-Fi Management interface. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
This can be used for controlling Wi-Fi through the console via exposing a shell module named “wifi”. |
|
Enable Link Layer Discovery Protocol (LLDP) Transmit support. Please refer to IEEE Std 802.1AB for more information. |
|
Chassis ID value |
|
Byte 0 of the MAC address. |
|
Byte 1 of the MAC address. |
|
Byte 2 of the MAC address. |
|
Byte 3 of the MAC address. |
|
Byte 4 of the MAC address. |
|
Byte 5 of the MAC address. |
|
Chassis ID subtype options are defined below. Please refer to section 8.5.2.2 of the 802.1AB for more info. Subtype 1 = Chassis component Subtype 2 = Interface alias Subtype 3 = Port component Subtype 4 = MAC address Subtype 5 = Network address Subtype 6 = Interface name Subtype 7 = Locally assigned If subtype 4 is selected, MAC address, then configs NET_LLDP_CHASSIS_ID_MAC0 through NET_LLDP_CHASSIS_ID_MAC5 must be defined, otherwise you must use NET_LLDP_CHASSIS_ID instead. |
|
Tells whether LLDPDU packet will have marker at the end of the packet. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Port ID value |
|
Byte 0 of the MAC address. |
|
Byte 1 of the MAC address. |
|
Byte 2 of the MAC address. |
|
Byte 3 of the MAC address. |
|
Byte 4 of the MAC address. |
|
Byte 5 of the MAC address. |
|
Port ID subtype options are defined below. Please refer to section 8.5.3.2 of the 802.1AB for more info. Subtype 1 = Interface alias Subtype 2 = Port component Subtype 3 = MAC address Subtype 4 = Network address Subtype 5 = Interface name Subtype 6 = Agent circuit ID Subtype 7 = Locally assigned If subtype 3 is selected (MAC address) then configs NET_LLDP_PORT_ID_MAC0 through NET_LLDP_PORT_ID_MAC5 must be defined, otherwise you must use NET_LLDP_PORT_ID instead. |
|
This value (msgTxHold) is used as a multiplier of CONFIG_NET_LLDP_TX_INTERVAL, to determine the value to be used as Time to Live in LLDP frames. For further information please refer to section 9.2.5.6 of the LLDP spec. |
|
Interval between transmissions of LLDPDUs during normal (non-fast mode) transmission periods. For further information please refer to section 9.2.5.7 of the LLDP spec. |
|
Enable logging in various parts of the network stack. Specific debugging options to other sub-menus will be unlocked as well (IPv6, IPv4, …). |
|
Net loopback driver |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
6lowpan context options table size. The value depends on your network and memory consumption. More 6CO options uses more memory. |
|
The value depends on your network needs. The value should include both UDP and TCP connections. |
|
Each network context is used to describe a network 5-tuple that is used when listening or sending network traffic. This is very similar as one could call a network socket in some other systems. |
|
This determines how many entries can be stored in multicast routing table. |
|
This determines how many entries can be stored in nexthop table. |
|
The value depends on your network needs. |
|
This determines how many entries can be stored in routing table. |
|
Add support for NM API that enables managing different aspects of the network stack as well as receiving notification on network events (ip address change, iface up and running …). |
|
This adds support for the stack to notify events towards any relevant listener. This can be necessary when application (or else) needs to be notified on a specific network event (ip address change for instance) to trigger some related work. |
|
Event notifier will be able to provide information to an event, and listeners will then be able to get it. Such information depends on the type of event. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Numbers of events which can be queued at same time. Note that if a 3rd event comes in, the first will be removed without generating any notification. Thus the size of this queue has to be tweaked depending on the load of the system, planned for the usage. |
|
Set the internal stack size for NM to run registered callbacks on events. |
|
Set the network management event core’s inner thread priority. Do not change this unless you know what you are doing. |
|
Enables Zephyr native IP stack. If you disable this, then you need to enable the offloading support if you want to have IP connectivity. |
|
Enables TCP/IP stack to be offload to a co-processor. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Enable network packet RX time statistics support. This is used to calculate how long on average it takes for a packet to travel from device driver to just before it is given to application. The RX timing information can then be seen in network interface statistics in net-shell. The RX statistics are only calculated for UDP and TCP packets. |
|
Each RX buffer will occupy smallish amount of memory. See include/net/net_pkt.h and the sizeof(struct net_pkt) |
|
Enable network packet timestamp support. This is needed for example in gPTP which needs to know how long it takes to send a network packet. |
|
Set the timestamp thread stack size in bytes. The timestamp thread waits for timestamped TX frames and calls registered callbacks. |
|
Create a TX timestamp thread that will pass the timestamped network packets to some other module like gPTP for further processing. If you just want to timestamp network packets and get information how long the network packets flow in the system, you can disable the thread support. |
|
Enable network packet TX time support. This is needed for when the application wants to set the exact time when the network packet should be sent. |
|
Enable network packet TX time statistics support. This is used to calculate how long on average it takes for a packet to travel from application to just before it is sent to network. The TX timing information can then be seen in network interface statistics in net-shell. The RX calculation is done only for UDP or TCP packets, but for TX we do not know the protocol so the TX packet timing is done for all network protocol packets. Note that CONFIG_NET_PKT_TXTIME cannot be set at the same time because net_pkt shares the time variable for statistics and TX time. |
|
Each TX buffer will occupy smallish amount of memory. See include/net/net_pkt.h and the sizeof(struct net_pkt) |
|
Point-to-point (PPP) UART based driver |
|
This option sets the driver name |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
This options sets the size of the UART pipe buffer where data is being read to. |
|
If you have a reliable link, then it might make sense to disable this as it takes some time to verify the received packet. |
|
Enable promiscuous mode support. This only works if the network device driver supports promiscuous mode. The user application also needs to read the promiscuous mode data. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Connect to host system via Qemu ethernet driver support. One such driver that Zephyr supports is Intel e1000 ethernet driver. |
|
Connect to host via PPP. |
|
Connect to host or to another Qemu via SLIP. |
|
This is a very specific option used to built only the very minimal part of the net stack in order to get network drivers working without any net stack above: core, L2 etc… Basically this will build only net_pkt part. It is currently used only by IEEE 802.15.4 drivers, though any type of net drivers could use it. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Allow IPv6 routing between different network interfaces and technologies. Currently this has limited use as some entity would need to populate the routing table. RPL used to do that earlier but currently there is no RPL support in Zephyr. |
|
What is the default network RX packet priority if user has not set one. The value 0 means lowest priority and 7 is the highest. |
|
Set the RX thread stack size in bytes. The RX thread is waiting data from network. There is one RX thread in the system. This value is a baseline and the actual RX stack size might be bigger depending on what features are enabled. |
|
Activate shell module that provides network commands like ping to the console. |
|
Enable various net-shell command to support dynamic command completion. This means that for example the nbr command can automatically complete the neighboring IPv6 address and user does not need to type it manually. Please note that this uses more memory in order to save the dynamic command strings. For example for nbr command the increase is 320 bytes (8 neighbors * 40 bytes for IPv6 address length) by default. Other dynamic completion commands in net-shell require also some smaller amount of memory. |
|
SLIP TAP support is necessary when testing with QEMU. The host needs to have tunslip6 with TAP support running in order to communicate via the SLIP driver. See net-tools project at https://github.com/zephyrproject-rtos/net-tools for more details. |
|
Provide BSD Sockets like API on top of native Zephyr networking API. |
|
The value depends on your network needs. |
|
The value tells how many sockets can receive data from same Socket-CAN interface. |
|
This variable specifies time in milliseconds after connect() API call will timeout if we have not received SYN-ACK from peer. |
|
This variable specifies time in milliseconds after which DNS query is considered timeout. Minimum timeout is 1 second and maximum timeout is 5 min. |
|
This variable specifies time in milliseconds after which DTLS connection is considered dead by TLS server and DTLS resources are freed. This is needed to prevent situation when DTLS client shuts down without closing connection gracefully, which can prevent other peers from connecting. Value of 0 indicates no timeout - resources will be freed only when connection is gracefully closed by peer sending TLS notification or socket is closed. |
|
Enable DTLS socket support. By default only TLS over TCP is supported. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Select this if you want to use socket API to get network managements events to your application. |
|
This sets the maximum number of net_mgmt sockets that can be set by the socket interface. So if you have two separate sockets that are used for listening events, you need to set this to two. |
|
Enables direct offloading of socket operations to dedicated TCP/IP hardware. This feature is intended to save resources by bypassing the Zephyr TCP/IP stack in the case where there is only one network interface required in the system, providing full BSD socket offload capability. As a result, it bypasses any potential IP routing that Zephyr might provide between multiple network interfaces. See NET_OFFLOAD for a more deeply integrated approach which offloads from the net_context() API within the Zephyr IP stack. |
|
This is an initial version of packet socket support (special type raw socket). Packets are passed to and from the device driver without any changes in the packet headers. It’s API caller responsibility to provide all the headers (e.g L2, L3 and so on) while sending. While receiving, packets (including all the headers) will be feed to sockets as it as from the driver. |
|
Maximum number of entries supported for poll() call. |
|
By default, Sockets API function are prefixed with |
|
Enable TLS socket option support which automatically establishes a TLS connection to the remote host. |
|
This variable sets maximum number of TLS/DTLS ciphersuites that can be used with specific socket, if set explicitly by socket option. By default, all ciphersuites that are available in the system are available to the socket. |
|
|
|
This variable sets maximum number of TLS/DTLS credentials that can be used with a specific socket. |
|
Manage statistics accounting. This takes memory so say ‘n’ if unsure. |
|
Keep track of Ethernet related statistics. Note that this requires support from the ethernet driver. The driver needs to collect the statistics. |
|
Allows Ethernet drivers to provide statistics information from vendor specific hardware registers in a form of key-value pairs. Deciphering the information may require vendor documentation. |
|
Keep track of ICMPv4/6 related statistics, depending whether IPv4 and/or IPv6 is/are enabled. |
|
Keep track of IPv4 related statistics |
|
Keep track of IPv6 related statistics |
|
Keep track of IPv6 Neighbor Discovery related statistics |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Keep track of MLD related statistics |
|
Print out all the statistics periodically through logging. This is meant for testing mostly. |
|
Collect statistics also for each network interface. |
|
Keep track of PPP related statistics |
|
Keep track of TCP related statistics |
|
Keep track of UDP related statistics |
|
Enable this if you need to grab relevant statistics in your code, via calling net_mgmt() with relevant NET_REQUEST_STATS_GET_* command. |
|
The value depends on your network needs. |
|
The current TCP stack that has been in use since Zephyr 1.0. |
|
Enable experimental TCP which is under development. |
|
This value affects the timeout when waiting ACK to arrive in various TCP states. The value is in milliseconds. Note that having a very low value here could prevent connectivity. |
|
Automatically accept incoming TCP data packet to the valid connection even if the application has not yet called accept(). This speeds up incoming data processing and is done like in Linux. Drawback is that we allocate data for the incoming packets even if the application has not yet accepted the connection. If the peer sends lot of packets, we might run out of memory in this case. |
|
The number of simultaneous TCP connection attempts, i.e. outstanding TCP connections waiting for initial ACK. |
|
Enables TCP handler to check TCP checksum. If the checksum is invalid, then the packet is discarded. |
|
This value affects the timeout between initial retransmission of TCP data packets. The value is in milliseconds. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
The following formula can be used to determine the time (in ms) that a segment will be be buffered awaiting retransmission: n=NET_TCP_RETRY_COUNT Sum((1<<n) * NET_TCP_INIT_RETRANSMISSION_TIMEOUT) n=0 With the default value of 9, the IP stack will try to retransmit for up to 1:42 minutes. This is as close as possible to the minimum value recommended by RFC1122 (1:40 minutes). Only 5 bits are dedicated for the retransmission count, so accepted values are in the 0-31 range. It’s highly recommended to not go below 9, though. Should a retransmission timeout occur, the receive callback is called with -ECONNRESET error code and the context is dereferenced. |
|
To avoid a (low-probability) issue when delayed packets from previous connection get delivered to next connection reusing the same local/remote ports, RFC 793 (TCP) suggests to keep an old, closed connection in a special “TIME_WAIT” state for the duration of 2*MSL (Maximum Segment Lifetime). The RFC suggests to use MSL of 2 minutes, but notes “This is an engineering choice, and may be changed if experience indicates it is desirable to do so.” For low-resource systems, having large MSL may lead to quick resource exhaustion (and related DoS attacks). At the same time, the issue of packet misdelivery is largely alleviated in the modern TCP stacks by using random, non-repeating port numbers and initial sequence numbers. Due to this, Zephyr uses much lower value of 250ms by default. Value of 0 disables TIME_WAIT state completely. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
This is the recommended priority to traffic class mapping for a system that supports SR (Stream Reservation) class A and SR class B. See 802.1Q, chapter 34.5 for more information. |
|
This is the recommended priority to traffic class mapping for a system that supports SR (Stream Reservation) class B only. See 802.1Q, chapter 34.5 for more information. |
|
This is the recommended default priority to traffic class mapping. Use it for implementations that do not support the credit-based shaper transmission selection algorithm. See 802.1Q, chapter 8.6.6 for more information. |
|
Define how many Rx traffic classes (queues) the system should have when receiving a network packet. The network packet priority can then be mapped to this traffic class so that higher prioritized packets can be processed before lower prioritized ones. Each queue is handled by a separate thread which will need RAM for stack space. Only increase the value from 1 if you really need this feature. The default value is 1 which means that all the network traffic is handled equally. In this implementation, the higher traffic class value corresponds to lower thread priority. |
|
Define how many Tx traffic classes (queues) the system should have when sending a network packet. The network packet priority can then be mapped to this traffic class so that higher prioritized packets can be processed before lower prioritized ones. Each queue is handled by a separate thread which will need RAM for stack space. Only increase the value from 1 if you really need this feature. The default value is 1 which means that all the network traffic is handled equally. In this implementation, the higher traffic class value corresponds to lower thread priority. |
|
Used for self-contained networking tests that do not require a network device. |
|
Enable JSON based test protocol (UDP). |
|
Normally this is enabled automatically if needed, so say ‘n’ if unsure. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
What is the default network packet priority if user has not specified one. The value 0 means lowest priority and 7 is the highest. |
|
Set the TX thread stack size in bytes. The TX thread is waiting data from application. Each network interface will start one TX thread for sending network packets destined to it. This value is a baseline and the actual TX stack size might be bigger depending on what features are enabled. |
|
The value depends on your network needs. |
|
Enables UDP handler to check UDP checksum. If the checksum is invalid, then the packet is discarded. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
RFC 768 states the possibility to have a missing checksum, for debugging purposes for instance. That feature is however valid only for IPv4 and on reception only, since Zephyr will always compute the UDP checksum in transmission path. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Enables virtual lan (VLAN) support for Ethernet. |
|
How many VLAN tags can be configured. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Enable support for Neural Network Accelerators |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Build with newlib library. The newlib library is expected to be part of the SDK in this case. |
|
If user mode is enabled, and MPU hardware has requirements that regions be sized to a power of two and aligned to their size, and user mode threads need to access this heap, then this is necessary to properly define an MPU region for the heap. If this is left at 0, then remaining system RAM will be used for this area and it may not be possible to program it as an MPU region. |
|
Build with floating point printf enabled. This will increase the size of the image. |
|
Build with floating point scanf enabled. This will increase the size of the image. |
|
Build with newlib-nano library, for small embedded apps. The newlib-nano library for ARM embedded processors is a part of the GNU Tools for ARM Embedded Processors. |
|
P0.9 and P0.10 are usually reserved for NFC. This option switch them to normal GPIO mode. HW enabling happens once in the device lifetime, during the first system startup. Disabling this option will not switch back these pins to NFCT mode. Doing this requires UICR erase prior to flashing device using the image which has this option disabled. |
|
Nios II Gen 2 architecture |
|
Add a “nocache” read-write memory section that is configured to not be cached. This memory section can be used to perform DMA transfers when cache coherence issues are not optimal or can not be solved using cache maintenance operations. |
|
Enable support for nrfx QSPI driver with EasyDMA. |
|
When CONFIG_FLASH_PAGE_LAYOUT is used this driver will support that API. By default the page size corresponds to the block size (65536). Other option include the sector size (4096). |
|
Device driver initialization priority. |
|
Quad Enable bit number in Status Register |
|
Compiler optimizations will be set to -O0 independently of other options. |
|
Do not do any runtime checks or asserts when using the CHECK macro. |
|
Selected if the architecture will generate a fault if unused stack memory is examined, which is the region between the current stack pointer and the deepest available address in the current stack region. |
|
Due to Anomaly 132 LF RC source may not start if restarted in certain window after stopping (230 us to 330 us). Software reset also stops the clock so if clock is initiated in certain window, the clock may also fail to start at reboot. A delay is added before starting LF clock to ensure that anomaly conditions are not met. Delay should be long enough to ensure that clock is started later than 330 us after reset. If crystal oscillator (XO) is used then low frequency clock initially starts with RC and then seamlessly switches to XO which has much longer startup time thus, depending on application, workaround may also need to be applied. Additional drivers initialization increases initialization time and delay may be shortened. Workaround is disabled by setting delay to 0. |
|
Enable ADC driver |
|
Enable CLOCK driver |
|
Enable COMP driver |
|
Enable DPPI allocator |
|
Enable EGU driver |
|
Enable EGU0 instance |
|
Enable EGU1 instance |
|
Enable EGU2 instance |
|
Enable EGU3 instance |
|
Enable EGU4 instance |
|
Enable EGU5 instance |
|
Enable GPIOTE driver |
|
Enable I2S driver |
|
Enable IPC driver |
|
Enable LPCOMP driver |
|
Enable NFCT driver |
|
Enable NVMC driver |
|
Enable PDM driver |
|
Enable POWER driver |
|
Enable PPI allocator |
|
Enable Peripheral Resource Sharing module |
|
Enable PRS box 0 |
|
Enable PRS box 1 |
|
Enable PRS box 2 |
|
Enable PRS box 3 |
|
Enable PRS box 4 |
|
Enable PWM driver |
|
Enable PWM0 instance |
|
Enable PWM1 instance |
|
Enable PWM2 instance |
|
Enable PWM3 instance |
|
Enable QDEC driver |
|
Enable QSPI driver |
|
Enable RNG driver |
|
Enable RTC driver |
|
Enable RTC0 instance |
|
Enable RTC1 instance |
|
Enable RTC2 instance |
|
Enable SAADC driver |
|
Enable SPI driver |
|
Enable SPI0 instance |
|
Enable SPI1 instance |
|
Enable SPI2 instance |
|
Enable SPIM driver |
|
Enable SPIM0 instance |
|
Enable SPIM1 instance |
|
Enable SPIM2 instance |
|
Enable SPIM3 instance |
|
Enable SPIM4 instance |
|
Enable SPIS driver |
|
Enable SPIS0 instance |
|
Enable SPIS1 instance |
|
Enable SPIS2 instance |
|
Enable SPIS3 instance |
|
Enable SYSTICK driver |
|
Enable TEMP driver |
|
Enable TIMER driver |
|
Enable TIMER0 instance |
|
Enable TIMER1 instance |
|
Enable TIMER2 instance |
|
Enable TIMER3 instance |
|
Enable TIMER4 instance |
|
Enable TWI driver |
|
Enable TWI0 instance |
|
Enable TWI1 instance |
|
Enable TWIM driver |
|
Enable TWIM0 instance |
|
Enable TWIM1 instance |
|
Enable TWIM2 instance |
|
Enable TWIM3 instance |
|
Enable TWIS driver |
|
Enable TWIS0 instance |
|
Enable TWIS1 instance |
|
Enable TWIS2 instance |
|
Enable TWIS3 instance |
|
Enable UART driver |
|
Enable UART0 instance |
|
Enable UARTE driver |
|
Enable UARTE0 instance |
|
Enable UARTE1 instance |
|
Enable UARTE2 instance |
|
Enable UARTE3 instance |
|
Enable USBD driver |
|
Enable USBREG driver |
|
Enable WDT driver |
|
Enable support for nrfx WDT instance 0. |
|
Enable support for nrfx WDT instance 1. |
|
Limit for occurrences above correlator threshold. When not equal to zero the correlator based signal detect is enabled. |
|
nRF IEEE 802.15.4 CCA Correlator threshold |
|
If energy detected in a given channel is above the value then the channel is deemed busy. The unit is defined as per 802.15.4-2006 spec. |
|
Carrier Seen |
|
Energy Above Threshold AND Carrier Seen |
|
Energy Above Threshold OR Carrier Seen |
|
Energy Above Threshold |
|
Enable nRF IEEE 802.15.4 radio driver |
|
Instruction and Data cache is available on nRF5340 CPUAPP (Application MCU). It may only be accessed by Secure code. Instruction cache only (I-Cache) is available in nRF5340 CPUNET (Network MCU). |
|
Enable the instruction cache (I-Cache) |
|
This module implements a kernel device driver for the nRF Real Time Counter NRF_RTC1 and provides the standard “system clock driver” interfaces. |
|
This module implements a kernel device driver for the nRF Timer Counter NRF_TIMER0 and provides the standard “system clock driver” interfaces. |
|
The number of level 2 interrupt aggregators to support. Each aggregator can manage at most MAX_IRQ_PER_AGGREGATOR level 2 interrupts. |
|
The number of level 3 interrupt aggregators to support. Each aggregator can manage at most MAX_IRQ_PER_AGGREGATOR level 3 interrupts. |
|
Number of cooperative priorities configured in the system. Gives access to priorities:
or seen another way, priorities:
This can be set to zero to disable cooperative scheduling. Cooperative threads always preempt preemptible threads. Each priority requires an extra 8 bytes of RAM. Each set of 32 extra total priorities require an extra 4 bytes and add one possible iteration to loops that search for the next thread to run. The total number of priorities is
The extra one is for the idle thread, which must run at the lowest priority, and be the only thread at that priority. |
|
Interrupts available will be 0 to NUM_IRQS-1. The minimum value is 17 as the first 16 entries in the vector table are for CPU exceptions. The BSP must provide a valid default. This drives the size of the vector table. |
|
Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1. The minimum value is 1. The BSP must provide a valid default for proper operation. |
|
This option specifies the total number of asynchronous mailbox messages that can exist simultaneously, across all mailboxes in the system. Setting this option to 0 disables support for asynchronous mailbox messages. |
|
This defines a set of priorities at the (numerically) lowest end of the range which have “meta-irq” behavior. Runnable threads at these priorities will always be scheduled before threads at lower priorities, EVEN IF those threads are otherwise cooperative and/or have taken a scheduler lock. Making such a thread runnable in any way thus has the effect of “interrupting” the current task and running the meta-irq thread synchronously, like an exception or system call. The intent is to use these priorities to implement “interrupt bottom half” or “tasklet” behavior, allowing driver subsystems to return from interrupt context but be guaranteed that user code will not be executed (on the current CPU) until the remaining work is finished. As this breaks the “promise” of non-preemptibility granted by the current API for cooperative threads, this tool probably shouldn’t be used from application code. |
|
This option specifies the total number of asynchronous pipe messages that can exist simultaneously, across all pipes in the system. Setting this option to 0 disables support for asynchronous pipe messages. |
|
Number of preemptible priorities available in the system. Gives access to priorities 0 to CONFIG_NUM_PREEMPT_PRIORITIES - 1. This can be set to 0 to disable preemptible scheduling. Each priority requires an extra 8 bytes of RAM. Each set of 32 extra total priorities require an extra 4 bytes and add one possible iteration to loops that search for the next thread to run. The total number of priorities is
The extra one is for the idle thread, which must run at the lowest priority, and be the only thread at that priority. |
|
Enable support of Non-volatile Storage. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable data structures required by the boot ROM to boot the application from an external flash device. |
|
This option enable the feature for tracing kernel objects. This option is for debug purposes and increases the memory footprint of the kernel. |
|
Offload requests workqueue priority |
|
Workqueue stack size for thread offload requests |
|
Choose Y for best performance. On some architectures (including x86) this will favor code size and performance over debugability. Choose N in you wish to retain the frame pointer. This option may be useful if your application uses runtime backtracing and does not support parsing unwind tables. If unsure, disable OVERRIDE_FRAME_POINTER_DEFAULT to allow the compiler to adopt sensible defaults for your architecture. |
|
This option enables the OpenAMP IPC library |
|
This option specifies the path to the source for the open-amp library |
|
This option exports an array of offsets to kernel structs, used by OpenOCD to determine the state of running threads. (This option selects CONFIG_THREAD_MONITOR, so all of its caveats are implied.) |
|
Default Channel |
|
Enable commissioner capability in OpenThread stack. Note, that DTLS handshake used in the commissioning procedure requires a larger mbedTLS heap than the default value. A minimum recommended value of CONFIG_MBEDTLS_HEAP_SIZE for the commissioning is 8KB. |
|
This option enables log support for OpenThread |
|
Enable DHCPv6 client capability in OpenThread stack |
|
Enable DHCPv6 server capability in OpenThread stack |
|
Enable OpenThread CLI diagnostic commands |
|
FTD - Full Thread Device |
|
Enable jam detection in OpenThread stack |
|
Enable joiner capability in OpenThread stack. Note, that DTLS handshake used in the commissioning procedure requires a larger mbedTLS heap than the default value. A minimum recommended value of CONFIG_MBEDTLS_HEAP_SIZE for the commissioning is 8KB. |
|
Enable automatic joiner start |
|
Pre Shared Key for the Device to start joiner |
|
This option enables log support for OpenThread |
|
This option enables dumping of 802.15.4 packets |
|
This option enables dumping of IPv6 packets |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Debug |
|
Error |
|
Info |
|
Warning |
|
MTD - Minimal Thread Device |
|
SED - Sleepy End Device |
|
Network name for OpenThread |
|
Default PAN ID |
|
List size for Ip6 packet buffering |
|
This option enables OpenThread platform |
|
Platform information for OpenThread |
|
Poll period for sleepy end devices [ms] |
|
Enable OpenThread shell |
|
OpenThread thread priority |
|
OpenThread thread stack size |
|
Extended PAN ID for OpenThread with format “de:ad:00:be:ef:00:ca:fe” |
|
Enable driver for OPT3001 light sensors. |
|
Set this option to use the oscillator in external reference clock mode. |
|
Set this option to use the oscillator in high-gain mode. |
|
Set this option to use the oscillator in low-power mode. |
|
Set the external oscillator frequency in Hz. This should be set by the board’s defconfig. |
|
Support for echo command |
|
When a reset command is received, the system waits this many milliseconds before performing the reset. This delay allows time for the mcumgr response to be delivered. |
|
Support for taskstat command |
|
This option sets flash pages count used by OpenThread to store its settings. They are located at the end of flash. |
|
Create an .lst file with the assembly listing of the firmware. |
|
If the toolchain supports it, this option will pass –print-memory-region to the linker when it is doing it’s first linker pass. Note that the memory regions are symbolic concepts defined by the linker scripts and do not necessarily map directly to the real physical address space. Take also note that some platforms do two passes of the linker so the results do not match exactly to the final elf file. See also rom_report, ram_report and https://sourceware.org/binutils/docs/ld/MEMORY.html |
|
Create a stat file using readelf -e <elf> |
|
Omitting the frame pointer prevents the compiler from putting the stack frame pointer into a register. Saves a few instructions in function prologues/epilogues and frees up a register for general-purpose use, which can provide good performance improvements on register-constrained architectures like x86. On some architectures (including x86) omitting frame pointers impedes debugging as local variables are harder to locate. At -O1 and above gcc will enable -fomit-frame-pointer automatically but only if the architecture does not require if for effective debugging. Choose Y if you want to override the default frame pointer behavior of your compiler, otherwise choose N. |
|
Antenna connected to PA_BOOST pin. |
|
Antenna connected to PA_RFO pin. |
|
Enable LED driver for PCA9633. PCA9633 LED driver has 4 channels each with multi-programmable states. Each channel can drive up to 25 mA per LED. |
|
This option enables support for new PCI(e) drivers. |
|
Use Message-Signaled Interrupts where possible. With this option enabled, PCI(e) devices which support MSI will be configured (at runtime) to use them. This is typically required for PCIe devices to generate interrupts at all. |
|
Enable commands for debugging PCI(e) using the built-in shell. |
|
This option disables all interrupts on the legacy i8259 PICs at boot. |
|
Enable board pinmux driver |
|
Enable driver for ARM V2M Beetle Pin multiplexer. |
|
Enable the TI SimpleLink CC13xx / CC26xx pinmux driver. |
|
Enable driver for ESP32 Pin multiplexer. |
|
Enable driver for ARC HSDK I/O pin mux. |
|
Pinmux driver initialization priority. Pinmux driver almost certainly should be initialized before the rest of hardware devices (which may need specific pins already configured for them), and usually after generic GPIO drivers. Thus, its priority should be between KERNEL_INIT_PRIORITY_DEFAULT and KERNEL_INIT_PRIORITY_DEVICE. There are exceptions to this rule for particular boards. Don’t change this value unless you know what you are doing. |
|
Enable driver for Intel S1000 I/O multiplexer. |
|
Enable the MCUX pinmux driver. |
|
Enable the MCUX LPC pinmux driver. |
|
Enable Port 0. |
|
Pinmux Port 0 driver name |
|
Enable Port 1. |
|
Pinmux Port 1 driver name |
|
Enable Port A. |
|
Pinmux Port A driver name |
|
Enable Port B. |
|
Pinmux Port B driver name |
|
Enable Port C. |
|
Pinmux Port C driver name |
|
Enable Port D. |
|
Pinmux Port D driver name |
|
Enable Port E. |
|
Pinmux Port E driver name |
|
The name of the pinmux driver. |
|
Enable the RV32M1 pinmux driver. |
|
Enable Port A. |
|
Pinmux Port A driver name |
|
Enable Port B. |
|
Pinmux Port B driver name |
|
Enable Port C. |
|
Pinmux Port C driver name |
|
Enable Port D. |
|
Pinmux Port D driver name |
|
Enable Port E. |
|
Pinmux Port E driver name |
|
Enable support for the Atmel SAM0 PORT pin multiplexer. |
|
Enable driver for the SiFive Freedom SOC pinmux driver |
|
SIFIVE pinmux 0 driver name |
|
Enable pin multiplexer for STM32 MCUs |
|
This option controls the priority of pinmux device initialization. Higher priority ensures that the device is initialized earlier in the startup cycle. Note that the pinmux device needs to be initialized after clock control device, but possibly before all other devices. If unsure, leave at default value 2 |
|
Enable the Microchip XEC pinmux driver. |
|
Enable Port 000-036 or what would be equivalent to Port A. |
|
Pinmux Port 000_036 driver name |
|
Enable Port 040-076 or what would be equivalent to Port B |
|
Pinmux Port 040_076 driver name |
|
Enable Port 100-136 or what would be equivalent to Port C |
|
Pinmux Port 100_136 driver name |
|
Enable Port 140-176 or what would be equivalent to Port C |
|
Pinmux Port 140_176 driver name |
|
Enable Port 200-236 or what would be equivalent to Port D |
|
Pinmux Port 200_236 driver name |
|
Enable Port 240-276 or what would be equivalent to Port E |
|
Pinmux Port 200_276 driver name |
|
The platform specific initialization code (z_platform_init) is executed at the beginning of the startup code (__start). |
|
Platform Level Interrupt Controller provides support for external interrupt lines defined by the RISC-V SoC; |
|
Enable driver for pms7003 particulate matter sensor. |
|
Driver name |
|
UART device |
|
Asynchronous notification framework. Enable the k_poll() and k_poll_signal_raise() APIs. The former can wait on multiple events concurrently, which can be either directly triggered or triggered by the availability of some kernel objects (semaphores and fifos). |
|
Enable mostly-standards-compliant implementations of various POSIX (IEEE 1003.1) APIs. |
|
This enables POSIX clock_*(), timer_*(), and *sleep() functions. |
|
This enables POSIX style file system related APIs. |
|
Maximum number of open file descriptors, this includes files, sockets, special devices, etc. |
|
Maximum number of open files. Note that this setting is additionally bounded by CONFIG_POSIX_MAX_FDS. |
|
This enabled POSIX message queue related APIs. |
|
This is only necessary if a ppp connection should be established with a Microsoft Windows PC. |
|
Specify a MAC address for the PPP interface in the form of six hex 8-bit chars separated by colons (e.g.: aa:33:cc:22:e2:c0). The default is an empty string, which means the code will make 00:00:5E:00:53:XX, where XX will be random. |
|
This option directs printk() debugging output to the supported console device, rather than suppressing the generation of printk() output entirely. Output is sent immediately, without any mutual exclusion or buffering. |
|
If userspace is enabled, printk() calls are buffered so that we do not have to make a system call for every character emitted. Specify the size of this buffer. |
|
Just the driver init priority |
|
Priority inheritance ceiling |
|
This option sets the privileged stack region size that will be used in addition to the user mode thread stack. During normal execution, this region will be inaccessible from user mode. During system calls, this region will be utilized by the system call. |
|
Stack text area size for privileged stacks. |
|
Include PS/2 drivers in system config. |
|
PS/2 device driver initialization priority. There isn’t any critical component relying on this priority at the moment. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable the Microchip XEC PS2 IO driver. The driver also depends on the KBC 8042 keyboard controller. |
|
Enable PS2 0. |
|
Enable PS2 1. |
|
This enables a mostly-standards-compliant implementation of the pthread mutex, condition variable and barrier IPC mechanisms. |
|
Enable options for Precision Time Protocol Clock drivers. |
|
Enable MCUX PTP clock support. |
|
Enable SAM GMAC PTP Clock support. |
|
Enable config options for PWM drivers. |
|
Enable PWM port 0 |
|
Enable PWM port 1 |
|
Enable PWM port 2 |
|
Enable PWM port 3 |
|
Enable PWM port 4 |
|
Enable driver to utilize PWM on the DesignWare Timer IP block. Care must be taken if one is also to use the timer feature, as they both use the same set of registers. |
|
Specify the device name for the DesignWare PWM driver. |
|
Enable support for i.MX pwm driver. |
|
This option enables the PWM LED driver for ESP32 family of processors. Say y if you wish to use PWM LED port on ESP32. |
|
Specify the device name for the PWM driver. |
|
Set high speed channels |
|
Enable channel 0 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 1 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 2 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 3 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 4 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 5 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 6 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 7 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Set high speed timers |
|
Set timer 0 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 1 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 2 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 3 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set low speed channels |
|
Enable channel 0 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 1 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 2 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 3 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 4 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 5 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 6 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 7 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Set low speed timers |
|
Set timer 0 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 1 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 2 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 3 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Enable support for LiteX PWM driver |
|
PWM device driver initialization priority. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable mcux pwm driver. |
|
Enable support for mcux ftm pwm driver. |
|
Enable driver to utilize PWM on the Nordic Semiconductor nRF5x series. This implementation provides up to 3 pins using one HF timer, two PPI channels per pin and one GPIOTE config per pin. |
|
Enable support for nrfx Hardware PWM driver for nRF52 MCU series. |
|
Enable driver for PCA9685 I2C-based PWM chip. |
|
Enable config options for the PCA9685 I2C-based PWM chip #0. |
|
Specify the device name for the PCA9685 I2C-based PWM chip #0. |
|
Specify the I2C slave address for the PCA9685 I2C-based PWM chip #0. |
|
Specify the device name of the I2C master device to which this PCA9685 chip #0 is binded. |
|
Device driver initialization priority. |
|
Loop count for PWM Software Reset when disabling PWM channel. |
|
Enable the RV32M1 TPM PWM driver. |
|
Enable PWM driver for Atmel SAM MCUs. |
|
Enable the PWM related shell commands. |
|
Enable the PWM driver for the SiFive Freedom platform |
|
SiFive PWM Driver Initialization Priority |
|
This option enables the PWM driver for STM32 family of processors. Say y if you wish to use PWM port on STM32 MCU. |
|
Enable output for PWM1 in the driver. Say y here if you want to use PWM1 output. |
|
Enable output for PWM10 in the driver. Say y here if you want to use PWM10 output. |
|
Enable output for PWM11 in the driver. Say y here if you want to use PWM11 output. |
|
Enable output for PWM12 in the driver. Say y here if you want to use PWM12 output. |
|
Enable output for PWM13 in the driver. Say y here if you want to use PWM13 output. |
|
Enable output for PWM14 in the driver. Say y here if you want to use PWM14 output. |
|
Enable output for PWM15 in the driver. Say y here if you want to use PWM15 output. |
|
Enable output for PWM16 in the driver. Say y here if you want to use PWM16 output. |
|
Enable output for PWM17 in the driver. Say y here if you want to use PWM17 output. |
|
Enable output for PWM18 in the driver. Say y here if you want to use PWM18 output. |
|
Enable output for PWM19 in the driver. Say y here if you want to use PWM19 output. |
|
Enable output for PWM2 in the driver. Say y here if you want to use PWM2 output. |
|
Enable output for PWM20 in the driver. Say y here if you want to use PWM20 output. |
|
Enable output for PWM3 in the driver. Say y here if you want to use PWM3 output. |
|
Enable output for PWM4 in the driver. Say y here if you want to use PWM4 output. |
|
Enable output for PWM5 in the driver. Say y here if you want to use PWM5 output. |
|
Enable output for PWM6 in the driver. Say y here if you want to use PWM6 output. |
|
Enable output for PWM7 in the driver. Say y here if you want to use PWM7 output. |
|
Enable output for PWM8 in the driver. Say y here if you want to use PWM8 output. |
|
Enable output for PWM9 in the driver. Say y here if you want to use PWM9 output. |
|
Enable driver to utilize PWM on the Microchip XEC IP block. |
|
Enable support for nrfx QDEC driver for nRF MCU series. |
|
Mark all QEMU targets with this variable for checking whether we are running in an emulated environment. |
|
Qemu (without -icount) has trouble keeping time when the host process needs to timeshare. The host OS will routinely schedule out a process at timescales equivalent to the guest tick rate. With traditional ticks delivered regularly by the hardware, that’s mostly OK as it looks like a late interrupt. But in tickless mode, the driver needs some CPU in order to schedule the tick in the first place. If that gets delayed across a tick boundary, time gets wonky. This tunable is a hint to the driver to disable tickless accounting on qemu. Use it only on tests that are known to have problems. |
|
Emit console messages to a RAM buffer “ram_console” which can be examined at runtime with a debugger. Useful in board bring-up if there aren’t any working serial drivers. |
|
Size of the RAM console buffer. Messages will wrap around if the length is exceeded. |
|
Enable the sys_reboot() API. Enabling this can drag in other subsystems needed to perform a “safe” reboot (e.g. SYSTEM_CLOCK_DISABLE, to stop the system clock before issuing a reset). |
|
Reboot via the RST_CNT register, going back to BIOS. |
|
Helper symbol to indicate some feature requires a C library implementation with more functionality than what MINIMAL_LIBC provides |
|
The ARC CPU can be configured to have more than one register bank. If fast interrupts are supported (FIRQ), the 2nd register bank, in the set, will be used by FIRQ interrupts. If fast interrupts are supported but there is only 1 register bank, the fast interrupt handler must save and restore general purpose registers. |
|
Enable usage of ring buffers. This is similar to kernel FIFOs but ring buffers manage their own buffer memory and can store arbitrary data. For optimal performance, use buffer sizes that are a power of 2. |
|
RISCV architecture |
|
Compile using generic riscv32 toolchain. Allow SOCs that have custom extended riscv ISA to still compile with generic riscv32 toolchain. |
|
Does SOC has CPU IDLE instruction |
|
Does the SOC provide support for a Platform Level Interrupt Controller |
|
This module implements a kernel device driver for the generic RISCV machine timer driver. It provides the standard “system clock driver” interfaces. |
|
Enable low-level SOC-specific context management, for SOCs with extra state that must be saved when entering an interrupt/exception, and restored on exit. If unsure, leave this at the default value. Enabling this option requires that the SoC provide a soc_context.h header which defines the following macros:
The generic architecture IRQ wrapper will also call __soc_save_context and __soc_restore_context routines at ISR entry and exit, respectively. These should typically be implemented in assembly. If they were C functions, they would have these signatures:
The calls obey standard calling conventions; i.e., the state pointer address is in a0, and ra contains the return address. |
|
Enable SOC-based interrupt initialization (call soc_interrupt_init, within _IntLibInit when enabled) |
|
Enabling this option requires that the SoC provide a soc_offsets.h header which defines the following macros:
|
|
RNDIS bulk endpoint size |
|
RNDIS interrupt endpoint size |
|
add the resource table in the generated binary. This table is compatible with linux remote proc framework and OpenAMP library. |
|
MEC1501 RTOS timer |
|
This option enables support of C++ RTTI. |
|
Emit console messages to a RAM buffer that is then read by the Segger J-Link software and displayed on a computer in real-time. Requires support for Segger J-Link on the companion IC onboard. |
|
Number of TX retries before dropping the byte and assuming that RTT session is inactive. |
|
Sleep period between TX retry attempts. During RTT session, host pulls data periodically. Period starts from 1-2 milliseconds and can be increased if traffic on RTT increases (also from host to device). In case of heavy traffic data can be lost and it may be necessary to increase delay or number of retries. |
|
If enabled RTT console will busy wait between TX retries when console assumes that RTT session is active. In case of heavy traffic data can be lost and it may be necessary to increase delay or number of retries. |
|
Always perform runtime checks covered with the CHECK macro. This option is the default and the only option used during testing. |
|
The kernel provides a simple NMI handler that simply hangs in a tight loop if triggered. This fills the requirement that there must be an NMI handler installed when the CPU boots. If a custom handler is needed, enable this option and attach it via _NmiHandlerSet(). |
|
Select this option to enable support for the RV32M1 INTMUX driver. This provides a level 2 interrupt controller for the SoC. The INTMUX peripheral combines level 2 interrupts into eight channels; each channel has its own level 1 interrupt to the core. |
|
Enable support for INTMUX channel 0. |
|
Enable support for INTMUX channel 1. |
|
Enable support for INTMUX channel 2. |
|
Enable support for INTMUX channel 3. |
|
Enable support for INTMUX channel 4. |
|
Enable support for INTMUX channel 5. |
|
Enable support for INTMUX channel 6. |
|
Enable support for INTMUX channel 7. |
|
Boot time initialization priority for INTMUX driver. Don’t change the default unless you know what you are doing. |
|
This module implements a kernel device driver for using the LPTMR peripheral as the system clock. It provides the standard “system clock driver” interfaces. |
|
Enable EIC driver for SAM0 series of devices. This is required for GPIO interrupt support. |
|
This module implements a kernel device driver for the Atmel SAM0 series Real Time Counter and provides the standard “system clock driver” interfaces. |
|
When true, the application will have access to the k_thread_cpu_mask_*() APIs which control per-CPU affinity masks in SMP mode, allowing applications to pin threads to specific CPUs or disallow threads from running on given CPUs. Note that as currently implemented, this involves an inherent O(N) scaling in the number of idle-but-runnable threads, and thus works only with the DUMB scheduler (as SCALABLE and MULTIQ would see no benefit). Note that this setting does not technically depend on SMP and is implemented without it for testing purposes, but for obvious reasons makes sense as an application API only where there is more than one CPU. With one CPU, it’s just a higher overhead version of k_thread_start/stop(). |
|
This enables a simple “earliest deadline first” scheduling mode where threads can set “deadline” deltas measured in k_cycle_get_32() units. Priority decisions within (!!) a single priority will choose the next expiring deadline and not simply the least recently added thread. |
|
When selected, the scheduler ready queue will be implemented as a simple unordered list, with very fast constant time performance for single threads and very low code size. Choose this on systems with constrained code size that will never see more than a small number (3, maybe) of runnable threads in the queue at any given time. On most platforms (that are not otherwise using the red/black tree) this results in a savings of ~2k of code size. |
|
True if the architecture supports a call to arch_sched_ipi() to broadcast an interrupt that will call z_sched_ipi() on other CPUs in the system. Required for k_thread_abort() to operate with reasonable latency (otherwise we might have to wait for the other thread to take an interrupt, which can be arbitrarily far in the future). |
|
IDT vector to use for scheduler IPI |
|
When selected, the scheduler ready queue will be implemented as the classic/textbook array of lists, one per priority (max 32 priorities). This corresponds to the scheduler algorithm used in Zephyr versions prior to 1.12. It incurs only a tiny code size overhead vs. the “dumb” scheduler and runs in O(1) time in almost all circumstances with very low constant factor. But it requires a fairly large RAM budget to store those list heads, and the limited features make it incompatible with features like deadline scheduling that need to sort threads more finely, and SMP affinity which need to traverse the list of threads. Typical applications with small numbers of runnable threads probably want the DUMB scheduler. |
|
When selected, the scheduler ready queue will be implemented as a red/black tree. This has rather slower constant-time insertion and removal overhead, and on most platforms (that are not otherwise using the rbtree somewhere) requires an extra ~2kb of code. But the resulting behavior will scale cleanly and quickly into the many thousands of threads. Use this on platforms where you may have many threads (very roughly: more than 20 or so) marked as runnable at a given time. Most applications don’t want this. |
|
Enable SDL based emulated display compliant with display driver API. |
|
ARGB 8888 |
|
BGR 565 |
|
Mono Black=0 |
|
Mono Black=1 |
|
RGB 565 |
|
RGB 888 |
|
SDL display device name |
|
X resolution for SDL display |
|
Y resolution for SDL display |
|
Size of the buffer for terminal input of target, from host |
|
Size of the buffer for terminal output of target, up to host |
|
Maximum number of down-buffers |
|
Maximum number of up-buffers |
|
Use a simple byte-loop instead of standard memcpy |
|
Block: Wait until there is space in the buffer. |
|
Skip. Do not block, output nothing. |
|
Trim: Do not block, output as much as fits. |
|
Size of buffer for RTT printf to bulk-send chars via RTT |
|
Segger SystemView support |
|
Start logging SystemView events on system start |
|
Buffer size for SystemView RTT |
|
Maximum semaphore count in POSIX compliant Application. |
|
Include sensor drivers in system config |
|
Sensor initialization priority. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
This shell provides access to basic sensor data. |
|
Enable options for serial drivers. |
|
This is an option to be enabled by individual serial driver to signal that there is a serial driver. This is being used by other drivers which are dependent on serial. |
|
This is an option to be enabled by individual serial driver to signal that the driver and hardware supports async operation. |
|
This is an option to be enabled by individual serial driver to signal that the driver and hardware supports interrupts. |
|
The settings subsystem allows its users to serialize and deserialize state in memory into and from non-volatile memory. It supports several back-ends to store and load serialized data from and it can do so atomically for all involved modules. |
|
Use a custom settings storage back-end. |
|
Enables the use of dynamic settings handlers |
|
Use FCB as a settings storage back-end. |
|
Magic 32-bit word for to identify valid settings area |
|
Number of areas to allocate in the settings FCB. A smaller number is used if the flash hardware cannot support this value. |
|
Use a file system as a settings storage back-end. |
|
Directory where the settings data is stored |
|
Full path to the default settings file. |
|
Limit how many items stored in a file before compressing |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
No storage back-end. |
|
Enables NVS storage support |
|
Number of sectors used for the NVS settings area |
|
The sector size to use for the NVS settings area as a multiple of FLASH_ERASE_BLOCK_SIZE. |
|
Enables runtime storage back-end. |
|
This option has been deprecated and will not be supported in future releases. Enables values encoding using Base64. |
|
This option sets up the GDT as part of the boot process. However, this may conflict with some security scenarios where the GDT is already appropriately set by an earlier bootloader stage, in which case this should be disabled. If disabled, the global _gdt pointer will not be available. |
|
Include shared interrupt support in system. Shared interrupt support is NOT required in most systems. If in doubt answer no. |
|
Provide an instance of the shared interrupt driver when system configuration requires that multiple devices share an interrupt. |
|
Provide an instance of the shared interrupt driver when system configuration requires that multiple devices share an interrupt. |
|
Shared IRQ are initialized on POST_KERNEL init level. They have to be initialized before any device that uses them. |
|
Configures the maximum number of clients allowed per shared instance of the shared interrupt driver. To conserve RAM set this value to the lowest practical value. |
|
Shell |
|
Maximum number of arguments that can build a command. If command is composed of more than defined, argument SHELL_ARGC_MAX and following are passed as one argument in the string. |
|
Enable shell backends. |
|
Enable dummy backend which can be used to execute commands with no need for physical transport interface. |
|
Enable RTT backend. |
|
Amount of messages that can enqueued in order to be processed by shell thread. Too small queue may lead to logger thread being blocked (see $(module)_LOG_MESSAGE_QUEUE_TIMEOUT). Too big queue on relatively slow shell transport may lead to situation where logs are dropped because all log messages are enqueued. |
|
If queue with pending log messages is full, oldest log message is dropped if queue is still full after requested time (-1 is forever). Logger thread is blocked for that period, thus long timeout impacts other logger backends and must be used with care. |
|
Enable serial backend. |
|
Interrupt driven |
|
Debug |
|
System limit (LOG_MAX_LEVEL) |
|
Error |
|
Info |
|
None |
|
Warning |
|
Amount of messages that can enqueued in order to be processed by shell thread. Too small queue may lead to logger thread being blocked (see $(module)_LOG_MESSAGE_QUEUE_TIMEOUT). Too big queue on relatively slow shell transport may lead to situation where logs are dropped because all log messages are enqueued. |
|
If queue with pending log messages is full, oldest log message is dropped if queue is still full after requested time (-1 is forever). Logger thread is blocked for that period, thus long timeout impacts other logger backends and must be used with care. |
|
Determines how often UART is polled for RX byte. |
|
RX ring buffer size impacts accepted latency of handling incoming bytes by shell. If shell input is coming from the keyboard then it is usually enough if ring buffer is few bytes (more than one due to escape sequences). However, if bulk data is transferred it may be required to increase it. |
|
If UART is utilizing DMA transfers then increasing ring buffer size increases transfers length and reduces number of interrupts. |
|
Enable TELNET backend. |
|
Terminals have different escape code settings for backspace button. Some terminals send code: 0x08 (backspace) other 0x7F (delete). When this option is set shell will expect 0x7F for backspace key. |
|
Enable built-in commands like ‘clear’, ‘history’, etc. |
|
By default shell assumes width of a terminal screen set to 80 characters. Each time terminal screen width is changed resize command must be called to ensure correct text display on the terminal screen. The resize command can be turned off to save code memory (~0,5k). |
|
This option enables select command. It can be used to set new root command. Exit to main command tree is with alt+r. |
|
Maximum command size in bytes. One byte is reserved for the string terminator character. |
|
If enabled shell prints back every input byte. |
|
Enables formatting help message when requested with ‘-h’ or ‘–help’. |
|
Enable printing help on wrong argument count |
|
Enable commands history. History can be accessed using up and down arrows. |
|
Number of bytes dedicated for storing executed commands. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enables shell meta keys: Ctrl+a, Ctrl+b, Ctrl+c, Ctrl+d, Ctrl+e, Ctrl+f, Ctrl+k, Ctrl+l, Ctrl+u, Ctrl+w, Alt+b, Alt+f Meta keys will not be active when shell echo is set to off. |
|
Maximum text buffer size for fprintf function. It is working like stdio buffering in Linux systems to limit number of peripheral access calls. |
|
Displayed prompt name for DUMMY backend. |
|
Displayed prompt name for RTT backend. |
|
Displayed prompt name for TELNET backend. |
|
Displayed prompt name for UART backend. |
|
Debug |
|
System limit (LOG_MAX_LEVEL) |
|
Error |
|
Info |
|
None |
|
Warning |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Determines how often RTT is polled for RX byte. |
|
Stack size for thread created for each instance. |
|
Enable shell statistics |
|
Debug |
|
System limit (LOG_MAX_LEVEL) |
|
Error |
|
Info |
|
None |
|
Warning |
|
This option can be used to modify the size of the buffer storing shell output line, prior to sending it through the network. Of course an output line can be longer than such size, it just means sending it will start as soon as it reaches this size. It really depends on what type of output is expected. A lot of short lines: better reduce this value. On the contrary, raise it. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Amount of messages that can enqueued in order to be processed by shell thread. Too small queue may lead to logger thread being blocked (see $(module)_LOG_MESSAGE_QUEUE_TIMEOUT). Too big queue on relatively slow shell transport may lead to situation where logs are dropped because all log messages are enqueued. |
|
If queue with pending log messages is full, oldest log message is dropped if queue is still full after requested time (-1 is forever). Logger thread is blocked for that period, thus long timeout impacts other logger backends and must be used with care. |
|
This option is used to configure on which port telnet is going to be bound. |
|
This option can be used to modify the duration of the timer that kick in when a line buffer is not empty but did not yet meet the line feed. |
|
Current support is so limited it’s not interesting to enable it. However, if proven to be needed at some point, it will be possible to extend such support. |
|
If enabled VT100 colors are used in shell (e.g. print errors in red). |
|
Enables using wildcards: * and ? in the shell. |
|
Enable driver for SHT3xD temperature and humidity sensors. |
|
0.5 |
|
1 |
|
10 |
|
2 |
|
4 |
|
periodic data acquisition |
|
high |
|
low |
|
medium |
|
single shot |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable I2C-based driver for Si7006 Temperature and Humidity Sensor. |
|
Enable driver for SI7060 temperature sensors. |
|
If enabled, SPI 0 is reserved for accessing the SPI flash ROM and a driver interface won’t be instantiated for SPI 0. Beware disabling this option on HiFive 1! The SPI flash ROM is where the program is stored, and if this driver initializes the interface for peripheral control the FE310 will crash on boot. |
|
Build the SimpleLink host driver |
|
Specify if the board configuration should be treated as a simulator. |
|
Compiler optimizations will be set to -Os independently of other options. |
|
The size of sjli (Secure Jump and Link Indexed) table. The code in normal mode call secure services in secure mode through sjli instruction. |
|
This is the address the slave core will boot from. Additionally this address is where we will copy the SLAVE_IMAGE to. We default this to the base of SRAM1 |
|
Driver for slave core startup |
|
This points to the image file for the the binary code that will be used by the slave core. |
|
SLIP driver |
|
This option sets the driver name |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Specify a MAC address for the SLIP interface in the form of six hex 8-bit chars separated by colons (e.g.: aa:33:cc:22:e2:c0). The default is an empty string, which means the code will make 00:00:5E:00:53:XX, where XX will be random. |
|
This option enables statistics support for SLIP driver. |
|
In TAP the Ethernet frames are transferred over SLIP. |
|
When true, kernel will be built with SMP support, allowing more than one CPU to schedule Zephyr tasks at a time. |
|
Enable SNTP client library |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
SoC name which can be found under soc/<arch>/<soc name>. This option holds the directory name used by the build system to locate the correct linker and header files for the SoC. |
|
Enable SOCKS5 proxy support |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Intel Apollo Lake Soc |
|
Synopsys ARC EM Software Development Platform |
|
Synopsys ARC HSDK SoC |
|
Synopsys ARC IoT SoC |
|
The main clock is being used to drive the PLL, and thus driving the processor clock. Says y if you want to use external crystal oscillator to drive the main clock. Note that this adds about a second to boot time, as the crystal needs to stabilize after power-up. The crystal used here can be from 3 to 20 MHz. Says n here will use the internal fast RC oscillator running at 12 MHz. |
|
Says y if you want to use external 32 kHz crystal oscillator to drive the slow clock. Note that this adds a few seconds to boot time, as the crystal needs to stabilize after power-up. Says n if you do not need accurate and precise timers. The slow clock will be driven by the internal fast RC oscillator running at 32 kHz. |
|
This is the divider (DIVA) used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. With default of MULA == 6, and DIVA == 1, PLL is running at 7 times of main clock. |
|
This is the multiplier (MULA) used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. With default of MULA == 6, and DIVA == 1, PLL is running at 7 times of main clock. |
|
For JTAG debugging CPU clock (HCLK) should not stop. In order to achieve this, make CPU go to Wait mode instead of Sleep mode while using external crystal oscillator for main clock. |
|
The main clock is being used to drive the PLL, and thus driving the processor clock. Says y if you want to use external crystal oscillator to drive the main clock. Note that this adds about a second to boot time, as the crystal needs to stabilize after power-up. The crystal used here can be from 3 to 20 MHz. Says n here will use the internal fast RC oscillator running at 12 MHz. |
|
Says y if you want to use external 32 kHz crystal oscillator to drive the slow clock. Note that this adds a few seconds to boot time, as the crystal needs to stabilize after power-up. Says n if you do not need accurate and precise timers. The slow clock will be driven by the internal fast RC oscillator running at 32 kHz. |
|
This is the divider (DIVA) used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. With default of MULA == 9, and DIVA == 1, PLL is running at 10 times of main clock. |
|
This is the multiplier (MULA) used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. With default of MULA == 9, and DIVA == 1, PLL is running at 10 times of main clock. |
|
For JTAG debugging CPU clock (HCLK) should not stop. In order to achieve this, make CPU go to Wait mode instead of Sleep mode while using external crystal oscillator for main clock. |
|
The main clock is being used to drive the PLL, and thus driving the processor clock. Says y if you want to use external crystal oscillator to drive the main clock. Note that this adds about a second to boot time, as the crystal needs to stabilize after power-up. The crystal used here can be from 3 to 20 MHz. Says n here will use the internal fast RC oscillator running at 12 MHz. |
|
Says y if you want to use external 32 kHz crystal oscillator to drive the slow clock. Note that this adds a few seconds to boot time, as the crystal needs to stabilize after power-up. Says n if you do not need accurate and precise timers. The slow clock will be driven by the internal fast RC oscillator running at 32 kHz. |
|
This is the divider (DIVA) used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. With default of MULA == 9, and DIVA == 1, PLL is running at 10 times of main clock. |
|
This is the multiplier (MULA) used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. With default of MULA == 9, and DIVA == 1, PLL is running at 10 times of main clock. |
|
For JTAG debugging CPU clock (HCLK) should not stop. In order to achieve this, make CPU go to Wait mode instead of Sleep mode while using external crystal oscillator for main clock. |
|
OSCULP32K |
|
Say y to enable the external 32 kHZ crystal oscillator at startup. This can then be selected as the main clock source for the SOC. |
|
XOSC32K |
|
OSC8M |
|
Say y to enable the external crystal oscillator at startup. |
|
Say y to enable the external 32 kHZ crystal oscillator at startup. This can then be selected as the main clock source for the SOC. |
|
XOSC32K |
|
XOSC |
|
At reset ERASE pin is configured in System IO mode. Asserting the ERASE pin at ‘1’ will completely erase Flash memory. Setting this option will switch the pin to general IO mode giving control of the pin to the GPIO module. |
|
The main clock is being used to drive the PLL, and thus driving the processor clock. Say y if you want to use external crystal oscillator to drive the main clock. Note that this adds about a second to boot time, as the crystal needs to stabilize after power-up. The crystal used here can be from 3 to 20 MHz. Says n here will use the internal fast RC oscillator running at 12 MHz. |
|
Say y if you want to use external 32 kHz crystal oscillator to drive the slow clock. Note that this adds a few seconds to boot time, as the crystal needs to stabilize after power-up. Says n if you do not need accurate and precise timers. The slow clock will be driven by the internal fast RC oscillator running at 32 kHz. |
|
This divisor defines a ratio between processor clock (HCLK) and master clock (MCK): MCK = HCLK / MDIV |
|
This is the divider DIVA used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. Setting DIVA=0 would disable PLL at boot, this is currently not supported. With default of MULA == 24, and DIVA == 1, PLL is running at 25 times the main clock frequency. |
|
This is the multiplier MULA used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. Setting MULA=0 would disable PLL at boot, this is currently not supported. With default of MULA == 24, and DIVA == 1, PLL is running at 25 times the main clock frequency. |
|
For JTAG debugging CPU clock (HCLK) should not stop. In order to achieve this, make CPU go to Wait mode instead of Sleep mode while using external crystal oscillator for main clock. |
|
At reset ERASE pin is configured in System IO mode. Asserting the ERASE pin at ‘1’ will completely erase Flash memory. Setting this option will switch the pin to general IO mode giving control of the pin to the GPIO module. |
|
The main clock is being used to drive the PLL, and thus driving the processor clock. Say y if you want to use external crystal oscillator to drive the main clock. Note that this adds about a second to boot time, as the crystal needs to stabilize after power-up. The crystal used here can be from 3 to 20 MHz. Says n here will use the internal fast RC oscillator running at 12 MHz. |
|
Say y if you want to use external 32 kHz crystal oscillator to drive the slow clock. Note that this adds a few seconds to boot time, as the crystal needs to stabilize after power-up. Says n if you do not need accurate and precise timers. The slow clock will be driven by the internal fast RC oscillator running at 32 kHz. |
|
This divisor defines a ratio between processor clock (HCLK) and master clock (MCK): MCK = HCLK / MDIV |
|
This is the divider DIVA used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. Setting DIVA=0 would disable PLL at boot, this is currently not supported. With default of MULA == 24, and DIVA == 1, PLL is running at 25 times the main clock frequency. |
|
This is the multiplier MULA used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. Setting MULA=0 would disable PLL at boot, this is currently not supported. With default of MULA == 24, and DIVA == 1, PLL is running at 25 times the main clock frequency. |
|
For JTAG debugging CPU clock (HCLK) should not stop. In order to achieve this, make CPU go to Wait mode instead of Sleep mode while using external crystal oscillator for main clock. |
|
Intel ATOM SoC |
|
Broadcom BCM58400 |
|
ARM BEETLE R0 |
|
CC1352R |
|
CC2652R |
|
CC3220SF |
|
CC3235SF |
|
Enable nRF52 series System on Chip DC/DC converter. |
|
Enable nRF53 series System on Chip Application MCU DC/DC converter. |
|
Enable nRF53 series System on Chip High Voltage DC/DC converter. |
|
Enable nRF53 series System on Chip Network MCU DC/DC converter. |
|
This hidden option is set in the SoC configuration and indicates the Zephyr release that the SoC configuration will be removed. When set, any build for that SoC will generate a clearly visible deprecation warning. |
|
Synopsys ARC EM11D of EMSDP |
|
Synopsys ARC EM4 of EMSDP |
|
Synopsys ARC EM5D of EMSDP |
|
Synopsys ARC EM6 of EMSDP |
|
Synopsys ARC EM7D of EMSDP |
|
Synopsys ARC EM7D+ESP of EMSDP |
|
Synopsys ARC EM9D of EMSDP |
|
Synopsys ARC EM Starter Kit SoC |
|
Synopsys ARC EM11D of EMSK |
|
Synopsys ARC EM7D of EMSK |
|
Synopsys ARC EM9D of EMSK |
|
ESP32 |
|
SoC family name which can be found under soc/<arch>/<family>. This option holds the directory name used by the build system to locate the correct linker and header files. |
|
Enable Silicon Labs Gecko series internal flash driver. |
|
Enables the MCUX flash shim driver. WARNING: This driver will disable the system interrupts for the duration of the flash erase/write operations. This will have an impact on the overall system performance - whether this is acceptable or not will depend on the use case. |
|
Enables the Nios-II QSPI flash driver. |
|
Specify the device name for the QSPI flash driver. |
|
Enables Nordic Semiconductor nRF flash driver. |
|
When this option is enabled writing chunks less than minimal write block size parameter (imposed by manufacturer) is possible but operation is more complex and requires basic user knowledge about NVMC controller. |
|
Enable synchronization between flash memory driver and radio. |
|
Enable operations on UICR. Once enabled UICR are written or read as ordinary flash memory. Erase is possible for whole UICR at once. |
|
Enables the RV32M1 flash shim driver. WARNING: This driver will disable the system interrupts for the duration of the flash erase/write operations. This will have an impact on the overall system performance - whether this is acceptable or not will depend on the use case. |
|
Enable the Atmel SAM series internal flash driver. |
|
Enable the Atmel SAM0 series internal flash driver. |
|
Emulate a device with byte-sized pages by doing a read/modify/erase/write. |
|
Enable STM32F0x, STM32F3x, STM32F4x, STM32F7x, STM32L4x, STM32WBx, STM32G0x or STM32G4x series flash driver. |
|
Set if the clock management unit (CMU) is present in the SoC. |
|
Set if the Core interrupt handling (CORE) HAL module is used. |
|
Set if the Ultra Low Energy Timer/Counter (CRYOTIMER) HAL module is used. |
|
Set if the Energy Management Unit (EMU) HAL module is used. |
|
Enable the on chip DC/DC regulator |
|
Bypass |
|
DC/DC Off |
|
DC/DC On |
|
Initial / Unconfigured |
|
Set if the General Purpose Input/Output (GPIO) HAL module is used. |
|
Set if the SoC is affected by errata RTCC_E201: “When the RTCC is configured with a prescaler, the CCV1 top value enable feature enabled by setting CCV1TOP in RTCC_CTRL fails to wrap the counter when RTCC_CNT is equal to RTCC_CC1_CCV, as intended.” |
|
If enabled, indicates that SoC allows to configure individual pin locations. This is supported by e.g. efr32fg1p, efr32mg12p series. If disabled, indicates that pin locations are configured in groups. This is supported by e.g. efm32hg, efm32wg series. |
|
Set if the Inter-Integrated Circuit Interface (I2C) HAL module is used. |
|
Set if the Low Energy Timer (LETIMER) HAL module is used. |
|
Set if the Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) HAL module is used. |
|
Set if the Memory System Controller (MSC) HAL module is used. |
|
Set if the Peripheral Reflex System (PRS) HAL module is used. |
|
Set if the Reset Management Unit (RMU) HAL module is used. |
|
Set if the Real Time Counter (RTC) HAL module is used. |
|
Set if the Real Time Counter and Calendar (RTCC) HAL module is used. |
|
Set if the Timer/Counter (TIMER) HAL module is used. |
|
Set if the Universal Synchronous Asynchronous Receiver/Transmitter (USART) HAL module is used. |
|
Set if the Watchdog Timer (WDOG) HAL module is used. |
|
Generic IA32 SoC |
|
intel_apl_adsp |
|
intel_s1000 |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
SOC_LPC54114_M0 |
|
SOC_LPC54114_M4 |
|
SOC_LPC55S69 M33 [CPU 0] |
|
SOC_LPC55S69 M33 [CPU 1] |
|
SOC_MCIMX6X_M4 |
|
SOC_MCIMX7_M4 |
|
Use an external 32768 Hz clock source for PLL reference clock. Say y if you want to use an external source for the PLL 32KHz reference clock. Say n to use the +/-2% internal silicon oscillator. |
|
Choose a crystal as the external 32KHz source. Say y if you wish to use a crystal as the external 32KHz clock source. Saying n will select the 32KHZ_IN pin as the external 32KHz clock source. |
|
Choose external 32KHz crystal connection. Say y if the crystal is connected parallel between the XTAL1 and XTAL pins. Say n if the crystal is connected single ended to the XTAL2 pin or a 32KHz square wave is on XTAL2. |
|
MEC1501_HSZ |
|
This divisor defines a ratio between processor clock (HCLK) and master clock (MCK): HCLK = MCK / PROC_CLK_DIV Allowed divider values: 1, 3, 4, 16, and 48. |
|
Set this is if VTR3 power sourcejumper in the board is changed. |
|
MEC1701_QSZ |
|
SOC_MIMXRT1011 |
|
SOC_MIMXRT1015 |
|
SOC_MIMXRT1021 |
|
SOC_MIMXRT1051 |
|
SOC_MIMXRT1052 |
|
SOC_MIMXRT1061 |
|
SOC_MIMXRT1062 |
|
SOC_MIMXRT1064 |
|
SOC_MK22F51212 |
|
SOC_MK64F12 |
|
MK80F25615 |
|
MK82F25615 |
|
MKE14F16 |
|
MKE16F16 |
|
MKE18F16 |
|
SOC_MKL25Z4 |
|
MKV56F24 |
|
MKV58F24 |
|
SOC_MKW22D5 |
|
SOC_MKW24D5 |
|
SOC_MKW40Z4 |
|
SOC_MKW41Z4 |
|
ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385) |
|
ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) |
|
MSP432P401R |
|
Nios IIf - Zephyr Golden Configuration |
|
Nios II - Experimental QEMU emulation |
|
Note: This is deprecated, use Cmake function zephyr_linker_sources() instead. Include an SoC specific linker script fragment named soc-noinit.ld for inserting additional data and linker directives into the noinit section. This only has effect if the SoC uses the common linker script under include/arch/. |
|
NRF51822_QFAA |
|
NRF51822_QFAB |
|
NRF51822_QFAC |
|
NRF52810_QFAA |
|
NRF52811_QFAA |
|
Allow enabling the nRF SPI Master with EasyDMA, despite Product Anomaly Notice 58 (SPIM: An additional byte is clocked out when RXD.MAXCNT == 1 and TXD.MAXCNT <= 1). Without this override, the SPI Master is only available without EasyDMA. Note that the ‘SPIM’ and ‘SPIS’ drivers use EasyDMA, while the ‘SPI’ driver does not. Use this option ONLY if you are certain that transactions with RXD.MAXCNT == 1 and TXD.MAXCNT <= 1 will NOT be executed. |
|
NRF52832_CIAA |
|
NRF52832_QFAA |
|
NRF52832_QFAB |
|
NRF52833_QIAA |
|
NRF52840_QIAA |
|
NRF5340_CPUAPP_QKAA |
|
NRF5340_CPUNET_QKAA |
|
NRF9160_SICA |
|
Synopsys nSIM simulator for ARC cores |
|
Synopsys ARC EM in nSIM |
|
Synopsys ARC HS in nSIM |
|
Multi-core Synopsys ARC HS in nSIM |
|
Synopsys ARC SEM in nSIM |
|
OpenISA RV32M1 RI5CY core |
|
Enable support for OpenISA RV32M1 RISC-V processors. Choose this option to target the RI5CY or ZERO-RISCY core. This option should not be used to target either Arm core. |
|
OpenISA RV32M1 ZERO-RISCY core |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
CY8C6247BZI_D54 |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
SAM3X4C |
|
SAM3X4E |
|
SAM3X8C |
|
SAM3X8E |
|
SAM3X8H |
|
SAM4E16C |
|
SAM4E16E |
|
SAM4E8C |
|
SAM4E8E |
|
SAM4S16B |
|
SAM4S16C |
|
SAM4S2A |
|
SAM4S2B |
|
SAM4S2C |
|
SAM4S4A |
|
SAM4S4B |
|
SAM4S4C |
|
SAM4S8B |
|
SAM4S8C |
|
SAMD20E14 |
|
SAMD20E15 |
|
SAMD20E16 |
|
SAMD20E17 |
|
SAMD20E18 |
|
SAMD20G14 |
|
SAMD20G15 |
|
SAMD20G16 |
|
SAMD20G17 |
|
SAMD20G17U |
|
SAMD20G18 |
|
SAMD20G18U |
|
SAMD20J14 |
|
SAMD20J15 |
|
SAMD20J16 |
|
SAMD20J17 |
|
SAMD20J18 |
|
SAMD21E15A |
|
SAMD21E16A |
|
SAMD21E17A |
|
SAMD21E18A |
|
SAMD21G15A |
|
SAMD21G16A |
|
SAMD21G17A |
|
SAMD21G17AU |
|
SAMD21G18A |
|
SAMD21G18AU |
|
SAMD21J15A |
|
SAMD21J16A |
|
SAMD21J17A |
|
SAMD21J18A |
|
SAMD51G18A |
|
SAMD51G19A |
|
SAMD51J18A |
|
SAMD51J19A |
|
SAMD51J20A |
|
SAMD51N19A |
|
SAMD51N20A |
|
SAMD51P19A |
|
SAMD51P20A |
|
SAME51J18A |
|
SAME51J19A |
|
SAME51J20A |
|
SAME51N19A |
|
SAME51N20A |
|
SAME53J18A |
|
SAME53J19A |
|
SAME53J20A |
|
SAME53N19A |
|
SAME53N20A |
|
SAME54N19A |
|
SAME54N20A |
|
SAME54P19A |
|
SAME54P20A |
|
SAME70J19 |
|
SAME70J19B |
|
SAME70J20 |
|
SAME70J20B |
|
SAME70J21 |
|
SAME70J21B |
|
SAME70N19 |
|
SAME70N19B |
|
SAME70N20 |
|
SAME70N20B |
|
SAME70N21 |
|
SAME70N21B |
|
SAME70Q19 |
|
SAME70Q19B |
|
SAME70Q20 |
|
SAME70Q20B |
|
SAME70Q21 |
|
SAME70Q21B |
|
SAMR21E16A |
|
SAMR21E17A |
|
SAMR21E18A |
|
SAMR21E19A |
|
SAMR21G16A |
|
SAMR21G17A |
|
SAMR21G18A |
|
SAMV71J19 |
|
SAMV71J19B |
|
SAMV71J20 |
|
SAMV71J20B |
|
SAMV71J21 |
|
SAMV71J21B |
|
SAMV71N19 |
|
SAMV71N19B |
|
SAMV71N20 |
|
SAMV71N20B |
|
SAMV71N21 |
|
SAMV71N21B |
|
SAMV71Q19 |
|
SAMV71Q19B |
|
SAMV71Q20 |
|
SAMV71Q20B |
|
SAMV71Q21 |
|
SAMV71Q21B |
|
SOC for to the POSIX arch. It emulates a CPU running at an infinitely fast clock. That means the CPU will always run in zero time until completion after each wake reason (e.g. interrupts), before going back to idle. Note that an infinite loop in the code which does not sleep the CPU will cause the process to appear “hung”, as simulated time does not advance while the CPU does not sleep. Therefore do not use busy waits while waiting for something to happen (if needed use k_busy_wait()). Note that the interrupt handling is provided by the board. |
|
MEC1501 Power Management |
|
SOC_PSOC6_M0 |
|
SOC_PSOC6_M4 |
|
QEMU virt platform (cortex-a53) |
|
LiteX VexRiscv system implementation |
|
Microsemi Mi-V system implementation |
|
SiFive Freedom SOC implementation |
|
Note: This is deprecated, use Cmake function zephyr_linker_sources() instead. Include an SoC specific linker script fragment named soc-rodata.ld for inserting additional data and linker directives into the rodata section. This only has effect if the SoC uses the common linker script under include/arch/. |
|
Note: This is deprecated, use Cmake function zephyr_linker_sources() instead. Include an SoC specific linker script fragment named soc-rwdata.ld for inserting additional data and linker directives into the data section. This only has effect if the SoC uses the common linker script under include/arch/. |
|
SoC series name which can be found under soc/<arch>/<family>/<series>. This option holds the directory name used by the build system to locate the correct linker and header files. |
|
Enable support for Beetle MCU Series |
|
Any NRF52 simulated SOC with BabbleSim, based on the POSIX arch |
|
Any NRF simulated SOC with BabbleSim, based on the POSIX arch |
|
Enable support for TI SimpleLink CC13x2 / CC26x2 SoCs |
|
Enable support for TI SimpleLink CC32xx |
|
Enable support for EFM32 GiantGecko MCU series |
|
Enable support for EFM32 Happy Gecko MCU series |
|
Enable support for EFM32 JadeGecko MCU series |
|
Enable support for EFM32 PearlGecko MCU series |
|
Enable support for EFM32 WonderGecko MCU series |
|
Enable support for EFR32 FlexGecko MCU series |
|
Enable support for EFR32 Mighty Gecko MCU series |
|
Enable support for i.MX7 M4 MCU series |
|
Enable support for M4 core of i.MX 6SoloX MCU series |
|
Enable support for i.MX RT MCU series |
|
Enable support for Kinetis K2x MCU series |
|
Enable support for Kinetis K6x MCU series |
|
Enable support for Kinetis K8x MCU series |
|
Enable support for Kinetis KE1xF MCU series |
|
Enable support for Kinetis KL2x MCU series |
|
Enable support for Kinetis KV5x MCU series |
|
Enable support for Kinetis KWx MCU series |
|
Enable support for LPC LPC54XXX MCU series |
|
Enable support for LPC5500 Series MCU series |
|
Enable support for Microchip MEC Cortex-M4 MCU series |
|
Enable support for Microchip MEC Cortex-M4 MCU series |
|
Enable support for ARM MPS2 MCU Series |
|
Enable support for TI SimpleLink MSP432P4XX. |
|
Enable support for ARM MPS2 MCU Series |
|
Enable support for arm V2M Musca B1 MCU Series |
|
Enable support for NRF51 MCU series |
|
Enable support for NRF52 MCU series |
|
Enable support for NRF53 MCU series |
|
Enable support for NRF91 MCU series |
|
Enable support for Cypress PSoC6 MCU series |
|
Enable support for Microsemi Mi-V |
|
Enable support for SiFive Freedom SOC |
|
Enable support for Atmel SAM3X Cortex-M3 microcontrollers. Part No.: SAM3X8E |
|
Enable support for Atmel SAM4E Cortex-M4 microcontrollers. Part No.: SAM4E16E, SAM4E16C, SAM4E8E, SAM4E8C |
|
Enable support for Atmel SAM4S Cortex-M4 microcontrollers. Part No.: SAM4S16C, SAM4S16B, SAM4S8C, SAM4S8B, SAM4S4C, SAM4S4B, SAM4S4A, SAM4S2C, SAM4S2B, SAM4S2A |
|
Enable support for Atmel SAMD20 Cortex-M0+ microcontrollers. |
|
Enable support for Atmel SAMD21 Cortex-M0+ microcontrollers. |
|
Enable support for Atmel SAMD51 Cortex-M4F microcontrollers. |
|
Enable support for Atmel SAME51 Cortex-M4F microcontrollers. |
|
Enable support for Atmel SAME53 Cortex-M4F microcontrollers. |
|
Enable support for Atmel SAME54 Cortex-M4F microcontrollers. |
|
Enable support for Atmel SAM E70 ARM Cortex-M7 Microcontrollers. Part No.: SAME70J19, SAME70J20, SAME70J21, SAME70N19, SAME70N20, SAME70N21, SAME70Q19, SAME70Q20, SAME70Q21, SAME70J19B, SAME70J20B, SAME70J21B, SAME70N19B, SAME70N20B, SAME70N21B, SAME70Q19B, SAME70Q20B, SAME70Q21B |
|
Enable support for Atmel SAMR21 Cortex-M0+ microcontrollers. |
|
Enable support for Atmel SAM V71 ARM Cortex-M7 Microcontrollers. Part No.: SAMV71J19, SAMV71J20, SAMV71J21, SAMV71N19, SAMV71N20, SAMV71N21, SAMV71Q19, SAMV71Q20, SAMV71Q21, SAMV71J19B, SAMV71J20B, SAMV71J21B, SAMV71N19B, SAMV71N20B, SAMV71N21B, SAMV71Q19B, SAMV71Q20B, SAMV71Q21B |
|
Enable support for STM32F0 MCU series |
|
Enable support for STM32F1 MCU series |
|
Enable support for stm32f2 MCU series |
|
Enable support for STM32F3 MCU series |
|
Enable support for STM32F4 MCU series |
|
Enable support for STM32F7 MCU series |
|
Enable support for STM32G0 MCU series |
|
Enable support for STM32G4 MCU series |
|
Enable support for STM32H7 MCU series |
|
Enable support for STM32L0 MCU series |
|
Enable support for STM32L1 MCU series |
|
Enable support for STM32L4 MCU series |
|
Enable support for STM32MP1 MPU series |
|
Enable support for STM32WB MCU series |
|
Enable support for Broadcom Valkyrie Series |
|
STM32F030X4 |
|
STM32F030X8 |
|
STM32F051X8 |
|
STM32F070XB |
|
STM32F072XB |
|
STM32F091XC |
|
STM32F098XX |
|
STM32F100XB |
|
STM32F100XE |
|
STM32F103X8 |
|
STM32F103XB |
|
STM32F103XE |
|
STM32F107XC |
|
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. They are intended for applications where connectivity and real-time performances are required such as industrial control, control panels for security applications, UPS or home audio. For STM32F107xx also the Ethernet MAC is available. |
|
|
|
STM32F207XX |
|
STM32F302X8 |
|
STM32F303XC |
|
STM32F334X8 |
|
STM32F373XC |
|
STM32F401XC |
|
STM32F401XE |
|
STM32F405XG |
|
STM32F407XG |
|
STM32F411XE |
|
STM32F412CG |
|
STM32F412ZG |
|
STM32F413XX |
|
STM32F415XX |
|
STM32F417XX |
|
STM32F429XI |
|
STM32F437XX |
|
STM32F446XX |
|
STM32F469XX |
|
STM32F723XX |
|
STM32F746XX |
|
STM32F756XX |
|
STM32F767XX |
|
STM32F769XX |
|
STM32G031XX |
|
STM32G071XX |
|
STM32G431XX |
|
STM32G474XX |
|
STM32H747XX |
|
STM32L053XX |
|
STM32L072XX |
|
STM32L073XX |
|
STM32L151X8A |
|
STM32L151XB |
|
STM32L151XBA |
|
STM32L152XE |
|
STM32L432XX |
|
STM32L433XX |
|
STM32L452XX |
|
STM32L471XX |
|
STM32L475XX |
|
STM32L476X |
|
STM32L496XX |
|
STM32L4R5XX |
|
STM32L4R9XX |
|
STM32MP15_M4 |
|
STM32WB55XX |
|
TI LM3S6965 |
|
ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA |
|
ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA-B1 |
|
Xilinx ZynqMP RPU |
|
Xtensa sample_controller core |
|
Compiler optimizations will be set to -O2 independently of other options. |
|
Enable support for the SPI hardware bus. |
|
There’s a spinlock validation framework available when asserts are enabled. It adds a relatively hefty overhead (about 3k or so) to kernel code size, don’t use on platforms known to be small. |
|
Enable SPI controller port 0. |
|
Over-read character. Character clocked out after an over-read of the transmit buffer. |
|
Enable nRF SPI Master without EasyDMA on port 0. |
|
Enable nRF SPI Master with EasyDMA on port 0. |
|
Enable nRF SPI Slave with EasyDMA on port 0. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM. |
|
This sets the supported operation modes at runtime, by the SPI port 0, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 1. |
|
Over-read character. Character clocked out after an over-read of the transmit buffer. |
|
Enable nRF SPI Master without EasyDMA on port 1. |
|
Enable nRF SPI Master with EasyDMA on port 1. |
|
Enable nRF SPI Slave with EasyDMA on port 1. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM. |
|
This sets the supported operation modes at runtime, by the SPI port 1, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 2. |
|
Over-read character. Character clocked out after an over-read of the transmit buffer. |
|
Enable nRF SPI Master without EasyDMA on port 2. |
|
Enable nRF SPI Master with EasyDMA on port 2. |
|
Enable nRF SPI Slave with EasyDMA on port 2. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM. |
|
This sets the supported operation modes at runtime, by the SPI port 2, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 3. |
|
Over-read character. Character clocked out after an over-read of the transmit buffer. |
|
Number of 64 MHz clock cycles (15.625 ns) delay from the sampling edge of SCK (leading or trailing, depending on the CPHA setting used) until the input serial data on MISO is actually sampled. |
|
Enable nRF SPI Master with EasyDMA on port 3. |
|
Enable nRF SPI Slave with EasyDMA on port 3. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM. |
|
This sets the supported operation modes at runtime, by the SPI port 3, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 4. |
|
Over-read character. Character clocked out after an over-read of the transmit buffer. |
|
Number of 64 MHz clock cycles (15.625 ns) delay from the sampling edge of SCK (leading or trailing, depending on the CPHA setting used) until the input serial data on MISO is actually sampled. |
|
Enable nRF SPI Master with EasyDMA on port 4. |
|
This sets the supported operation modes at runtime, by the SPI port 4, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 5. |
|
This sets the supported operation modes at runtime, by the SPI port 5, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 6. |
|
This sets the supported operation modes at runtime, by the SPI port 6, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 7. |
|
This sets the supported operation modes at runtime, by the SPI port 7, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 8. |
|
This sets the supported operation modes at runtime, by the SPI port 8, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
This option enables the asynchronous API calls. |
|
Enable support for the TI SimpleLink CC13xx / CC26xx SPI peripheral |
|
Enable support for Designware’s SPI controllers. |
|
In some case, e.g. ARC HS Development kit, the peripheral space of DesignWare SPI only allows word access, byte access will raise exception. |
|
SPI IP block registers are part of user extended auxiliary registers and thus their access is different than memory mapped registers. |
|
Corresponds to the SSI_TX_FIFO_DEPTH and SSI_RX_FIFO_DEPTH of the DesignWare Synchronous Serial Interface. Depth ranges from 2-256. |
|
Enable clock gating |
|
Clock controller’s subsystem |
|
Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated. |
|
Enable clock gating |
|
Clock controller’s subsystem |
|
Single interrupt line for all interrupts |
|
Enable clock gating |
|
Clock controller’s subsystem |
|
Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated. |
|
Enable clock gating |
|
Clock controller’s subsystem |
|
Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated. |
|
SPI NOR Flash Winbond W25QXXDV |
|
This is the device ID of the flash chip to use, which is 0x00ef4015 for the W25QXXDV |
|
SPI flash device name |
|
This is the flash capacity in bytes. |
|
This is the wait delay (in us) to allow for CS switching to take effect |
|
This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic. |
|
Device driver initialization priority. Device is connected to SPI bus, it has to be initialized after SPI driver. |
|
This is the maximum size of a page program operation. Writing data over this page boundary will split the write operation into two pages. |
|
Enable the SPI peripherals on Gecko |
|
Device driver initialization priority. |
|
Enable the SPI peripherals on LiteX |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable support for mcux spi driver. |
|
Enable support for mcux flexcomm spi driver. |
|
Enable support for mcux spi driver. |
|
SPI NOR Flash |
|
This is the wait delay (in us) to allow for CS switching to take effect |
|
When CONFIG_FLASH_PAGE_LAYOUT is used this driver will support that API. By default the page size corresponds to the block size (65536). Other options include the 32K-byte erase size (32768), the sector size (4096), or any non-zero multiple of the sector size. |
|
Where supported deep power-down mode can reduce current draw to as little as 0.1% of standby current. However it takes some milliseconds to enter and exit from this mode. Select this option for applications where device power management is not enabled, the flash remains inactive for long periods, and when used the impact of waiting for mode enter and exit delays is acceptable. |
|
Device driver initialization priority. Device is connected to SPI bus, it has to be initialized after SPI driver. |
|
Enable support for nrfx SPI drivers for nRF MCU series. Peripherals with the same instance ID cannot be used together, e.g. SPI_0 and I2C_0. You may need to disable I2C_0 or I2C_1. |
|
SPIM peripherals cannot transmit data directly from flash. Therefore, a buffer in RAM needs to be provided for each instance of SPI driver using SPIM peripheral, so that the driver can copy there a chunk of data from flash and transmit it. The size is specified in bytes. A size of 0 means that this feature should be disabled, and the application must then take care of not supplying buffers located in flash to the driver, otherwise such transfers will fail. |
|
Enable the Simple SPI controller |
|
Enable the RV32M1 LPSPI driver. |
|
Enable support for the SAM SPI driver. |
|
Enable support for the SAM0 SERCOM SPI driver. |
|
Enable SPI0 at boot |
|
PA11 |
|
PB2 |
|
PA31 |
|
PA9 |
|
PB14 |
|
PC4 |
|
PD25 |
|
PA10 |
|
PA30 |
|
PB2 |
|
PD12 |
|
PA22 |
|
PA3 |
|
PA5 |
|
PD27 |
|
Enable SPI1 at boot |
|
PC25 |
|
PC28 |
|
PD0 |
|
PC29 |
|
PD1 |
|
PC30 |
|
PD2 |
|
Enable the SPI peripherals on SiFive Freedom processors |
|
Enables Driver SPI slave operations. Slave support depends on the driver and the hardware it runs on. |
|
Enable SPI support on the STM32 family of processors. |
|
Enable Interrupt support for the SPI Driver of STM32 family. |
|
Use Slave Select pin instead of software Slave Select. |
|
Enable support for the Microchip XEC QMSPI driver. |
|
The SRAM base address. The default value comes from from /chosen/zephyr,sram in devicetree. The user should generally avoid changing it via menuconfig or in configuration files. |
|
The SRAM size in kB. The default value comes from /chosen/zephyr,sram in devicetree. The user should generally avoid changing it via menuconfig or in configuration files. |
|
Enable driver for SSD1306 display driver. |
|
Default SSD1306 controller |
|
SSD16XX default contrast. |
|
SSD16XX reverse video mode. |
|
Enable SH1106 compatible mode |
|
Enable driver for SSD16XX compatible controller. |
|
This option enables the use of SSE registers by threads. |
|
This option allows the compiler to generate SSEx instructions for performing floating point math. This can greatly improve performance when exactly the same operations are to be performed on multiple data objects; however, it can also significantly reduce performance when preemptive task switches occur because of the larger register set that must be saved and restored. Disabling this option means that the compiler utilizes only the x87 instruction set for floating point operations. |
|
Enable driver for ST7789V display driver. |
|
RGB565 |
|
RGB888 |
|
This is needed to conform to AAPCS, the procedure call standard for the ARM. It wastes stack space. The option also enforces alignment of stack upon exception entry on Cortex-M3 and Cortex-M4 (ARMv7-M). Note that for ARMv6-M, ARMv8-M, and Cortex-M7 MCUs stack alignment on exception entry is enabled by default and it is not configurable. |
|
This option enables compiler stack canaries. If stack canaries are supported by the compiler, it will emit extra code that inserts a canary value into the stack frame when a function is entered and validates this value upon exit. Stack corruption (such as that caused by buffer overflow) results in a fatal error condition for the running entity. Enabling this option can result in a significant increase in footprint and an associated decrease in performance. If stack canaries are not supported by the compiler an error will occur at build time. |
|
Select this option if the architecture has upward growing thread stacks. This is not common. |
|
This option performs a limited form of Address Space Layout Randomization by offsetting some random value to a thread’s initial stack pointer upon creation. This hinders some types of security attacks by making the location of any given stack frame non-deterministic. This feature can waste up to the specified size in bytes the stack region, which is carved out of the total size of the stack region. A reasonable minimum value would be around 100 bytes if this can be spared. This is currently only implemented for systems whose stack pointers grow towards lower memory addresses. |
|
Store a magic value at the lowest addresses of a thread’s stack. Periodically check that this value is still present and kill the thread gracefully if it isn’t. This is currently checked in four places:
This feature doesn’t prevent corruption and the system may be in an unusable state. However, given the bizarre behavior associated with stack overflows, knowledge that this is happening is very useful. This feature is intended for those systems which lack hardware support for stack overflow protection, or have insufficient system resources to use that hardware support. |
|
Generate an extra file that specifies the maximum amount of stack used, on a per-function basis. |
|
Enable per-module event counters for troubleshooting, maintenance, and usage monitoring. Statistics can be retrieved with the mcumgr management subsystem. |
|
Include a full name string for each statistic in the build. If this setting is disabled, statistics are assigned generic names of the form “s0”, “s1”, etc. Enabling this setting simplifies debugging, but results in a larger code size. |
|
Limits the maximum stat group name length in mcumgr requests, in bytes. A buffer of this size gets allocated on the stack during handling of all stat read commands. If a stat group’s name exceeds this limit, it will be impossible to retrieve its values with a stat show command. |
|
This option directs standard output (e.g. printf) to the console device, rather than suppressing it entirely. See also EARLY_CONSOLE option. |
|
2011 C++ standard, previously known as C++0x. |
|
2014 C++ standard. |
|
2017 C++ standard, previously known as C++0x. |
|
Next revision of the C++ standard, which is expected to be published in 2020. |
|
1998 C++ standard as modified by the 2003 technical corrigendum and some later defect reports. |
|
Cortex-M7 and Cortex-M4 running from the flash (each from a bank) System configuration performed by the Cortex-M7 Cortex-M4 goes to STOP after boot, then woken-up by Cortex-M7 using a HW semaphore |
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Cortex-M4 boot is gated using Flash option bytes Cortex-M7 and Cortex-M4 running from the flash (each from a bank) Cortex-M7 boots , performs the System configuration then enable the Cortex-M4 boot using RCC. This mode requires option byte setting update (BCM4 unchecked) |
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Enable Dual Core |
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LPTIM clock value |
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Use LSE as LPTIM clock |
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Use LSI as LPTIM clock |
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LPTIM AutoReload value |
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This module implements a kernel device driver for the LowPower Timer and provides the standard “system clock driver” interfaces. |
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Enable driver for STTS751 I2C-based temperature sensor. |
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Sensor output data rate expressed in conversions per second. Data rates supported by the chip are: 0: 1 conv every 16 sec 1: 1 conv every 8 sec 2: 1 conv every 4 sec 3: 1 conv every 2 sec 4: 1 conv every sec 5: 2 convs every sec 6: 4 convs every sec 7: 8 convs every sec 8: 16 convs every sec 9: 32 convs every sec |
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HIGH temperature threshold to trigger an alarm |
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LOW temperature threshold to trigger an alarm |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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On some architectures, the _Swap() primitive cannot be made atomic with respect to the irq_lock being released. That is, interrupts may be received between the entry to _Swap and the completion of the context switch. There are a handful of workaround cases in the kernel that need to be enabled when this is true. Currently, this only happens on ARM when the PendSV exception priority sits below that of Zephyr-handled interrupts. |
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Programmable Interrupt Controller for the SweRV EH1 RISC-V CPU; |
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This option indicates that we want to switch to EL1 at boot. Only switching to EL1 from EL3 is supported. |
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Add Vector Table relay handler and relay vector table, to relay interrupts based on a vector table pointer. This is only required for Cortex-M0 (or an Armv8-M baseline core) with no hardware vector table relocation mechanisms or for Cortex-M0+ (or an Armv8-M baseline core) with no VTOR and no other hardware relocation table mechanisms. |
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Enable driver for SX9500 I2C-based SAR proximity sensor. |
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The SX9500 offers 4 separate proximity channels. Choose which one you are using. Valid numbers are 0 to 3. |
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Thread priority |
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Sensor delayed work thread stack size |
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Use global thread |
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No trigger |
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Use own thread |
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This option enables the sys_clock_disable() API in the kernel. It is needed by some subsystems (which will automatically select it), but is rarely needed by applications. |
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This options can be used to set a specific initialization priority value for the system clock driver. As driver initialization might need the clock to be running already, you should let the default value as it is (0). |
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When true, the timer driver is not required to maintain a correct system uptime count when the system enters idle. Some platforms may take advantage of this to reduce the overhead from regular interrupts required to handle counter wraparound conditions. |
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By default, system work queue priority is the lowest cooperative priority. This means that any work handler, once started, won’t be preempted by any other thread until finished. |
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System workqueue stack size |
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This option specifies that the kernel lacks timer support. Some device configurations can eliminate significant code if this is disabled. Obviously timeout-related APIs will not work. |
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This option specifies hardware clock. |
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This option specifies the nominal frequency of the system clock in Hz. Depending on the choice made, an amount of possibly expensive math must occur when converting ticks to milliseconds and vice-versa. Some values are optimized, and yield significantly less math. The optimal values from a computational point-of-view are 1000, 500, 250 and 125, since in these cases there is either no computation required, or it is all done via bit-shifting. These also give a granularity from 1ms to 8ms. Other good values are 100, 50, 25, 20 and 10. In this case, some math is required but is minimized. These are also values that necessitate a reduced number of clock interrupts per second, at the cost of granularity (10ms to 100ms). All other values require some extensive 64-bit math, and in some configurations even require calls to compiler built-in functions, and can require a non-trivial extra amount of stack space (e.g. around 80 bytes on x86). Note that when available and enabled, in “tickless” mode this config variable specifies the minimum available timing granularity, not necessarily the number or frequency of interrupts delivered to the kernel. A value of 0 completely disables timer support in the kernel. |
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Enable System Power Management debugging hooks. |
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Enable system power management direct force trigger mode. In this mode application thread can directly put system in sleep or deep sleep mode instead of waiting for idle thread to do it, so that it can reduce latency to enter low power mode. |
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Debug |
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Error |
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Info |
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Off |
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Warning |
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Minimum residency in milliseconds to enter SYS_POWER_STATE_DEEP_SLEEP_1 state. |
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Minimum residency in milliseconds to enter SYS_POWER_STATE_DEEP_SLEEP_2 state. |
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Minimum residency in milliseconds to enter SYS_POWER_STATE_DEEP_SLEEP_3 state. |
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Minimum residency in milliseconds to enter SYS_POWER_STATE_SLEEP_1 state. |
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Minimum residency in milliseconds to enter SYS_POWER_STATE_SLEEP_2 state. |
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Minimum residency in milliseconds to enter SYS_POWER_STATE_SLEEP_3 state. |
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When this option is selected, the application must provide PM policy. |
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Dummy PM Policy which simply returns next PM state in a loop. |
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Select this option for PM policy based on CPU residencies. |
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Enable Power Management system state locking capability if any application wants to temporarily disable certain Power States while doing any critical work or needs quick response from hardware resources. |
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This option enables the kernel to interface with a power manager application. This permits the system to enter a Deep sleep state supported by the SOC where the system clock is turned off while RAM is retained. This state would be entered when the kernel becomes idle for extended periods and would have a high wake latency. Resume would be from the reset vector same as cold boot. The interface allows restoration of states that were saved at the time of suspend. |
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This option enables the board to implement extra power management policies whenever the kernel becomes idle. The kernel informs the power management subsystem of the number of ticks until the next kernel timer is due to expire. |
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This option enables the kernel to interface with a power manager application. This permits the system to enter a custom CPU low power state when the kernel becomes idle. The low power state could be any of the CPU low power states supported by the processor. Generally the one saving most power. |
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Enable driver for NXP Kinetis temperature sensor. |
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ADC oversampling to use for the temperature sensor and bandgap voltage readings. Oversampling can help in providing more stable readings. |
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ADC resolution to use for the temperature sensor and bandgap voltage readings. |
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Enable driver for nRF5 temperature sensor. |
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Mark a project or an application as a test. This will enable a few test defaults. |
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ARM Cortex-M configuration required when testing. Currently, this option is only utilized, to force routing BusFault, HardFault, and NMI exceptions to Secure State, when building a Secure ARMv8-M firmware. This will allow the testing suite to utilize these exceptions, in tests. Note that by default, when building with ARM_SECURE_FIRMWARE set, these exceptions are set to target the Non-Secure state. |
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This hidden option implements the TEST_USERSPACE logic. It turns on USERSPACE when CONFIG_ARCH_HAS_USERSPACE is set and the test case itself indicates that it exercises user mode via CONFIG_TEST_USERSPACE. |
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Additional stack for tests on some platform where default is not enough. |
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This option will help test the flash drivers. This should be enabled only when using qemu_x86. |
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This option will enable hardware-based stack protection by default for all test cases if the hardware supports it. |
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Option which implements default policy of enabling logging in minimal mode for all test cases. For tests that need alternate logging configuration, or no logging at all, disable this in the project-level defconfig. |
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This option signifies that the kernel’s random number APIs are permitted to return values that are not truly random. This capability is provided for testing purposes, when a truly random number generator is not available. The non-random number generator should not be used in a production environment. |
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Enable various platform and driver related shells for testing. |
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This option indicates that a test case puts threads in user mode, and that the build system will [override and] enable USERSPACE if the platform supports it. It should be set in a .conf file on a per-test basis and is not meant to be used outside test cases. Tests with this option should also have the “userspace” filtering tag in their testcase.yaml file. The userspace APIs are no-ops if userspace is not enabled, so it is OK to enable this even if the test will run on platforms which do not support userspace. The test should still run on those platforms, just with all threads in supervisor mode. If a test requires that userspace be enabled in order to pass, CONFIG_ARCH_HAS_USERSPACE should be filtered in its testcase.yaml. |
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A HW platform might not have sufficient MPU/MMU capabilities to support running all test cases with User Mode and HW Stack Protection features simultaneously enabled. For this platforms we execute the User Mode- related tests without enabling HW stack protection. |
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If the application is built for chain-loading by a bootloader this variable is required to be set to value that leaves sufficient space between the beginning of the image and the start of the .text section to store an image header or any other metadata. In the particular case of the MCUboot bootloader this reserves enough space to store the image header, which should also meet vector table alignment requirements on most ARM targets, although some targets may require smaller or larger values. |
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Enable driver for the TH02 temperature sensor. |
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This option allows each thread to store 32 bits of custom data, which can be accessed using the k_thread_custom_data_xxx() APIs. |
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Thread names get stored in the k_thread struct. Indicate the max name length, including the terminating NULL byte. Reduce this value to conserve memory. |
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This option instructs the kernel to maintain a list of all threads (excluding those that have not yet started or have already terminated). |
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This option allows to set a name for a thread. |
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This option allows each thread to store the thread stack info into the k_thread data structure. |
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Timer drivers should select this flag if they are capable of supporting tickless operation. That is, a call to z_clock_set_timeout() with a number of ticks greater than one should be expected not to produce a call to z_clock_announce() (really, not to produce an interrupt at all) until the specified expiration. |
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This option suppresses periodic system clock interrupts whenever the kernel becomes idle. This permits the system to remain in a power saving state for extended periods without having to wake up to service each tick as it occurs. |
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This option enables clock interrupt suppression when the kernel idles for only a short period of time. It specifies the minimum number of ticks that must occur before the next kernel timer expires in order for suppression to happen. |
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This option enables a fully event driven kernel. Periodic system clock interrupt generation would be stopped at all times. |
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The dualtimer (DTMR) present in the platform is used as a timer. This option enables the support for the timer. |
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This options enables number generator based on system timer clock. This number generator is not random and used for testing only. |
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The drivers select this option automatically when needed. Do not modify this unless you have a very good reason for it. |
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The timers (TMR) present in the platform are used as timers. This option enables the support for the timers. |
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This option specifies the thread priority level at which time slicing takes effect; threads having a higher priority than this ceiling are not subject to time slicing. |
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This option specifies the maximum amount of time a thread can execute before other threads of equal priority are given an opportunity to run. A time slice size of zero means “no limit” (i.e. an infinitely large time slice). |
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This option enables time slicing between preemptible threads of equal priority. |
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This option enables the tinyCBOR library. |
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This option enables the TinyCrypt cryptography library. |
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This option enables support for AES-128 decrypt and encrypt. |
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This option enables support for AES-128 block cipher mode. |
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This option enables support for AES-128 CCM mode. |
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This option enables support for AES-128 CMAC mode. |
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This option enables support for AES-128 counter mode. |
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This option enables support for the pseudo-random number generator in counter mode. |
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This option enables support for the Elliptic curve Diffie-Hellman anonymous key agreement protocol. Enabling ECC requires a cryptographically secure random number generator. |
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This option enables support for the Elliptic Curve Digital Signature Algorithm (ECDSA). Enabling ECC requires a cryptographically secure random number generator. |
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This option enables support for SHA-256 hash function primitive. |
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This option enables support for HMAC using SHA-256 message authentication code. |
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This option enables support for pseudo-random number generator. |
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Enable driver for TI temperature and humidity sensors. |
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Enable TLS credentials management subsystem. |
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Allows clients of the socket APIs to specify filenames of security certificates and private keys to use during subsequent TLS/SSL negotiations. The secure files will have been previously provisioned to the device’s secure file system; eg, via a vendor tool or by executing a separate binary. This option is currently only available for secure socket offload devices. |
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Maximum number of TLS credentials that can be registered. |
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Enable driver for TMP007 infrared thermopile sensors. |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable the driver for Texas Instruments TMP112 High-Accuracy Digital Temperature Sensors. The TMP102 is compatible with the TMP112 but is less accurate and has been successfully tested with this driver. |
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Enable driver for TMP116 temperature sensor. |
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Enable system tracing. This requires a backend such as SEGGER Systemview to be enabled as well. |
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Enable asynchronous tracing. This will buffer all the tracing packets to the ring buffer first, tracing thread will try to output as much data as possible from the buffer when tracing thread get scheduled. |
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Use posix architecture to output tracing data to file system. |
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Use UART to output tracing data. |
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This option specifies the name of UART device to be used for tracing backend. |
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Use USB to output tracing data. |
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Size of tracing buffer. If TRACING_ASYNC is enabled, tracing buffer is used as a ring buffer to buffer data packet and string packet. If TRACING_SYNC is enabled, the buffer is used to hold the formated data. |
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Size of tracing command buffer. |
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Automatically selected by formats that require the core tracing infrastructure. |
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Module provides information about percent of CPU usage based on tracing hooks for threads switching in and out, interrupts enters and exits (only distinguishes between idle thread, non idle thread and scheduler). Use provided API or enable automatic logging to get values. |
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Time period of displaying information about CPU usage. |
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Periodically displays information about CPU usage. |
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Enable tracing to a Common Trace Format stream. |
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Timestamp prefix will be added to the beginning of CTF event internally. |
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When enabled tracing will handle cmd from host to dynamically enable and disable tracing to have host capture tracing stream data conveniently. |
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Enable tracing ISRs. This requires the backend to be very low-latency. |
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None of the available tracing formats is selected. |
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Max size of one tracing packet. |
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Enable synchronous tracing. This requires the backend to be very low-latency. |
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Enable tracing for testing kinds of format purpose. It must implement the tracing hooks defined in tracing_test.h |
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Stack size of tracing thread. |
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Tracing thread waiting period given in milliseconds after every first packet put to tracing buffer. |
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USB tracing backend max packet size(endpoint MPS). |
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Select this option to enable building a Non-Secure firmware image for a platform that supports Trusted Execution. A Non-Secure firmware image will execute in Non-Secure (Normal) state. Therefore, it shall not access CPU resources (memory areas, peripherals, interrupts etc.) belonging to the Secure domain. |
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Select this option to enable building a Secure firmware image for a platform that supports Trusted Execution. A Secure firmware image will execute in Secure state. It may allow the CPU to execute in Non-Secure (Normal) state. Therefore, a Secure firmware image shall be able to configure security attributions of CPU resources (memory areas, peripherals, interrupts, etc.) as well as to handle faults, related to security violations. It may optionally allow certain functions to be called from the Non-Secure (Normal) domain. |
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The x86 implementation of LOAPIC k_cycle_get_32() relies on the x86 TSC. This runs at the CPU speed and not the bus speed. If set to 0, the value of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC will be used instead; many MCUs these values are the same. |
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This option enables UART Asynchronous API support on port 0. |
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If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up. |
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This option enables UART interrupt support on port 0. |
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Enable flow control. If selected, additionally two pins, RTS and CTS have to be configured. |
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If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel |
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Timer instance |
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Enable parity bit. |
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Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC. |
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Enable nRF UART without EasyDMA on port 0. |
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Enable nRF UART with EasyDMA on port 0. |
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Enable support for USART1 port in the driver. Say y here if you want to use USART1 device. |
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Enable support for UART10 port in the driver. Say y here if you want to use UART10 device. |
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This option enables UART Asynchronous API support on port 1. |
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If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up. |
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This option enables UART interrupt support on port 1. |
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Enable flow control. If selected, additionally two pins, RTS and CTS have to be configured. |
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If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel |
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Timer instance |
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Enable parity bit. |
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Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC. |
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Enable nRF UART with EasyDMA on port 1. |
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Enable support for USART2 port in the driver. Say y here if you want to use USART2 device. |
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This option enables UART Asynchronous API support on port 2. |
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If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up. |
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This option enables UART interrupt support on port 2. |
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Enable flow control. If selected, additionally two pins, RTS and CTS have to be configured. |
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If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel |
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Timer instance |
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Enable parity bit. |
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Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC. |
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Enable nRF UART with EasyDMA on port 2. |
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Enable support for USART3 port in the driver. Say y here if you want to use USART3 device. |
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This option enables UART Asynchronous API support on port 3. |
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If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up. |
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This option enables UART interrupt support on port 3. |
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Enable flow control. If selected, additionally two pins, RTS and CTS have to be configured. |
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If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel |
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Timer instance |
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Enable parity bit. |
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Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC. |
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Enable nRF UART with EasyDMA on port 3. |
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Enable support for U(S)ART4 port in the driver. Say y here if you want to use U(S)ART4 device. |
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Enable support for U(S)ART5 port in the driver. Say y here if you want to use U(S)ART5 device. |
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Enable support for USART6 port in the driver. Say y here if you want to use USART6 device. |
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Enable support for U(S)ART7 port in the driver. Say y here if you want to use U(S)ART7 device. |
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Enable support for U(S)ART8 port in the driver. Say y here if you want to use U(S)ART8 device. |
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Enable support for UART9 port in the driver. Say y here if you want to use UART9 device. |
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Enable the Altera JTAG UART driver, built in to many Nios II CPU designs. |
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This option enables new asynchronous UART API. |
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Enable the TI SimpleLink CC13xx / CC26xx UART driver. |
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Enable UART 0. |
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Enable UART 1. |
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This option enables the CC32XX UART driver, for UART_0. |
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This option enables the UART driver for ARM CMSDK APB UART. |
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Enable this option to use one UART for console. Make sure CONFIG_UART_CONSOLE_ON_DEV_NAME is also set correctly. |
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This option allows a debug server agent such as GDB to take over the handling of traffic that goes through the console logic. The debug server looks at characters received and decides to handle them itself if they are some sort of control characters, or let the regular console code handle them if they are of no special significance to it. |
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Device driver initialization priority. Console has to be initialized after the UART driver it uses. |
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Debug |
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Error |
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Info |
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Off |
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Warning |
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Enables the UART console to receive mcumgr frames for image upgrade and device management. When enabled, the UART console does not process mcumgr frames, but it hands them up to a higher level module (e.g., the shell). If unset, incoming mcumgr frames are dropped. |
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This option specifies the name of UART device to be used for UART console. |
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This enables the API to send extra commands to drivers. This allows drivers to expose hardware specific functions. Says no if not sure. |
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Enable the ESP32 UART using ROM routines. |
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Enable the Gecko uart driver. |
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This option enables the UART driver for NXP i.MX7 family processors. |
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Enable support for UART1 port in the driver. Say y here if you want to use UART1 device. |
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Enable support for UART2 port in the driver. Say y here if you want to use UART2 device. |
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Enable support for UART3 port in the driver. Say y here if you want to use UART3 device. |
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Enable support for UART4 port in the driver. Say y here if you want to use UART4 device. |
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Enable support for UART5 port in the driver. Say y here if you want to use UART5 device. |
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Enable support for UART6 port in the driver. Say y here if you want to use UART6 device. |
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Enable support for UART7 port in the driver. Say y here if you want to use UART7 device. |
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This option enables interrupt support for UART allowing console input and other UART based drivers. |
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This enables the API for apps to control the serial line, such as baud rate, CTS and RTS. Implementation is up to individual driver. Says no if not sure. |
|
This option enables LiteUART serial driver. |
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Enable the mcumgr UART driver. This driver allows the application to communicate over UART using the mcumgr protocol for image upgrade and device management. The driver doesn’t inspect received data (as contrary to console UART driver) and all aspects of received protocol data are handled by an application provided callback. |
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This option specifies the name of UART device to be used for mcumgr UART. |
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Specifies the number of the mcumgr UART receive buffers. Receive buffers hold received mcumgr fragments prior to reassembly. This setting’s value must satisfy the following relation: UART_MCUMGR_RX_BUF_COUNT * UART_MCUMGR_RX_BUF_SIZE >= MCUMGR_SMP_UART_MTU |
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Specifies the size of the mcumgr UART receive buffer, in bytes. This value must be large enough to accommodate any line sent by an mcumgr client. |
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Enable the MCUX uart driver. |
|
Enable UART 0. |
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Enable UART 1. |
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Enable UART 2. |
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Enable UART 3. |
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Enable UART 4. |
|
Enable UART 5. |
|
Enable the MCUX USART driver. |
|
Enable USART 0. |
|
Enable the MCUX LPSCI driver. |
|
Enable UART 0. |
|
Enable the MCUX LPUART driver. |
|
Enable UART 0. |
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Enable UART 1. |
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Enable UART 2. |
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Enable UART 3. |
|
Enable UART 4. |
|
This option enables the Mi-V serial driver. |
|
This tells the driver to configure the UART port at boot, depending on the additional configuration options below. |
|
This option enables the MSP432P4XX UART driver, for UART_0. |
|
This enables a UART driver for the POSIX ARCH with up to 2 UARTs. For the first UART port, the driver can be configured to either connect to the terminal from which native_posix was run, or into one dedicated pseudoterminal for that UART. |
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Useful if you need to have another serial connection to host. This is used for example in PPP (Point-to-Point Protocol) implementation. |
|
This is the device name for UART, and is included in the device struct. |
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Enable support for nrfx UART drivers for nRF MCU series. Peripherals with the same instance ID cannot be used together, e.g. UART_0 and UARTE_0. |
|
This option enables the NS16550 serial driver. This driver can be used for the serial hardware available on x86 boards. |
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In some case, e.g. ARC HS Development kit, the peripheral space of ns 16550 (DesignWare UART) only allows word access, byte access will raise exception. |
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This enables the API for apps to send commands to driver. Says n if not sure. |
|
This enables the API for apps to control the serial line, such as CTS and RTS. Says n if not sure. |
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This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
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Options used for port initialization. |
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This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
Options used for port initialization. |
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This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
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Options used for port initialization. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
Options used for port initialization. |
|
This enables support for 64-bytes FIFO if UART controller is 16750. |
|
This enables the UART driver for the MetaWare nSim simulator. |
|
Enable pipe UART driver. This driver allows application to communicate over UART with custom defined protocol. Driver doesn’t inspect received data (as contrary to console UART driver) and all aspects of received protocol data are handled by application provided callback. |
|
This option specifies the name of UART device to be used for pipe UART. |
|
This option enables the UART driver for the PL011 |
|
Build the driver to utilize UART controller Port 0. |
|
When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to the UART driver. |
|
Build the driver to utilize UART controller Port 1. |
|
When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to the UART driver. |
|
This option enables the UART driver for PSoC6 family of processors. |
|
Enable support for UART_5 on port 5 in the driver. |
|
Enable support for UART_6 on port 12 in the driver. |
|
This option enables access RTT channel as UART device. |
|
Enable UART on (default) RTT channel 0. Default channel has to be configured in non-blocking skip mode. |
|
Enable UART on RTT channel 1 |
|
Size of the RTT down buffer for UART 1 reception. |
|
Size of the RTT up buffer for UART 1 transmission. |
|
Enable UART on RTT channel 2 |
|
Size of the RTT down buffer for UART 2 reception. |
|
Size of the RTT up buffer for UART 2 transmission. |
|
Enable UART on RTT channel 3 |
|
Size of the RTT down buffer for UART 3 reception. |
|
Size of the RTT up buffer for UART 3 transmission. |
|
Enable the RV32M1 LPUART driver. |
|
Enable UART 0. |
|
Enable UART 1. |
|
Enable UART 2. |
|
Enable UART 3. |
|
This option enables the UARTx driver for Atmel SAM MCUs. |
|
This option enables the SERCOMx USART driver for Atmel SAM0 MCUs. |
|
Enable UART0 at boot. |
|
Enable UART1 at boot. |
|
PA4 |
|
PA6 |
|
PD26 |
|
Enable UART2 at boot |
|
Enable UART3 at boot |
|
PD30 |
|
PD31 |
|
Enable UART4 at boot |
|
PD19 |
|
PD3 |
|
This option specifies the name of UART device to be used for the SHELL UART backend. |
|
This option enables the SiFive Freedom serial driver. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
Port 0 Interrupt Priority |
|
Port 0 RX Threshold at which the RX FIFO interrupt triggers. |
|
Port 0 TX Threshold at which the TX FIFO interrupt triggers. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
Port 1 Interrupt Priority |
|
Port 1 RX Threshold at which the RX FIFO interrupt triggers. |
|
Port 1 TX Threshold at which the TX FIFO interrupt triggers. |
|
This option enables the Stellaris serial driver. This specific driver can be used for the serial hardware available at the Texas Instrument LM3S6965 board. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
This option enables the UART driver for STM32 family of processors. Say y if you wish to use serial port on STM32 MCU. |
|
This option enables the UART driver for Xilinx MPSoC platforms. |
|
Builds Zephyr with Undefined Behavior Sanitizer enabled.
This is currently only supported by boards based on the posix
architecture, and requires a recent-ish compiler with the
|
|
UpdateHub is an enterprise-grade solution which makes simple to remotely update all your embedded devices in the field. It handles all aspects related to sending Firmware Over-the-Air (FOTA) updates with maximum security and efficiency, while you focus in adding value to your product. |
|
Allow the use of UpdateHub Community Server (updatehub-ce) as alternative to the updatehub.io enterprise server. |
|
Enables DTLS communication between the UpdateHub client and the server |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Set the interval that the UpdateHub update server will be polled. This time interval is zero and 43200 minutes(30 days). |
|
The product unique identifier is used when communicating with the UpdateHub server. |
|
This configuration is default, if need to use other address, must be set on the UpdateHub shell |
|
Activate shell module that provides UpdateHub commands like |
|
Configure the max number of supported hardware by the same image. |
|
This option enables the USARTx driver for Atmel SAM MCUs. |
|
Enable USART0 at boot |
|
Enable USART1 at boot |
|
Enable USART2 at boot |
|
Enable USB drivers. |
|
USB CDC ACM device class driver. Default device name is “CDC_ACM_0”. |
|
Number of instances of this USB Device class. |
|
Device name template for the CDC ACM Devices. First device would have name $(USB_CDC_ACM_DEVICE_NAME)_0, etc. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
USB CDC ACM ring buffer size |
|
Enable composite USB device driver. |
|
Kinetis and RT EHCI USB Device Controller Driver. |
|
SAM family USB HS device controller Driver. |
|
SAM0 family USB device controller Driver. |
|
Enable USB support on the STM32 F0, F1, F2, F3, F4, F7, L0, L4 and G4 family of processors. |
|
Say Y if your board uses USB DISCONNECT pin to enable the pull-up resistor on USB DP. |
|
USB Bluetooth device class driver |
|
Enable USB Binary Device Object Store (BOS) |
|
Stack should not handle ZLP for Variable-length Data Stage because it is taken over by the hardware. |
|
Enables USB Human Interface Device support. Default device name is “HID_0”. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
USB Loopback Function Driver |
|
USB device Manufacturer string. MUST be configured by vendor. |
|
Ethernet Control Model (ECM) is a part of Communications Device Class (CDC) USB protocol specified by USB-IF. |
|
MAC Host OS Address string. MAC Address which would be assigned to network device, created in the Host’s Operating System. Use RFC 7042 Documentation values as default MAC. |
|
Ethernet Emulation Model (EEM) is part of Communications Device Class (CDC) USB protocol and can be used to encapsulate Ethernet frames for transport over USB. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Remote NDIS (RNDIS) is commonly used Microsoft vendor protocol with Specification available from Microsoft web site. |
|
Enable MS OS Descriptors support |
|
USB device product ID. MUST be configured by vendor. |
|
USB device Product string. MUST be configured by vendor. |
|
This option requires USBD peripheral driver to also support remote wakeup. |
|
Placeholder for USB device Serial Number String. Serial Number String will be derived from Hardware Information Driver (HWINFO). |
|
Enable Start of Frame processing in events |
|
Enable USB device stack. |
|
USB device vendor ID. MUST be configured by vendor. |
|
USB DFU class driver |
|
Default value for bwPollTimeout (in ms) |
|
A thread can wait for a prescribed time (in ms) for DFU to begin |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Designware USB Device Controller Driver. |
|
Indicates whether or not USB specification version 2.0 is supported |
|
Sets bInterfaceSubClass to 1 and enables Set_Protocol and Get_Protocol requests handling. See Chapter 4.2 of Device Class Definition for Human Interface Devices 1.11 for more information. |
|
Number of instances of this USB Device class. |
|
Device name template for the HID Devices. First device would have name $(USB_HID_DEVICE_NAME)_0, etc. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Polling interval in ms selected by the USB HID Device. |
|
Sets bIntefaceProtocol in HID instance. 0 = None 1 = Keyboard 2 = Mouse See Chapter 4.3 of Device Class Definition for Human Interface Devices 1.11 for more information. |
|
Number of HID reports in the instance. Must be equal or higher than highest report ID (if they are not consecutive). |
|
Kinetis USB Device Controller Driver. |
|
USB Mass Storage device class driver |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Set bMaxPower value in the Standard Configuration Descriptor, the result is 2mA times the value provided. |
|
Native Posix USB Device Controller Driver. |
|
nRF USB Device Controller Driver |
|
Size of the driver’s internal event queue. Required size will depend on number of endpoints (class instances) in use. |
|
Size of the stack for the work queue thread that is used in the driver for handling the events from the USBD ISR, i.e. executing endpoint callbacks and providing proper notifications to the USB device stack. |
|
Number of endpoint write retries. |
|
Set buffer size for Standard, Class and Vendor request handlers |
|
Set Self-powered characteristic in bmAttributes to indicate self powered USB device. |
|
Enable this option to use the USB UART for console output. The output can be viewed from the USB host via /dev/ttyACM* port. Note that console inputs from the USB UART are not functional yet. Also since the USB layer currently doesn’t support multiple interfaces, this shouldn’t be selected in conjunction with, say, USB Mass Storage. |
|
Enable this option to use flow control on the console. The uart console waits until the DTR is asserted by the host. Note: Disabling this might lead to missing console prints. |
|
When enabled, threads may be created or dropped down to user mode, which has significantly restricted permissions and must interact with the kernel via system calls. See Zephyr documentation for more details about this feature. If a user thread overflows its stack, this will be caught and the kernel itself will be shielded from harm. Enabling this option may or may not catch stack overflows when the system is in privileged mode or handling a system call; to ensure these are always caught, enable CONFIG_HW_STACK_PROTECTION. |
|
When enabled, the application will be linked into the flash partition selected by the zephyr,code-partition property in /chosen in devicetree. When this is disabled, the flash load offset and size can be set manually below. |
|
Enable Segger J-Link RTT libraries for platforms that support it. Selection of this option enables use of RTT for various subsystems. Note that by enabling this option, RTT buffers consume more RAM. |
|
Enable STM32Cube Analog-to-Digital Converter (ADC) HAL module driver |
|
Enable STM32Cube Extended Analog-to-Digital Converter (ADC) HAL module driver |
|
Enable STM32Cube Controller Area Network (CAN) HAL module driver |
|
Enable STM32Cube HDMI-CEC controller (CEC) HAL module driver |
|
Enable STM32Cube Ultra Low Power Comparator channels (COMP) HAL module driver |
|
Enable STM32Cube CORTEX HAL module driver |
|
Enable STM32Cube Cyclic redundancy check calculation unit (CRC) HAL module driver |
|
Enable STM32Cube Extended Cyclic redundancy check calculation unit (CRC) HAL module driver |
|
Enable STM32Cube Cryptographic processor (CRYP) HAL module driver |
|
Enable STM32Cube Extended Cryptographic processor (CRYP) HAL module driver |
|
Enable STM32Cube Digital-to-analog converter (DAC) HAL module driver |
|
Enable STM32Cube Extended Digital-to-analog converter (DAC) HAL module driver |
|
Enable STM32Cube Digital camera interface (DCM) HAL module driver |
|
Enable STM32Cube Extended Digital camera interface (DCM) HAL module driver |
|
Enable STM32Cube Digital filter for sigma delta modulators (DFSDM) HAL module driver |
|
Enable STM32Cube Extended Digital filter for sigma delta modulators (DFSDM) HAL module driver |
|
Enable STM32Cube Direct Memory Access controller (DMA) HAL module driver |
|
Enable STM32Cube Chrom-Art Accelerator™ controller (DMA2D) HAL module driver |
|
Enable STM32Cube Extended Direct Memory Access controller (DMA) HAL module driver |
|
Enable STM32Cube Display Serial Interface Host (DSI) HAL module driver |
|
Enable STM32Cube Ethernet (ETH) HAL module driver |
|
Enable STM32Cube Extended interrupt and event controller (EXTI) HAL module driver |
|
Enable STM32Cube Controller area network with flexible data rate (FDCAN) HAL module driver |
|
Enable STM32Cube Firewall HAL module driver |
|
Enable STM32Cube Embedded Flash Memory (FLASH) HAL module driver |
|
Enable STM32Cube Extended Embedded Flash Memory (FLASH) HAL module driver |
|
Enable STM32Cube Embedded Flash Memory RAM functions (FLASH_RAMFUNC) HAL module driver |
|
Enable STM32Cube Fast-mode Plus Inter-integrated circuit (FMPI2C) HAL module driver |
|
Enable STM32Cube Extended Fast-mode Plus Inter-integrated circuit (FMPI2C) HAL module driver |
|
Enable STM32Cube Chrom-GRCTM (GFXMMU) HAL module driver |
|
Enable STM32Cube General-purpose I/Os (GPIO) HAL module driver |
|
Enable STM32Cube Extended General-purpose I/Os (GPIO) HAL module driver |
|
Enable STM32Cube Hash processor (HASH) HAL module driver |
|
Enable STM32Cube Extended Hash processor (HASH) HAL module driver |
|
Enable STM32Cube Host Controller device (HCD) HAL module driver |
|
Enable STM32Cube High-Resolution Timer (HRTIM) HAL module driver |
|
Enable STM32Cube Hardware Semaphore (HSEM) HAL module driver |
|
Enable STM32Cube Inter-integrated circuit (I2C) interface HAL module driver |
|
Enable STM32Cube Extended Inter-integrated circuit (I2C) interface HAL module driver |
|
Enable STM32Cube Inter-IC sound (I2S) HAL module driver |
|
Enable STM32Cube Etxended Inter-IC sound (I2S) HAL module driver |
|
Enable STM32Cube Inter-Processor communication controller (IPCC) HAL module driver |
|
Enable STM32Cube Infrared Data Association (IRDA) HAL module driver |
|
Enable STM32Cube Independent watchdog (IWDG) HAL module driver |
|
Enable STM32Cube Jpeg codec (JPEG) HAL module driver |
|
Enable STM32Cube LCD controller (LCD) HAL module driver |
|
Enable STM32Cube Low Power Timer (LPTIM) HAL module driver |
|
Enable STM32Cube LCD-TFT controller (LTDC) HAL module driver |
|
Enable STM32Cube Extended LCD-TFT controller (LTDC) HAL module driver |
|
Enable STM32Cube Management data input/output (MDIOS) HAL module driver |
|
Enable STM32Cube Master Direct Memory Access controller (MDMA) HAL module driver |
|
Enable STM32Cube MultiMediaCard interface (SDMMC) HAL module driver |
|
Enable STM32Cube Extended MultiMediaCard interface (SDMMC) HAL module driver |
|
Enable STM32Cube NAND Controller (NAND) HAL module driver |
|
Enable STM32Cube NOR Controller (NOR) HAL module driver |
|
Enable STM32Cube Operational amplifiers (OPAMP) HAL module driver |
|
Enable STM32Cube Extended Operational amplifiers (OPAMP) HAL module driver |
|
Enable STM32Cube Octo-SPI interface (OSPI) HAL module driver |
|
Enable STM32Cube PCCard memories (PCCARD) HAL module driver |
|
Enable STM32Cube USB Peripheral Controller (PCD) HAL module driver |
|
Enable STM32Cube Extended USB Peripheral Controller (PCD) HAL module driver |
|
Enable STM32Cube Power control (PWR) HAL module driver |
|
Enable STM32Cube Extended Power control (PWR) HAL module driver |
|
Enable STM32Cube Quad-SPI interface (QSPI) HAL module driver |
|
Enable STM32Cube RAM ECC monitoring (RAMECC) HAL module driver |
|
Enable STM32Cube Reset and Clock Control (RCC) HAL module driver |
|
Enable STM32Cube Extended Reset and Clock Control (RCC) HAL module driver |
|
Enable STM32Cube True random number generator (RNG) HAL module driver |
|
Enable STM32Cube Real-time clock (RTC) HAL module driver |
|
Enable STM32Cube Extended Real-time clock (RTC) HAL module driver |
|
Enable STM32Cube Serial audio interface (SAI) HAL module driver |
|
Enable STM32Cube Extended Serial audio interface (SAI) HAL module driver |
|
Enable STM32Cube Secure digital input/output MultiMediaCard interface (SDMMC) HAL module driver |
|
Enable STM32Cube SDADC HAL module driver |
|
Enable STM32Cube SDRAM controller (SDRAM) HAL module driver |
|
Enable STM32Cube Extended Secure digital input/output MultiMediaCard interface (SDMMC) HAL module driver |
|
Enable STM32Cube Smartcard controller (SMARTCARD) HAL module driver |
|
Enable STM32Cube Extended Smartcard controller (SMARTCARD) HAL module driver |
|
Enable STM32Cube System Management Bus (SMBus) HAL module driver |
|
Enable STM32Cube SPDIF receiver interface (SPDIFRX) HAL module driver |
|
Enable STM32Cube Serial peripheral interface (SPI) HAL module driver |
|
Enable STM32Cube Extended Serial peripheral interface (SPI) HAL module driver |
|
Enable STM32Cube SRAM controller (SRAM) HAL module driver |
|
Enable STM32Cube Single Wire Protocol Master Interface (SWPMI) HAL module |
|
Enable STM32Cube Timer (TIM) HAL module driver |
|
Enable STM32Cube Extended Timer (TIM) HAL module driver |
|
Enable STM32Cube Touch sensing controller (TSC) HAL module driver |
|
Enable STM32Cube Universal asynchronous receiver transmitter (USART) HAL module driver |
|
Enable STM32Cube Extended Universal asynchronous receiver transmitter (USART) HAL module driver |
|
Enable STM32Cube Universal synchronous asynchronous receiver transmitter (USART) HAL module driver |
|
Enable STM32Cube Extended Universal synchronous asynchronous receiver transmitter (USART) HAL module driver |
|
Enable STM32Cube System window watchdog (WWDG) HAL module driver |
|
Enable STM32Cube Analog-to-Digital Converter (ADC) LL module driver |
|
Enable STM32Cube Basic direct memory access controller (BDMA) LL module driver |
|
Enable STM32Cube Ultra Low Power Comparator channels (COMP) LL module driver |
|
Enable STM32Cube Cyclic redundancy check calculation unit (CRC) LL module driver |
|
Enable STM32Cube Clock recovery system (CRS) LL module driver |
|
Enable STM32Cube Digital-to-analog converter (DAC) LL module driver |
|
Enable STM32Cube DelayBlock (DELAYBLOCK) LL module driver |
|
Enable STM32Cube Direct Memory Access controller (DMA) LL module driver |
|
Enable STM32Cube Chrom-Art Accelerator™ controller (DMA2D) LL module driver |
|
Enable STM32Cube Extended interrupt and event controller (EXTI) LL module driver |
|
Enable STM32Cube Flexible memory controller (FMC) LL module driver |
|
Enable STM32Cube Flexible static memory controller (FSMC) LL module driver |
|
Enable STM32Cube Extended General-purpose I/Os (GPIO) LL module driver |
|
Enable STM32Cube High-Resolution Timer (HRTIM) LL module driver |
|
Enable STM32Cube Inter-integrated circuit (I2C) interface LL module driver |
|
Enable STM32Cube Inter-Processor communication controller (IPCC) LL module driver |
|
Enable STM32Cube Low Power Timer (LPTIM) LL module driver |
|
Enable STM32Cube Low-power universal asynchronous receiver transmitter (LPUART) LL module driver |
|
Enable STM32Cube Master Direct Memory Access controller (MDMA) LL module driver |
|
Enable STM32Cube Operational amplifiers (OPAMP) LL module driver |
|
Enable STM32Cube Power control (PWR) LL module driver |
|
Enable STM32Cube Reset and Clock Control (RCC) LL module driver |
|
Enable STM32Cube True random number generator (RNG) LL module driver |
|
Enable STM32Cube Real-time clock (RTC) LL module driver |
|
Enable STM32Cube SD/SDIO/MMC card host interface (SDMMC) LL module driver |
|
Enable STM32Cube Serial peripheral interface (SPI) LL module driver |
|
Enable STM32Cube Single Wire Protocol Master Interface (SWPMI) LL module driver |
|
Enable STM32Cube Timer (TIM) LL module driver |
|
Enable STM32Cube Universal synchronous asynchronous receiver transmitter (USART) LL module driver |
|
Enable STM32Cube Universal serial bus full-speed device interface (USB) LL module driver |
|
Enable STM32Cube Utility functions (UTILS) LL module driver |
|
The _arch_switch() API is a lower level context switching primitive than the original arch_swap mechanism. It is required for an SMP-aware scheduler, or if the architecture does not provide arch_swap. In uniprocess situations where the architecture provides both, _arch_switch incurs more somewhat overhead and may be slower. |
|
Indicates whether _arch_switch() API is supported by the currently enabled platform. This option should be selected by platforms that implement it. |
|
RV32M1 VEGA SDK support |
|
IRQ implementation for LiteX VexRiscv |
|
Enable support for the VIDEO. |
|
Alignment of the video pool’s buffer |
|
Number of maximum sized buffer in the video pool |
|
Size of the largest buffer in the video pool |
|
NXP MCUX CMOS Sensor Interface (CSI) driver |
|
Enable driver for MT9M114 CMOS digital image sensor device. |
|
Enable video pattern generator (for testing purposes). |
|
Enable driver for VL53L0X I2C-based time of flight sensor. |
|
Threshold used for proximity detection when sensor is used with SENSOR_CHAN_PROX. |
|
When selected, the wait_q will be implemented with a doubly-linked list. Choose this if you expect to have only a few threads blocked on any single IPC primitive. |
|
When selected, the wait_q will be implemented with a balanced tree. Choose this if you expect to have many threads waiting on individual primitives. There is a ~2kb code size increase over WAITQ_DUMB (which may be shared with SCHED_SCALABLE) if the rbtree is not used elsewhere in the application, and pend/unpend operations on “small” queues will be somewhat slower (though this is not generally a performance path). |
|
Include support for watchdogs. |
|
Enable CMSDK APB Watchdog (WDOG_CMSDK_APB) Driver for ARM family of MCUs. |
|
Enable this setting to allow WDOG to be automatically started during device initialization. Note that once WDOG is started it must be reloaded before the counter reaches 0, otherwise the MCU will be reset. |
|
Keep the watchdog timer enabled at boot with the internal 128kHz LPO clock (and a prescaler of 256) as clock source. The application can take over control of the watchdog timer after boot and install a different timeout, if needed. |
|
This processor enables the watchdog timer with a short window for configuration upon reset. Therefore, this requires that the watchdog be configured during reset handling. |
|
Initial timeout value for the watchdog timer in milliseconds. |
|
Set the IRQ line used by the WDT device. Very few lines can be chosen here, as it must be a level 4 interrupt. |
|
Set the IRQ line used by the WDT device. Very few lines can be chosen here, as it must be a level 4 interrupt. |
|
Disable watchdog at Zephyr system startup. |
|
Enable WDT driver for ESP32. |
|
Enable WDOG driver for Silicon Labs Gecko MCUs. |
|
Debug |
|
Error |
|
Info |
|
Off |
|
Warning |
|
Enable the mcux wdog driver. |
|
Enable the mcux wdog32 driver. |
|
Enable multistage operation of watchdog timeouts. |
|
Enable support for nrfx WDT driver for nRF MCU series. |
|
Enable WDT driver for Atmel SAM MCUs. |
|
Enable WDT driver for Atmel SAM0 MCUs. |
|
Enable WDT driver for Microchip XEC MCU series. |
|
Enable Websocket client library. |
|
How many Websockets can be created in the system. |
|
add support for Wi-Fi Drivers |
|
Inventek eS-WiFi support |
|
Driver name |
|
This option sets the priority of the esWiFi threads. Do not touch it unless you know what you are doing. |
|
Wi-Fi device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
|
Write to log with NET_DBG or LOG_DBG in addition to previous levels. |
|
Use default log level. |
|
Only write to log when NET_ERR or LOG_ERR is used. |
|
Write to log with NET_INFO or LOG_INF in addition to previous levels. |
|
Do not write to log. |
|
Write to log with NET_WARN or LOG_WRN in addition to previous level. |
|
Enable support for Full-MAC Wi-Fi devices. |
|
SimpleLink Wi-Fi driver support |
|
SimpleLink uses the “FastConnect” feature to reconnect to the previously connected AP on startup. Should the Wi-Fi connection timeout, the SimpleLink driver will fail to initialize, and LOG an error. |
|
Set the maximum size of a network packet going through the chip. This sets the size of each buffer, in each buffer pool. Do not modify it unless you know what you are doing. |
|
The number of times, separated by a one second interval, to retry a request for the network list. |
|
Driver name |
|
The number of results to request on a Wi-Fi scan operation. Actual number returned may be less. Maximum is 30. |
|
WINC1500 driver support |
|
Set the number of buffer the driver will have access to in each of its buffer pools. |
|
This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic. |
|
Set the maximum size of a network packet going through the chip. This sets the size of each buffer, in each buffer pools. Do not modify it unless you know what you are doing. |
|
Driver name |
|
Set the number of sockets that can be managed through the driver and the chip. |
|
Region Asia |
|
Region Europe |
|
Region North America |
|
This option sets the priority of the thread handling WINC1500 HAL callbacks. Do not touch it unless you know what you are doing. |
|
This option sets the size of the stack used by the thread handling WINC1500 HAL callbacks. Do not touch it unless you know what you are doing. |
|
Enable LED strip driver for daisy chains of WS2812-ish (or WS2812B, WS2813, SK6812, or compatible) devices. |
|
The GPIO driver does bit-banging with inline assembly, and is not available on all SoCs. |
|
The SPI driver is portable, but requires significantly more memory (1 byte of overhead per bit of pixel data). |
|
Enable WWDG driver for STM32 line of MCUs |
|
If your local APIC supports x2APIC mode, turn this on. |
|
x86 architecture |
|
Run in 64-bit mode |
|
Hidden config to select arch-independent option to enable Spectre V1 mitigations by default if the CPU is not known to be immune to it. |
|
Installing interrupt handlers with irq_connect_dynamic() requires some stub code to be generated at build time, one stub per dynamic interrupt. |
|
This hidden option enables defining a Task State Segment (TSS) for kernel execution. This is needed to handle double-faults or do privilege elevation. It also defines a special TSS and handler for correctly handling double-fault exceptions, instead of just letting the system triple-fault and reset. |
|
Internal config to enable runtime stack traces on fatal exceptions. |
|
Implements kernel page table isolation to mitigate Meltdown exploits to read Kernel RAM. Incurs a significant performance cost for user thread interrupts and system calls, and significant footprint increase for additional page tables and trampoline stacks. |
|
Maximum number of memory regions to hold in the memory map. |
|
This options enables the memory management unit present in x86 and creates a set of page tables at boot time that is runtime- mutable. |
|
Building page tables at boot requires a pool of free memory pages to construct it. This can’t be derived at build time, tune this to your SoC’s specific memory map. |
|
This hidden option should be set on a per-SOC basis to indicate that a particular SOC is not vulnerable to the Lazy FP CPU vulnerability, as described in CVE-2018-3665. |
|
This hidden option should be set on a per-SOC basis to indicate that a particular SOC is not vulnerable to the Meltdown CPU vulnerability, as described in CVE-2017-5754. |
|
This hidden option should be set on a per-SOC basis to indicate that a particular SOC is not vulnerable to the Spectre V1, V1.1, V1.2, and swapgs CPU vulnerabilities as described in CVE-2017-5753, CVE-2018-3693, and CVE-2019-1125. |
|
This hidden option should be set on a per-SOC basis to indicate that a particular SOC is not vulnerable to the Spectre V2 CPU vulnerability, as described in CVE-2017-5715. |
|
This hidden option should be set on a per-SOC basis to indicate that a particular SOC is not vulnerable to the Spectre V4 CPU vulnerability, as described in CVE-2018-3639. |
|
This hidden option should be set on a per-SOC basis to indicate that a particular SOC does not perform any kind of speculative execution, or is a newer chip which is immune to the class of vulnerabilities which exploit speculative execution side channel attacks. |
|
This option leverages the MMU to cause a system fatal error if the bounds of the current process stack are overflowed. This is done by preceding all stack areas with a 4K guard page. |
|
This options enables number generator based on timestamp counter of x86 boards, obtained with rdtsc instruction. |
|
This option enables APIs to drop a thread’s privileges down to ring 3, supporting user-level threads that are protected from each other and from crashing the kernel. |
|
Non-emulated X86 devices often require special hardware to attach a debugger, which may not be easily available. This option adds a very minimal serial driver which gets initialized at the very beginning of z_cstart(), via arch_kernel_init(). This driver enables printk to emit messages to the 16550 UART port 0 instance in device tree. This mini-driver assumes I/O to the UART is done via ports. |
|
This option allows the kernel to operate with its text and read-only sections residing in ROM (or similar read-only memory). Not all boards support this option so it must be used with care; you must also supply a linker command file when building your image. Enabling this option increases both the code and data footprint of the image. |
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This module implements a kernel device driver for the Xilinx ZynqMP platform provides the standard “system clock driver” interfaces. If unchecked, no timer will be used. |
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This is the index of TTC timer picked to provide system clock. |
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Enables the Xoroshiro128+ pseudo-random number generator, that uses the entropy driver as a seed source. This is a fast non-cryptographically secure random number generator. It is so named because it uses 128 bits of state. |
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Xtensa architecture |
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Device driver initialization priority. |
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Build the Xtensa HAL module during build process. This is selected by the Xtensa ARCH kconfig automatically. |
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Specify which special register to store the pointer to _kernel.cpus[] for the current CPU. |
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Uncheck this if you core does not implement “SCOMPARE1” register and “s32c1i” instruction. |
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This option controls whether the initial reset vector code is built. This is always needed for the simulator. Real boards may already implement this in boot ROM. |
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Use simulator console to print messages. |
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Enables a system timer driver for Xtensa based on the CCOUNT and CCOMPARE special registers. |
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Index of the CCOMPARE register (and associated interrupt) used for the system timer. Xtensa CPUs have hard-configured interrupt priorities associated with each timer, and some of them can be unmaskable (and thus not usable by OS code that need synchronization, like the timer subsystem!). Choose carefully. Generally you want the timer with the highest priority maskable interrupt. |
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SoC or boards might define their own __start by setting this setting to false. |
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The kernel may reserve some of the highest interrupts priorities in the system for its own use. These interrupts will not be masked by interrupt locking. When connecting interrupts the kernel will offset all interrupts to lower priority than those reserved by the kernel. Zero-latency interrupt can be used to set up an interrupt at the highest interrupt priority which will not be blocked by interrupt locking. Since Zero-latency ISRs will run in the same priority or possibly at higher priority than the rest of the kernel they cannot use any kernel functionality. |
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Enable the Zephyr testing framework. You should enable this only if you’re writing automated tests. |
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Set verbosity level for assertions. Assertion verbosity levels: 0 Write only file and line for failed assertions 1 Write file, line number, function and reason for failed assertions 2 Log also successful assertions |
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Stop and abort on first failing test. Do not continue with other tests that might be in the queue. |
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Enable mocking support for Ztest. This allows the test to set return values and expected parameters to functions. |
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Maximum amount of concurrent return values / expected parameters. |
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If the test passed reset the board so it is run again. This may be used as an alternative to manual resets when attempting to reproduce an intermittent failure. |
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Test function thread stack size |
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Enable overriding defines in tc_util.h. If True the user should provide tc_util_user_override.h in Zephyr’s include path, e.g. by adding zephyr_include_directories(project PRIVATE my_folder) to a project’s CMakeLists.txt. The override header may now #define the various macros and strings in tc_util.h which are surrounded by #ifndef … #endif blocks. |
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Set priority of the testing thread. Default is -1 (cooperative). |