Driver Configuration Options¶
Kconfig files describe build-time configuration options (called symbols
in Kconfig-speak), how they’re grouped into menus and sub-menus, and
dependencies between them that determine what configurations are valid.
Kconfig files appear throughout the directory tree. For example,
subsys/power/Kconfig defines power-related options.
This documentation is generated automatically from the Kconfig files by
the genrest.py script. Click on symbols for more
information.
Configuration Options¶
Symbol name |
Help/prompt |
|---|---|
Second level interrupts are used to increase the number of addressable interrupts in a system. |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the offset in _sw_isr_table, the generated ISR handler table, where storage for 2nd level interrupt ISRs begins. This is typically allocated after ISRs for level 1 interrupts. |
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Third level interrupts are used to increase the number of addressable interrupts in a system. |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the offset in _sw_isr_table, the generated ISR handler table, where storage for 3rd level interrupt ISRs begins. This is typically allocated after ISRs for level 2 interrupts. |
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Enable ADC (Analog to Digital Converter) driver configuration. |
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Enable ADC 0 |
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Enable ADC 1 |
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Enable ADC 2 |
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This option enables the asynchronous API calls. |
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Enable LMP90xxx ADC driver. The LMP90xxx is a multi-channel, low power sensor analog frontend (AFE). |
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Priority level for the internal ADC data acquisition thread. |
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Size of the stack used for the internal data acquisition thread. |
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Use Cyclic Redundancy Check (CRC) to verify the integrity of the data read from the LMP90xxx. |
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Enable GPIO child device support in the LMP90xxx ADC driver. The GPIO functionality is handled by the LMP90xxx GPIO driver. |
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LMP90xxx ADC device driver initialization priority. |
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Enable the MCUX ADC12 driver. |
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Enable the MCUX ADC16 driver. |
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Divide ratio is 1 |
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Divide ratio is 2 |
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Divide ratio is 4 |
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Divide ratio is 8 |
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Alternate reference pair |
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Default voltage reference pair V_REFH and V_REFL |
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Enable support for nrfx ADC driver for nRF51 MCU series. |
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Number of ADC channels to be supported by the driver. Each channel needs a dedicated structure in RAM that stores the ADC settings to be used when sampling this channel. |
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Enable support for nrfx SAADC driver for nRF52 MCU series. |
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Enable Atmel SAM0 MCU Family Analog-to-Digital Converter (ADC) driver. |
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Enable Atmel SAM MCU Family Analog-to-Digital Converter (ADC) driver based on AFEC module. |
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Enable ADC Shell for testing. |
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Enable the driver implementation for the stm32xx ADC |
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Enable ADC driver for Microchip XEC MCU series. |
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Enable the driver for Analog Devices ADT7420 High-Accuracy 16-bit Digital I2C Temperature Sensors. |
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The critical overtemperature pin asserts when the temperature exceeds this value. The default value of 147 is the reset default of the ADT7420. |
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Specify the temperature hysteresis in °C for the THIGH, TLOW, and TCRIT temperature limits. |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable driver for ADXL362 Three-Axis Digital Accelerometers. |
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Unsigned value that sets the ADXL362 interrupt mode in either absolute or referenced mode. 0 - Absolute mode 1 - Referenced mode |
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100 Hz |
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12.5 Hz |
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200 Hz |
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25 Hz |
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400 Hz |
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50 Hz |
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Set at runtime. |
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2G |
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4G |
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8G |
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Set at runtime. |
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Unsigned value that the adxl362 samples are compared to in activity trigger mode. |
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Unsigned value that the adxl362 samples are compared to in inactivity trigger mode. |
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Unsigned value that sets the ADXL362 in different interrupt modes. 0 - Default mode 1 - Linked mode 3 - Loop mode |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable driver for ADXL372 Three-Axis Digital Accelerometers. |
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Threshold for activity detection. |
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The activity timer implements a robust activity detection that minimizes false positive motion triggers. When the timer is used, only sustained motion can trigger activity detection. Number of multiples of 3.3 ms activity timer for which above threshold acceleration is required to detect activity. It is 3.3 ms per code for 6400 Hz ODR, and it is 6.6 ms per code for 3200 Hz ODR and below. |
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1600 Hz |
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200 Hz |
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3200 Hz |
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400 Hz |
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800 Hz |
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ODR/210 |
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ODR/411 |
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ODR/812 |
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ODR/1616 |
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Disabled |
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I2C Interface |
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Threshold for in-activity detection. |
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The time that all enabled axes must be lower than the inactivity threshold for an inactivity event to be detected. Number of multiples of 26 ms inactivity timer for which below threshold acceleration is required to detect inactivity. It is 26 ms per code for 3200 Hz ODR and below, and it is 13 ms per code for 6400 Hz ODR. |
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Disabled |
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In this mode, acceleration data is provided continuously at the output data rate (ODR). |
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1600 Hz |
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3200 Hz |
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400 Hz |
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6400 Hz |
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800 Hz |
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In most high-g applications, a single (3-axis) acceleration sample at the peak of an impact event contains sufficient information about the event, and the full acceleration history is not required. In this mode the device returns only the over threshold Peak Acceleration between two consecutive sample fetches. |
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Activity detection can be configured as referenced or absolute. When using absolute activity detection, acceleration samples are compared directly to a user set threshold to determine whether motion is present. In many applications, it is advantageous for activity detection to be based not on an absolute threshold, but on a deviation from a reference point or orientation. |
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SPI Interface |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable driver for AK8975 magnetometer. |
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I2C address of the AK8975 sensor. Choose:
If the AK8975 sensor is part of a MPU9159 chip, the I2C address needs to be 0x0C. |
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Specify the device name of the I2C master device to which the AK8975 chip is connected. |
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Device name with which the AK8975 sensor is identified. |
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This module implements a kernel device driver for the Altera Avalon Interval Timer as described in the Embedded IP documentation, for use with Nios II and possibly other Altera soft CPUs. It provides the standard “system clock driver” interfaces. |
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Enable driver for AMG88XX infrared thermopile sensor. |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable driver for iAQ-core Digital VOC sensor. |
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Enable the LED strip driver for a chain of APA102 RGB LEDs. These are sold as DotStar by Adafruit and Superled by others. |
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Enable driver for APDS9960 sensors. |
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16x |
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1x |
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4x |
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64x |
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Enable Ambient Light Sense (ALS). |
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1x |
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2x |
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4x |
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8x |
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100% |
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150% |
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200% |
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300% |
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Proximity Pulse Count |
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16us |
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32us |
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4us |
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8us |
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Use global thread |
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No trigger |
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Use the “new” local APIC timer driver for the system timer. This is a replacement for the legacy local APIC timer driver which supports tickless operation, but not the Quark MVIC. |
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This option specifies the IRQ used by the local APIC timer. |
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This option specifies the IRQ priority used by the local APIC timer. |
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If your CPU supports invariant TSC, and you know the ratio of the TSC frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC (the local APIC timer frequency), then enable this for a much faster and more accurate z_timer_cycle_get_32(). |
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TSC to local APIC timer frequency divisor (M) |
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TSC to local APIC timer frequency multiplier (N) |
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The ARCv2 interrupt unit has 16 allocated exceptions associated with vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255. The interrupt unit is optional in the ARCv2-based processors. When building a processor, you can configure the processor to include an interrupt unit. The ARCv2 interrupt unit is highly programmable. |
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This module implements a kernel device driver for the ARCv2 processor timer 0 and provides the standard “system clock driver” interfaces. |
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This option specifies the IRQ priority used by the ARC timer. Lower values have higher priority. |
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This module implements a kernel device driver for the ARM architected timer which provides per-cpu timers attached to a GIC to deliver its per-processor interrupts via PPIs. |
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Configure Clock Config Device name |
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Enable support for Audio |
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Enable Audio Codec Driver Configuration |
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Audio codec device driver initialization priority. |
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Enable Digital Microphone Driver Configuration |
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Audio Digital Microphone device driver initialization priority. |
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Enable Intel digital PDM microphone driver |
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Enable MPXXDTYY microphone support on the selected board |
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Enable TLV320DAC support on the selected board |
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Enable driver for BMA280 I2C-based triaxial accelerometer sensor family. |
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7.81Hz |
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15.63HZ |
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31.25Hz |
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62.5Hz |
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125Hz |
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250HZ |
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500Hz |
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unfiltered |
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+/-16g |
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+/-2g |
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+/-4g |
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+/-8g |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable driver for BMC150 I2C-based magnetometer sensor. |
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Enhanced regular (15, 27, 10) |
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High accuracy (47, 83, 20) |
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Low power (3, 3, 10) |
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Regular (9, 15, 10) |
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Enable alteration of sampling rate attribute at runtime. |
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Enable alteration of XY oversampling at runtime. |
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Enable alteration of Z oversampling at runtime. |
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Enable triggers for BMC150 magnetometer |
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Enable data ready interrupt for BMC150 magnetometer |
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Specify the internal thread stack size. |
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Enable driver for BME280 I2C-based or SPI-based temperature and pressure sensor. |
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16 |
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2 |
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4 |
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8 |
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filter off |
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x16 |
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x1 |
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x2 |
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x4 |
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x8 |
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x16 |
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x1 |
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x2 |
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x4 |
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x8 |
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0.5ms |
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1000ms |
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125ms |
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2000ms BMP280 / 10ms BME280 |
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250ms |
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4000ms BMP280 / 20ms BME280 |
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500ms |
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62.5ms |
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x16 |
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x1 |
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x2 |
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x4 |
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x8 |
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Enable driver for BME680 I2C-based based temperature, pressure, humidity and gas sensor. |
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128 |
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16 |
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2 |
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32 |
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4 |
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64 |
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8 |
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filter off |
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197 |
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1943 |
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320 |
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400 |
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x16 |
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x1 |
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x2 |
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x4 |
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x8 |
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x16 |
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x1 |
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x2 |
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x4 |
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x8 |
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x16 |
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x1 |
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x2 |
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x4 |
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x8 |
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Enable Bosch BMG160 gyroscope support. |
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Fast bus speed of up to 400KHz. |
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Standard bus speed of up to 100kHz. |
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100 Hz |
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1000 Hz |
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200 Hz |
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2000 Hz |
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400 Hz |
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Set at runtime. |
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1000 DPS |
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125 DPS |
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2000 DPS |
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250 DPS |
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500 DPS |
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Set at runtime. |
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The priority of the thread used for handling interrupts. |
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The thread stack size. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable Bosch BMI160 inertial measurement unit that provides acceleration and angular rate measurements. |
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100 Hz |
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1600 Hz |
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200 Hz |
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25 Hz |
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1.56 Hz |
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12.5 Hz |
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0.78 Hz |
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6.25 Hz |
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3.125 Hz |
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400 Hz |
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50 Hz |
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800 Hz |
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Set at runtime. |
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low power |
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normal |
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Set at runtime. |
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suspended/not used |
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16G |
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2G |
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4G |
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8G |
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Set at runtime. |
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100 Hz |
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1600 Hz |
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200 Hz |
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25 Hz |
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3200 Hz |
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400 Hz |
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50 Hz |
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800 Hz |
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Set at runtime. |
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fast start-up |
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normal |
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Set at runtime. |
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suspended/not used |
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1000 DPS |
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125 DPS |
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2000 DPS |
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250 DPS |
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500 DPS |
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Set at runtime. |
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The priority of the thread used for handling interrupts. |
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The thread stack size. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable driver for BMM150 I2C-based Geomagnetic sensor. |
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Enhanced regular (15, 27, 10) |
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High accuracy (47, 83, 20) |
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Low power (3, 3, 10) |
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Regular (9, 15, 10) |
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Enable alteration of sampling rate attribute at runtime. |
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Enable alteration of XY oversampling at runtime. |
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Enable alteration of Z oversampling at runtime. |
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Enable support for devices compatible with the BlueNRG Bluetooth Stack. Current driver supports: ST BLUENRG-MS. |
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Bluetooth H:4 UART driver. Requires hardware flow control lines to be available. |
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Bluetooth three-wire (H:5) UART driver. Implementation of HCI Three-Wire UART Transport Layer. |
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This is intended for unit tests where no internal driver should be selected. |
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Bluetooth HCI driver for communication with another CPU using RPMsg framework. |
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Enable RPMsg configuration for nRF53. Two channels of the IPM driver are used in the HCI driver: channel 0 for TX and channel 1 for RX. |
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RPMsg RX thread priority |
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RPMsg stack size for RX thread |
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Supports Bluetooth ICs using SPI as the communication protocol. HCI packets are sent and received as single Byte transfers, prepended after a known header. Headers may vary per device, so additional platform specific knowledge may need to be added as devices are. |
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Enable support for devices compatible with the BlueNRG Bluetooth Stack. Current driver supports: ST BLUENRG-MS. |
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TODO |
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This option specifies the name of UART device to be used for Bluetooth. |
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This driver provides access to the local Linux host’s Bluetooth adapter using a User Channel HCI socket to the Linux kernel. It is only intended to be used with the native POSIX build of Zephyr. The Bluetooth adapter must be powered off in order for Zephyr to be able to use it. |
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Enable CAN Driver Configuration |
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Enable CAN controller 0 |
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Enable CAN controller 1 |
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Enable CAN controller 2 on the STM32F4 series of processors. (Tested on the STM32F4 series, may also work on F7, F1, F2 and L4) |
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This option enables the automatic bus-off recovery according to ISO 11898-1 (recovery after 128 occurrences of 11 consecutive recessive bits). When this option is enabled, the recovery API is not available. |
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CAN device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
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This is a dummy driver that can only loopback messages. |
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“Device name for the loopback device” |
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Defines the array size of the callback/msgq pointers. Must be at least the size of concurrent reads. |
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Enable MCP2515 CAN Driver |
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MCP2515 driver initialization priority, must be higher than SPI. |
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Priority level of the internal thread which is ran for interrupt handling and incoming packets. |
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Size of the stack used for internal thread which is ran for interrupt handling and incoming packets. |
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Defines the array size of the callback/msgq pointers. Must be at least the size of concurrent reads. |
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Enable support for mcux flexcan driver. |
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Enable IPv6 Networking over can (6loCAN) |
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CAN NET device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
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Name of the network device driver for IPv6 over CAN. |
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This option enables a timestamp value of the CAN free running timer. The value is incremented every bit time and starts when the controller is initialized. |
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Enable CAN Shell for testing. |
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Enable STM32 CAN Driver. Tested on stm32F0, stm32L4 and stm32F7 series. |
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Number of frames in the buffer of a zcan_work. |
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These are 4 in number supporting a max of 32 interrupts each. |
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CAVS 0 Driver name |
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Parent interrupt number to which CAVS_0 maps |
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CAVS 1 Driver name |
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Parent interrupt number to which CAVS_1 maps |
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CAVS 2 Driver name |
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Parent interrupt number to which CAVS_2 maps |
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CAVS 3 Driver name |
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Parent interrupt number to which CAVS_3 maps |
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Cavs Interrupt Logic initialization priority. |
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This indicates the offset in the SW_ISR_TABLE beginning from where the ISRs for CAVS Interrupt Controller are assigned. |
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This module implements a kernel device driver for the TI SimpleLink CC13X2_CC26X2 series Real Time Counter and provides the standard “system clock driver” interfaces. |
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Enable driver for CCS811 Gas sensors. |
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Measurements disabled |
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Measurement every second |
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Measurement every ten seconds |
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Measurement every sixty seconds |
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Measurement every 250 milliseconds |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable support for hardware clock controller. Such hardware can provide clock for other subsystem, and thus can be also used for power efficiency by controlling their clock. Note that this has nothing to do with RTC. |
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Enable driver for Reset & Clock Control subsystem found in STM32F4 family of MCUs |
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This option controls the priority of clock control device initialization. Higher priority ensures that the device is initialized earlier in the startup cycle. If unsure, leave at default value 1 |
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Enable PLL on Beetle. Select n if not sure. |
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Enable support for mcux ccm driver. |
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Enable support for mcux mcg driver. |
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Enable support for MCUX PCC driver. |
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Enable support for mcux scg driver. |
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Enable support for mcux sim driver. |
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Enable support for the Nordic Semiconductor nRFxx series SoC clock driver. |
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Enables retrieving debug information like number of performed or skipped calibrations. |
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Calibration is skipped when temperature change since last calibration was less than configured threshold. If number of consecutive skips reaches configured value then calibration is performed unconditionally. Set to 0 to perform calibration periodically regardless of temperature change. |
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Periodically, calibration action is performed. Action includes temperature measurement followed by clock calibration. Calibration may be skipped if temperature change (compared to measurement of previous calibration) did not exceeded CLOCK_CONTROL_NRF_CALIBRATION_TEMP_DIFF and number of consecutive skips did not exceeded CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP. |
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Calibration is triggered if the temperature has changed by at least this amount since the last calibration. |
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This option can be enabled to force an alternative implementation of the clock control driver. |
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76 ppm to 100 ppm |
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101 ppm to 150 ppm |
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0 ppm to 20 ppm |
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151 ppm to 250 ppm |
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21 ppm to 30 ppm |
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251 ppm to 500 ppm |
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31 ppm to 50 ppm |
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51 ppm to 75 ppm |
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External full swing |
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External low swing |
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RC Oscillator |
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Synthesized from HFCLK |
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Crystal Oscillator |
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Enable support for RV32M1 PCC driver. |
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Enable driver for Reset & Clock Control subsystem found in STM32 family of MCUs |
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This option controls the priority of clock control device initialization. Higher priority ensures that the device is initialized earlier in the startup cycle. If unsure, leave at default value 1 |
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HCLK4 prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
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AHB prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
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APB1 Low speed clock (PCLK1) prescaler, allowed values: 1, 2, 4, 8, 16 |
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APB2 High speed clock (PCLK2) prescaler, allowed values: 1, 2, 4, 8, 16 |
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CPU1 HCLK prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
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CPU2 HCLK prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
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D1 Domain, CPU1 clock (sys_d1cpre_ck prescaler), allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
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APB3 clock (rcc_pclk3) prescaler, allowed values: 1, 2, 4, 8, 16 |
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APB1 clock (rcc_pclk1) prescaler, allowed values: 1, 2, 4, 8, 16 |
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APB2 clock (rcc_pclk2) prescaler, allowed values: 1, 2, 4, 8, 16 |
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APB4 clock (rcc_pclk4) prescaler, allowed values: 1, 2, 4, 8, 16 |
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hclk prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
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Enable this option to bypass external high-speed clock (HSE). |
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Value of external high-speed clock (HSE). |
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Enable the low-speed external (LSE) clock supplied with a 32.768 kHz crystal resonator oscillator. |
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allowed values: 1, 2, 3, 4, 5 |
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Use HSE as source of MCO1 |
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Use HSI as source of MCO1 |
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Use LSE as source of MCO1 |
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MCO1 output disabled, no clock on MCO1 |
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Use PLLCLK as source of MCO1 |
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allowed values: 1, 2, 3, 4, 5 |
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Use HSE as source of MCO2 |
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MCO2 output disabled, no clock on MCO2 |
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Use PLLCLK as source of MCO2 |
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Use PLLI2S as source of MCO2 |
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Use SYSCLK as source of MCO2 |
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Enable hardware auto-calibration with LSE. |
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Frequency range of MSI when MSI range is provided in RCC_CR register Range 0: 100kHz Range 1: 200kHz Range 2 around 400 kHz Range 3 around 800 kHz Range 4: 1 MHz Range 5: 2 MHz Range 6: 4 MHz (reset value) Range 7: 8 MHz Range 8: 16 MHz Range 9: 24 MHz Range 10: 32 MHz Range 11: 48 MHz |
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PLL divisor, allowed values: 2-4. |
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PLL multiplier, allowed values: 2-16. PLL output must not exceed 48MHz. |
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PLLM division factor needs to be set correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63 |
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PLLN multiplier factor needs to be set correctly to ensure that the VCO output frequency is between 100 and 432 MHz, except on STM32F401 where the frequency must be between 192 and 432 MHz. Allowed values: 50-432 (STM32F401: 192-432) |
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PREDIV is PLLSCR clock signal prescaler, allowed values: 1 - 16. |
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PREDIV is PLLSCR clock signal prescaler, present on STM32F0 SoC having an HSE Oscillator available like the stm32f04xx, stm32f07xx, stm32f09xx and stm32f030xc parts. If configured on a non supported part, the HSI oscillator will be used a default PLL source and this config will be ignored. Allowed values: 1 - 16. |
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PLLP division factor needs to be set correctly to not exceed 84MHz. Allowed values: 2, 4, 6, 8 |
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The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly. Allowed values: 2-15 |
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PLL R Output divisor, allowed values: 1-128. |
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Use HSE as source of PLL |
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Use HSI as source of PLL |
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Use MSI as source of PLL |
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Use PLL2 as source of main PLL. This is equivalent of defining PLL2 as source PREDIV1SCR. If not selected, default source is HSE. |
|
Enable this option to enable /2 prescaler on HSE to PLL clock signal |
|
Use HSE as source of SYSCLK |
|
Use HSI as source of SYSCLK |
|
Use MSI as source of SYSCLK |
|
Use PLL as source of SYSCLK |
|
Console drivers |
|
This option enables console input handler allowing to write simple interaction between serial console and the OS. |
|
This is an option to be enabled by console drivers to signal that some kind of console exists. |
|
This option can be used to modify the maximum length a console input can be. |
|
This module implements a kernel device driver for the Cortex-M processor SYSTICK timer and provides the standard “system clock driver” interfaces. |
|
Enable support for counter and timer. |
|
Counter driver for x86 CMOS/RTC clock |
|
Enable counter driver based on RTCC module for Silicon Labs Gecko chips. |
|
Enable the IMX EPIT driver. |
|
Enable Counter 1. |
|
Enable Counter 2. |
|
Enable support for mcux General Purpose Timer (GPT) driver. |
|
Enable Counter on GPT1 |
|
Enable Counter on GPT2 |
|
Enable support for mcux rtc driver. |
|
Enable Counter on RTC0 |
|
Enable Counter on RTC1 |
|
Enable Counter on RTC2 |
|
Build RTC driver for STM32 SoCs. Tested on STM32 F3, F4, L4, F7, G4 series |
|
Use LSE as RTC clock |
|
Use LSI as RTC clock |
|
Xtal mode higher driving capability |
|
Xtal mode lower driving capability |
|
Xtal mode medium high driving capability |
|
Xtal mode medium low driving capability |
|
Enable the SAM0 series timer counter (TC) driver in 32-bit wide mode. |
|
clock / 1 |
|
clock / 1024 |
|
clock / 16 |
|
clock / 2 |
|
clock / 256 |
|
clock / 4 |
|
clock / 64 |
|
clock / 8 |
|
clock / 1 |
|
clock / 1024 |
|
clock / 16 |
|
clock / 2 |
|
clock / 256 |
|
clock / 4 |
|
clock / 64 |
|
clock / 8 |
|
clock / 1 |
|
clock / 1024 |
|
clock / 16 |
|
clock / 2 |
|
clock / 256 |
|
clock / 4 |
|
clock / 64 |
|
clock / 8 |
|
clock / 1 |
|
clock / 1024 |
|
clock / 16 |
|
clock / 2 |
|
clock / 256 |
|
clock / 4 |
|
clock / 64 |
|
clock / 8 |
|
Enable Counter on TIMER0 |
|
Enable Counter on TIMER1 |
|
Enable Counter on TIMER2 |
|
Enable Counter on TIMER3 |
|
Enable Counter on TIMER4 |
|
Enable counter driver for Microchip XEC MCU series. Such driver will expose the basic timer devices present on the MCU. |
|
Crypto Drivers [EXPERIMENTAL] |
|
Enable Atmel ATAES132A 32k AES Serial EEPROM support. |
|
Name for the ATAES132A driver which will be used for binding. |
|
ATAES132A chip’s I2C address. |
|
Master I2C port name through which ATAES132A chip is accessed. |
|
Fast bus speed of up to 400KHz. |
|
Standard bis speed of up to 100KHz. |
|
Crypto devices initialization priority. |
|
Enable mbedTLS shim layer compliant with crypto APIs. You will need to fill in a relevant value to CONFIG_MBEDTLS_HEAP_SIZE. |
|
Device name for mbedTLS Pseudo device. |
|
This can be used to tweak the amount of sessions the driver can handle in parallel. |
|
Enable STM32 HAL-based Cryptographic Accelerator driver. |
|
This can be used to tweak the amount of sessions the driver can handle in parallel. |
|
Enable TinyCrypt shim layer compliant with crypto APIs. |
|
Device name for TinyCrypt Pseudo device. |
|
This can be used to tweak the amount of sessions the driver can handle in parallel. |
|
Enable driver for the DHT temperature and humidity sensor family. |
|
Enable display drivers |
|
Enable support for mcux eLCDIF driver. |
|
DMA driver Configuration |
|
IRQ Priority for the DMA Controller. |
|
Device name for DMA Controller 0. |
|
Device name for DMA Controller 1. |
|
Device name for DMA Controller 2. |
|
DesignWare DMA driver. |
|
Enable Nios-II Modular Scatter-Gather DMA(MSGDMA) driver. |
|
DMA driver for Atmel SAM0 series MCUs. |
|
Enable Atmel SAM MCU Family Direct Memory Access (XDMAC) driver. |
|
DMA driver for STM32 series SoCs. |
|
Enable DMA support on F2/F4/F7 series SoCs. |
|
Enable DMA support on F0/F1/F3/L0/L4 series SoCs. |
|
Enable dummy display driver compliant with display driver API. |
|
Dummy display device name |
|
X resolution for dummy display |
|
Y resolution for dummy display |
|
Designware Interrupt Controller can be used as a 2nd level interrupt controller which combines several sources of interrupt into one line that is then routed to the 1st level interrupt controller. |
|
DesignWare Interrupt Controller initialization priority. |
|
Give a name for the instance of Designware Interrupt Controller |
|
Parent interrupt number to which DW_ICTL maps |
|
This indicates the offset in the SW_ISR_TABLE beginning from where the ISRs for Designware Interrupt Controller are assigned. |
|
Enable support for EEPROM hardware. |
|
Enable support for Atmel AT24 (and compatible) I2C EEPROMs. |
|
Enable support for Atmel AT25 (and compatible) SPI EEPROMs. |
|
Enable support for Atmel AT2x (and compatible) I2C/SPI EEPROMs. |
|
Enable the EEPROM shell with EEPROM related commands. |
|
Size of the buffer used for EEPROM read/write commands in the EEPROM shell. |
|
Enable Simulated EEPROM driver. |
|
Minimum read time (µS) |
|
Minimum write time (µS) |
|
Enable Simulated hardware timing. |
|
Enable EEPROM support on the STM32 L0, L1 family of processors. |
|
Enable driver for ENS210 Digital Temperature and Humidity sensor. |
|
Check the crc value after data reading. |
|
Number of retries when value reading failed, value not valid or crc not ok. |
|
Number of retries when status reading failed or device not ready. |
|
The number of samples detected with repeating patterns before an alarm event is triggered. The associated FRO is automatically shut down. |
|
The size in bytes of the buffer used to store entropy generated by the hardware. Should be a power of two for high performance. |
|
This option enables the driver for the True Random Number Generator (TRNG) for TI SimpleLink CC13xx / CC26xx SoCs. |
|
The number of samples used to generate entropy. The time required to generate 64 bits of entropy is determined by the number of FROs enabled, the sampling (system) clock frequency, and this value. |
|
The number of FROs allowed to be shutdown before the driver attempts to take corrective action. |
|
This option enables the entropy number generator for ESP32 SoCs. With Wi-Fi and Bluetooth disabled, this will produce pseudo-entropy numbers: noise from these radios are used to feed entropy in this generator. |
|
Include entropy drivers in system config. |
|
This is an option to be enabled by individual entropy driver to signal that there is a true entropy driver. |
|
This option enables the RNG module, which is an entropy number generator, based on Pseudo-Random Binary Sequences (PRBS) for LiteX SoC builder |
|
This option enables the random number generator accelerator (RNGA) driver based on the MCUX RNGA driver. |
|
This option enables the true random number generator (TRNG) driver based on the MCUX TRNG driver. |
|
Specify the device name to be used for the ENTROPY driver. |
|
This option enables the RNG bias correction, which guarantees a uniform distribution of 0 and 1. When this option is enabled, the time to generate a byte cannot be guaranteed. |
|
Buffer length in bytes used to store entropy bytes generated by the hardware to make them ready for ISR consumers. Please note, that size of the pool must be a power of 2. |
|
Low water-mark threshold in bytes to trigger entropy generation for ISR consumers. As soon as the number of available bytes in the buffer goes below this number hardware entropy generation will be started. |
|
nRF5X RNG IRQ priority. |
|
This option enables the RNG peripheral, which is a random number generator, based on internal thermal noise, that provides a random 8-bit value to the host when read. |
|
Buffer length in bytes used to store entropy bytes generated by the hardware to make them ready for thread mode consumers. Please note, that size of the pool must be a power of 2. |
|
Low water-mark threshold in bytes to trigger entropy generation for thread mode consumers. As soon as the number of available bytes in the buffer goes below this number hardware entropy generation will be started. |
|
This option can be enabled to force an alternative implementation of the entropy driver. |
|
This option enables the true random number generator (TRNG) driver based on the RV32M1 TRNG driver. |
|
Enable True Random Number Generator (TRNG) driver for Atmel SAM MCUs. |
|
This option enables the RNG processor, which is a entropy number generator, based on a continuous analog noise, that provides a entropy 32-bit value to the host when read. It is available for F4 (except STM32F401 & STM32F411), L4, F7 and G4 series. |
|
Enable ESPI Driver. |
|
Enable automatic acknowledge from eSPI slave towards eSPI host whenever it receives suspend or reset warning. If this is disabled, it means the app wants to be give the opportunity to prepare for either HOST suspend or reset. |
|
eSPI Controller supports flash channel. |
|
Driver initialization priority for eSPI driver. |
|
eSPI Controller supports OOB channel. |
|
Enables 8042 keyboard controller over eSPI peripheral channel. |
|
eSPI Controller supports peripheral channel. |
|
Enables debug Port 80 over eSPI peripheral channel. |
|
Enables ACPI Host I/O over eSPI peripheral channel. |
|
Enables legacy Port 92 over eSPI peripheral channel. |
|
Enables UART over eSPI peripheral channel. |
|
This tells the driver to which SoC UART to direct the UART traffic send over eSPI from host. |
|
Enables eSPI driver in slave mode. |
|
eSPI Controller supports virtual wires channel. |
|
Enable the Microchip XEC ESPI driver. |
|
Enable Intel(R) PRO/1000 Gigabit Ethernet driver. |
|
Enabling this will turn on the hexdump of the received and sent frames. Do not leave on for production. |
|
ENC28J60C Stand-Alone Ethernet Controller with SPI Interface |
|
Include port 0 driver |
|
Enable Full Duplex. Device is configured half duplex when disabled. |
|
This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic. |
|
Priority level for internal thread which is ran for incoming packet processing. |
|
Size of the stack used for internal thread which is ran for incoming packet processing. |
|
Given timeout in milliseconds. Maximum amount of time that the driver will wait from the IP stack to get a memory buffer before the Ethernet frame is dropped. |
|
ENC424J600C Stand-Alone Ethernet Controller with SPI Interface |
|
This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic. |
|
Priority level for internal thread which is ran for incoming packet processing. |
|
Size of the stack used for internal thread which is ran for incoming packet processing. |
|
Given timeout in milliseconds. Maximum amount of time that the driver will wait from the IP stack to get a memory buffer before the Ethernet frame is dropped. |
|
Enable Ethernet driver for Silicon Labs Gecko chips. |
|
Set the RX idle timeout period in milliseconds after which the PHY’s carrier status is re-evaluated. |
|
IRQ priority of Ethernet device |
|
MAC Address Byte 0 |
|
MAC Address Byte 1 |
|
MAC Address Byte 2 |
|
MAC Address Byte 3 |
|
MAC Address Byte 4 |
|
MAC Address Byte 5 |
|
Assign an arbitrary MAC address. |
|
Device name allows user to obtain a handle to the device object required by all driver API functions. Device name has to be unique. |
|
Generate a random MAC address dynamically. |
|
RX thread priority |
|
RX thread stack size |
|
Ethernet device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
|
LiteEth Ethernet core driver |
|
LiteEth Ethernet port 0 |
|
IRQ priority |
|
Generate a random MAC address dynamically. |
|
Enable MCUX Ethernet driver. Note, this driver performs one shot PHY setup. There is no support for PHY disconnect, reconnect or configuration change. |
|
Include port 0 driver |
|
Manual MAC address |
|
Generate a random MAC address dynamically on each reboot. Note that using this choice and rebooting a board may leave stale MAC address in peers’ ARP caches and lead to issues and delays in communication. (Use “ip neigh flush all” on Linux peers to clear ARP cache.) |
|
Generate MAC address from MCU’s unique identification register. |
|
Enable hardware acceleration for the following: - IPv4, UDP and TCP checksum (both Rx and Tx) |
|
Enable additional PHY related debug information related to PHY status polling. |
|
Set the PHY status polling period. |
|
Place the Ethernet receiver in promiscuous mode. This may be useful for debugging and not needed for normal work. |
|
Set the frequency in Hz sourced to the PTP timer. If the value is set properly, the timer will be accurate. |
|
Set the number of RX buffers provided to the MCUX driver to store timestamps. |
|
Set the number of TX buffers provided to the MCUX driver to store timestamps. |
|
Set the number of RX buffers provided to the MCUX driver. |
|
Set the number of TX buffers provided to the MCUX driver. |
|
Enable native posix ethernet driver. Note, this driver is run inside a process in your host system. |
|
This option sets the TUN/TAP device name in your host system. |
|
This option sets the driver name and name of the network interface in your host system. |
|
Specify a MAC address for the ethernet interface in the form of six hex 8-bit chars separated by colons (e.g.: aa:33:cc:22:e2:c0). The default is an empty string, which means the code will make 00:00:5E:00:53:XX, where XX will be random. |
|
Enable PTP clock support. |
|
Generate a random MAC address dynamically. |
|
This option sets the name of the script that is run when the host TAP network interface is created. The script should setup IP addresses etc. for the host TAP network interface. The default script accepts following options: -i|–interface <network interface name>, default is zeth -f|–file <config file name>, default is net_setup_host.conf If needed, you can add these options to this script name option. Note that the driver will add -i option with the value of CONFIG_ETH_NATIVE_POSIX_DRV_NAME option to the end of the options list when calling the host setup script. |
|
If set, the native_posix ethernet driver will set up the network
interface, requiring |
|
This option sets the name of the script that is run when the host TAP network interface is created and setup script has been run. The startup script could launch e.g., wireshark to capture the network traffic for the freshly started network interface. Note that the network interface name CONFIG_ETH_NATIVE_POSIX_DRV_NAME is appended at the end of this startup script name. Example script for starting wireshark is provided in ${ZEPHYR_BASE}/samples/net/eth_native_posix/net_start_wireshark.sh file. |
|
By default the startup script is run as a root user. Set here the username to run the script if running it as a root user is not desired. Note that this setting is only for startup script and not for the setup script. The setup script needs to be run always as a root user. |
|
Native posix ethernet driver will strip of VLAN tag from Rx Ethernet frames and sets tag information in net packet metadata. |
|
Tells what Qemu network model to use. This value is given as a parameter to -nic qemu command line option. |
|
Enable Atmel SAM MCU Family Ethernet driver. |
|
Number of network buffers that will be permanently allocated by the Ethernet driver. These buffers are used in receive path. They are preallocated by the driver and made available to the GMAC module to be filled in with incoming data. Their number has to be large enough to fit at least one complete Ethernet frame. SAM ETH driver will always allocate that amount of buffers for itself thus reducing the NET_BUF_RX_COUNT which is a total amount of RX data buffers used by the whole networking stack. One has to ensure that NET_PKT_RX_COUNT is large enough to fit at least two Ethernet frames: one being received by the GMAC module and the other being processed by the higher layer networking stack. |
|
Which queue to force the routing to. This affects both the TX and RX queues setup. |
|
This option is meant to be used only for debugging. Use it to force all traffic to be routed through a specific hardware queue. With this enabled it is easier to verify whether the chosen hardware queue actually works. This works only if there are four or fewer RX traffic classes enabled, as the SAM GMAC hardware supports screening up to four traffic classes. |
|
IRQ priority of Ethernet device |
|
MAC Address Byte 0 |
|
MAC Address Byte 1 |
|
MAC Address Byte 2 |
|
MAC Address Byte 3 |
|
MAC Address Byte 4 |
|
MAC Address Byte 5 |
|
Device name, e.g. I2C_0, of an I2C bus driver device. It is required to obtain handle to the I2C device object. |
|
Read MAC address from an I2C EEPROM. |
|
Internal address of the EEPROM chip where the MAC address is stored. Chips with 1 to 4 byte internal address size are supported. Address size has to be configured in a separate Kconfig option. |
|
Size (in bytes) of the internal EEPROM address. |
|
I2C 7-bit address of the EEPROM chip. |
|
Assign an arbitrary MAC address. |
|
MII |
|
Device name allows user to obtain a handle to the device object required by all driver API functions. Device name has to be unique. |
|
GMAC PHY Address as used by IEEE 802.3, Section 2 MII compatible PHY transceivers. If you have a single PHY on board it is safe to leave it at 0 which is the broadcast address. |
|
Select the number of hardware queues used by the driver. Packets will be routed to appropriate queues based on their priority. |
|
Generate a random MAC address dynamically. |
|
RMII |
|
Enable driver for SMSC/LAN911x/9220 family of chips. |
|
Stellaris on-board Ethernet Controller |
|
Set the RX idle timeout period in milliseconds after which the PHY’s carrier status is re-evaluated. |
|
Enable STM32 HAL based Ethernet driver. It is available for all Ethernet enabled variants of the F2, F4 and F7 series. |
|
IRQ priority |
|
This is the byte 3 of the MAC address. |
|
This is the byte 4 of the MAC address. |
|
This is the byte 5 of the MAC address. |
|
Use the MII physical interface instead of RMII. |
|
Device name |
|
The phy address to use. |
|
Generate a random MAC address dynamically. |
|
RX thread priority |
|
RX thread stack size |
|
When this option is activated, the buffers for DMA transfer are moved from SRAM to the DTCM (Data Tightly Coupled Memory). |
|
Enable EXTI driver for STM32 line of MCUs |
|
IRQ priority of EXTI0 interrupt |
|
IRQ priority of EXTI10 interrupt |
|
IRQ priority of EXTI11 interrupt |
|
IRQ priority of EXTI12 interrupt |
|
IRQ priority of EXTI13 interrupt |
|
IRQ priority of EXTI14 interrupt |
|
IRQ priority of EXTI15:10 interrupt |
|
IRQ priority of EXTI15:4 interrupt |
|
IRQ priority of EXTI15 interrupt |
|
IRQ priority of EXTI1:0 interrupt |
|
IRQ priority of EXTI1 interrupt |
|
IRQ priority of EXTI2 interrupt |
|
IRQ priority of EXTI3:2 interrupt |
|
IRQ priority of EXTI3 interrupt |
|
IRQ priority of EXTI4 interrupt |
|
IRQ priority of EXTI5 interrupt |
|
IRQ priority of EXTI6 interrupt |
|
IRQ priority of EXTI7 interrupt |
|
IRQ priority of EXTI8 interrupt |
|
IRQ priority of EXTI9:5 interrupt |
|
IRQ priority of EXTI9 interrupt |
|
IRQ priority of LPTIM1 interrupt |
|
IRQ priority of USB OTG FS Wake interrupt |
|
IRQ priority of RVD Through interrupt |
|
IRQ priority of RTC Wake Up interrupt |
|
IRQ priority of Tamper and Timestamp interrupt |
|
This option enables the test random number generator for the native_posix board (ARCH_POSIX). This is based on the host random() API. Note that this entropy generator is only meant for test purposes and does not generate real entropy. It actually generates always the same sequence of random numbers if initialized with the same seed. |
|
Enable support for the flash hardware. |
|
This option is enabled when any flash driver is enabled. |
|
This option is enabled when the SoC flash driver supports retrieving the layout of flash memory pages. |
|
This option can be enabled to force an alternative implementation of the flash driver. |
|
Enables API for retrieving the layout of flash memory pages. |
|
Enable the flash shell with flash related commands such as test, write, read and erase. |
|
Enable the flash simulator. |
|
If selected, writing to a non-erased program unit will succeed, otherwise, it will return an error. Keep in mind that write operations can only pull bits to zero, regardless. |
|
If selected, turning on write protection will also prevent erasing. |
|
Minimum erase time (µS) |
|
Minimum read time (µS) |
|
Minimum write time (µS) |
|
Enable hardware timing simulation |
|
Only up to this number of beginning pages will be tracked while catching dedicated flash operations and thresholds. This number is not automatic because implementation uses UNTIL_REPEAT() macro, which is limited to take explicitly number of iterations. This is why it’s not possible to calculate the number of pages with preprocessor using DT properties. |
|
If selected, the reading operation does not check if access is aligned. Disable this option only if you want to simulate a specific FLASH interface that requires aligned read access. |
|
Enable output for FLEXPWM1_PWM0 in the driver. Say y here if you want to use FLEXPWM1_PWM0 output. |
|
Enable output for FLEXPWM1_PWM1 in the driver. Say y here if you want to use FLEXPWM1_PWM1 output. |
|
Enable output for FLEXPWM1_PWM2 in the driver. Say y here if you want to use FLEXPWM1_PWM2 output. |
|
Enable output for FLEXPWM1_PWM3 in the driver. Say y here if you want to use FLEXPWM1_PWM3 output. |
|
Enable output for FLEXPWM2_PWM0 in the driver. Say y here if you want to use FLEXPWM2_PWM0 output. |
|
Enable output for FLEXPWM2_PWM1 in the driver. Say y here if you want to use FLEXPWM2_PWM1 output. |
|
Enable output for FLEXPWM2_PWM2 in the driver. Say y here if you want to use FLEXPWM2_PWM2 output. |
|
Enable output for FLEXPWM2_PWM3 in the driver. Say y here if you want to use FLEXPWM2_PWM3 output. |
|
Enable output for FLEXPWM3_PWM0 in the driver. Say y here if you want to use FLEXPWM3_PWM0 output. |
|
Enable output for FLEXPWM3_PWM1 in the driver. Say y here if you want to use FLEXPWM3_PWM1 output. |
|
Enable output for FLEXPWM3_PWM2 in the driver. Say y here if you want to use FLEXPWM3_PWM2 output. |
|
Enable output for FLEXPWM3_PWM3 in the driver. Say y here if you want to use FLEXPWM3_PWM3 output. |
|
Enable output for FLEXPWM4_PWM0 in the driver. Say y here if you want to use FLEXPWM4_PWM0 output. |
|
Enable output for FLEXPWM4_PWM1 in the driver. Say y here if you want to use FLEXPWM4_PWM1 output. |
|
Enable output for FLEXPWM4_PWM2 in the driver. Say y here if you want to use FLEXPWM4_PWM2 output. |
|
Enable output for FLEXPWM4_PWM3 in the driver. Say y here if you want to use FLEXPWM4_PWM3 output. |
|
Enable framebuffer-based display ‘helper’ driver. |
|
Enable driver for the FXAS21002 gyroscope |
|
Selects the output data rate 0: 800 Hz 1: 400 Hz 2: 200 Hz 3: 100 Hz 4: 50 Hz 5: 25 Hz 6: 12.5 Hz 7: 12.5 Hz |
|
Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin. |
|
Selects the full scale range 0: +/-2000 dps (62.5 mdps/LSB) 1: +/-1000 dps (31.25 mdps/LSB) 2: +/-500 dps (15.625 mdps/LSB) 3: +/-250 dps (7.8125 mdps/LSB) |
|
Own thread priority |
|
Own thread stack size |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
The datasheet defines the value of the WHOAMI register, but some pre-production devices can have a different value. It is unlikely you should need to change this configuration option from the default. |
|
Enable driver for the FXOS8700 accelerometer/magnetometer. The driver also supports MMA8451Q, MMA8652FC and MMA8653FC accelerometers. If the driver is used with one of these accelerometers then the Accelerometer-only mode should be selected.” |
|
Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin. |
|
Accelerometer-only mode |
|
Hybrid (accel+mag) mode |
|
Magnetometer-only mode |
|
Enable motion detection |
|
Say Y to route motion interrupt to INT1 pin. Say N to route to INT2 pin. |
|
High resolution power mode |
|
Low noise low power mode |
|
Low power mode |
|
Normal power mode |
|
Enable pulse detection |
|
Pulse configuration register |
|
Say Y to route pulse interrupt to INT1 pin. Say N to route to INT2 pin. |
|
The time interval that starts after the first pulse detection where the pulse-detection function ignores the start of a new pulse. The resolution depends upon the sample rate (ODR) and the high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and pls_hpf_en=0, the resolution is 1.25 ms/LSB. |
|
Threshold to start the pulse-event detection procedure on the X-axis. Threshold values for each axis are unsigned 7-bit numbers with a fixed resolution of 0.063 g/LSB, corresponding to an 8g acceleration full-scale range. |
|
Threshold to start the pulse-event detection procedure on the Y-axis. Threshold values for each axis are unsigned 7-bit numbers with a fixed resolution of 0.063 g/LSB, corresponding to an 8g acceleration full-scale range. |
|
Threshold to start the pulse-event detection procedure on the Z-axis. Threshold values for each axis are unsigned 7-bit numbers with a fixed resolution of 0.063 g/LSB, corresponding to an 8g acceleration full-scale range. |
|
The maximum time interval that can elapse between the start of the acceleration on the selected channel exceeding the specified threshold and the end when the channel acceleration goes back below the specified threshold. The resolution depends upon the sample rate (ODR) and the high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and pls_hpf_en=0, the resolution is 0.625 ms/LSB. |
|
The maximum interval of time that can elapse after the end of the latency interval in which the start of the second pulse event must be detected provided the device has been configured for double pulse detection. The detected second pulse width must be shorter than the time limit constraint specified by the PULSE_TMLT register, but the end of the double pulse need not finish within the time specified by the PULSE_WIND register. The resolution depends upon the sample rate (ODR) and the high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and pls_hpf_en=0, the resolution is 1.25 ms/LSB. |
|
2g (0.244 mg/LSB) |
|
4g (0.488 mg/LSB) |
|
8g (0.976 mg/LSB) |
|
Enable the temperature sensor. Note that the temperature sensor is uncalibrated and its output for a given temperature may vary from one device to the next. |
|
Own thread priority |
|
Own thread stack size |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for GD7965 compatible controller. |
|
The ARM Generic Interrupt Controller v1 (e.g. PL390) works with the ARM Cortex-family processors. |
|
The ARM Generic Interrupt Controller v2 (e.g. GIC-400) works with the ARM Cortex-family processors. |
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The ARM Generic Interrupt Controller v3 (e.g. GIC-500 and GIC-600) works with the ARM Cortex-family processors. |
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Include GPIO drivers in system config |
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Enable GPIO port A support |
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Enable GPIO port B support |
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Enable the TI SimpleLink CC13xx / CC26xx GPIO driver. |
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Enable the GPIO driver on TI SimpleLink CC32xx boards |
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Include support for the GPIO port A0. |
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Include support for the GPIO port A1. |
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Include support for the GPIO port A2. |
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Include support for the GPIO port A3. |
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Enable config options to support the ARM CMSDK GPIO controllers. Says n if not sure. |
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Build the driver to utilize GPIO controller Port 0. |
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Device name for Port 0. |
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Interrupt priority for Port 0. |
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Build the driver to utilize GPIO controller Port 1. |
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Device name for Port 1. |
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Interrupt priority for Port 1. |
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Build the driver to utilize GPIO controller Port 2. |
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Device name for Port 2. |
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Interrupt priority for Port 2. |
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Build the driver to utilize GPIO controller Port 3. |
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Device name for Port 3. |
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Interrupt priority for Port 3. |
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Enable GPIO port C support |
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Enable driver for Designware GPIO |
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Include Designware GPIO driver |
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Clock controller’s subsystem |
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When interrupts fire, the driver’s ISR function is being called directly. |
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IRQ priority |
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When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers. |
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Driver name |
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Include Designware GPIO driver |
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Clock controller’s subsystem |
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When interrupts fire, the driver’s ISR function is being called directly. |
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IRQ priority |
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When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers. |
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Driver name |
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Include Designware GPIO driver |
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Clock controller’s subsystem |
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When interrupts fire, the driver’s ISR function is being called directly. |
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IRQ priority |
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When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers. |
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Driver name |
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Include Designware GPIO driver |
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Clock controller’s subsystem |
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When interrupts fire, the driver’s ISR function is being called directly. |
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IRQ priority |
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When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers. |
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Driver name |
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Enable clock gating |
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Device driver initialization priority. |
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Enable GPIO port D support |
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Enables the ESP32 GPIO driver |
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Include support for GPIO pins 0-31 on the ESP32. |
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Include support for GPIO pins 32-39 on the ESP32. |
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Select the IRQ line to be used for GPIO interrupts. Edge-triggered interrupts are supported on lines: 10, 22, 28, 30. Level-triggered interrupts are supported on lines: 0-5, 8, 9, 12, 13, 17-21, 23-27, 31. |
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Enable GPIO port E support |
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Enable GPIO port F support |
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Enable the Gecko gpio driver. |
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Common initialization priority |
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Enable Port A. |
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Enable Port B. |
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Enable Port C. |
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Enable Port D. |
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Enable Port E. |
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Enable Port F. |
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Enable Port G. |
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Enable Port H. |
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Enable Port I. |
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Enable Port J. |
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Enable Port K. |
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Enable GPIO port G support |
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Enable keyscan driver for HT16K33. The HT16K33 is a memory mapping, multifunction LED controller driver. The controller supports matrix key scan circuit of up to 13x3 keys. The keyscan functionality is exposed as up to 3 GPIO controller drivers, each supporting GPIO callbacks for keyscan event notifications. |
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Device driver initialization priority. This driver must be initialized after the HT16K33 LED driver. |
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Enable the IMX GPIO driver. |
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Enable Port 1. |
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Enable Port 2. |
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Enable Port 3. |
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Enable Port 4. |
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Enable Port 5. |
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Enable Port 6. |
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Enable Port 7. |
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Enable driver for Intel Apollo Lake SoC GPIO |
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This option enables the checks to make sure the GPIO pin can be manipulated. Only if the pin is owned by the host software and its functioning as GPIO, then the driver allows manipulating the pin. Say y if unsure. |
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Enable Litex GPIO driver. |
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Enable GPIO driver for LMP90xxx. The LMP90xxx is a multi-channel, low power sensor analog frontend (AFE). The GPIO port of the LMP90xxx (D6 to D0) is exposed as a GPIO controller driver with read/write support. |
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Device driver initialization priority. This driver must be initialized after the LMP90xxx ADC driver. |
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Enable the MCUX pinmux driver. |
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Enable the MCUX IGPIO driver. |
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Enable Port 1. |
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Enable Port 2. |
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Enable Port 3. |
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Enable Port 4. |
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Enable Port 5. |
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Enable the MCUX LPC pinmux driver. |
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Enable Port 0. |
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Port 0 driver name |
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Enable Port 1. |
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Port 1 driver name |
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Enable Port A. |
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Enable Port B. |
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Enable Port C. |
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Enable Port D. |
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Enable Port E. |
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This is a driver for accessing a simple, fixed purpose, 32-bit memory-mapped i/o register using the same APIs as GPIO drivers. This is useful when an SoC or board has registers that aren’t part of a GPIO IP block and these registers are used to control things that Zephyr normally expects to be specified using a GPIO pin, e.g. for driving an LED, or chip-select line for an SPI device. |
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Enable GPIO driver for nRF line of MCUs. |
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Initialization priority for nRF GPIO. |
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Enable nRF GPIO port P0 config options. |
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Enable nRF GPIO port P1 config options. |
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Enable driver for PCA95XX I2C-based GPIO chip. |
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Device driver initialization priority. |
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Enable the RV32M1 GPIO driver. |
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Enable Port A. |
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Enable Port B. |
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Enable Port C. |
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Enable Port D. |
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Enable Port E. |
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Enable support for the Atmel SAM ‘PORT’ GPIO controllers. |
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Enable support for the Atmel SAM0 ‘PORT’ GPIO controllers. |
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Enable GPIO Shell for testing. |
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Enable driver for the SiFive Freedom GPIO controller. Says n if not sure. |
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GPIO 0 interrupt priority |
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GPIO 10 interrupt priority |
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GPIO 11 interrupt priority |
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GPIO 12 interrupt priority |
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GPIO 13 interrupt priority |
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GPIO 14 interrupt priority |
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GPIO 15 interrupt priority |
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GPIO 16 interrupt priority |
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GPIO 17 interrupt priority |
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GPIO 18 interrupt priority |
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GPIO 19 interrupt priority |
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GPIO 1 interrupt priority |
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GPIO 20 interrupt priority |
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GPIO 21 interrupt priority |
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GPIO 22 interrupt priority |
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GPIO 23 interrupt priority |
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GPIO 24 interrupt priority |
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GPIO 25 interrupt priority |
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GPIO 26 interrupt priority |
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GPIO 27 interrupt priority |
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GPIO 28 interrupt priority |
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GPIO 29 interrupt priority |
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GPIO 2 interrupt priority |
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GPIO 30 interrupt priority |
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GPIO 31 interrupt priority |
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GPIO 3 interrupt priority |
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GPIO 4 interrupt priority |
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GPIO 5 interrupt priority |
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GPIO 6 interrupt priority |
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GPIO 7 interrupt priority |
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GPIO 8 interrupt priority |
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GPIO 9 interrupt priority |
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Enable support for the Stellaris GPIO controllers. |
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Enable GPIO driver for STM32 line of MCUs |
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Enable GPIO port A support |
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Enable GPIO port B support |
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Enable GPIO port C support |
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Enable GPIO port D support |
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Enable GPIO port E support |
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Enable GPIO port F support |
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Enable GPIO port G support |
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Enable GPIO port H support |
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Enable GPIO port I support |
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Enable GPIO port J support |
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Enable GPIO port K support |
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JTAG-DP Disabled and SW-DP Disabled |
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Full SWJ (JTAG-DP + SW-DP): Reset State |
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JTAG-DP Disabled and SW-DP Enabled |
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Full SWJ (JTAG-DP + SW-DP) but without NJTRST |
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Enable driver for SX1509B I2C GPIO chip. |
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Device driver initialization priority. |
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Enable the Microchip XEC gpio driver. |
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Enable GPIO 000-036 or what would be equivalent to PortA. |
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Enable GPIO 040-076 or what would be equivalent to Port B |
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Enable GPIO 100-136 or what would be equivalent to Port C |
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Enable GPIO 140-176 or what would be equivalent to Port C |
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Enable GPIO 200-236 or what would be equivalent to Port D |
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Enable GPIO 240-276 or what would be equivalent to Port E |
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Setting this value will enable driver support for the Groove-LCD RGB Backlight. |
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Specify the device name of the I2C master device to which the Grove LCD is connected. |
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Setting this value will enable driver support for the Grove Light Sensor. |
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Setting this value will enable driver support for the Grove Temperature Sensor. |
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Indicates that the platform supports SEGGER J-Link RTT. |
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Signifies whether DesignWare SPI compatible HW is available |
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Enable driver for HMC5883L I2C-based magnetometer. |
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Magnetometer full-scale range. An X value for the config represents a range of +/- X gauss. Valid values are 0.88, 1.3, 1.9, 2.5, 4, 4.7, 5.6 and 8.1. |
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Magnetometer output data rate expressed in samples per second. Data rates supported by the chip are 0.75, 1.5, 3, 7.5, 15, 30 and 75. |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable HopeRF HP206C barometer and altimeter support. |
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Value, in cm, that will be used to compensate altitude calculation. For more info on how to choose this value, consult section 6.1.1 in the datasheet. |
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Altitude offset set at runtime |
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Allowed values: 4096, 2048, 1024, 512, 256, 128 |
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Oversampling rate set at runtime |
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This option selects High Precision Event Timer (HPET) as a system timer. |
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Enable LED driver for HT16K33. The HT16K33 is a memory mapping, multifunction LED controller driver. The controller supports up to 128 LEDs (up to 16 rows and 8 commons). |
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Enable keyscan child device support in the HT16K33 LED driver. The keyscan functionality itself is handled by the HT16K33 GPIO driver. |
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Keyscan debounce interval in milliseconds. |
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Priority level for internal thread for keyscan interrupt processing. |
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Size of the stack used for internal thread for keyscan interrupt processing. |
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Keyscan poll interval in milliseconds. Polling is only used if no interrupt line is present. |
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Enable driver for HTS221 I2C-based temperature and humidity sensor. |
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Sensor output data rate expressed in samples per second. Data rates supported by the chip are 1, 7 and 12.5. |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable hwinfo driver. |
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Enable ESP32 hwinfo driver. |
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Enable NXP i.mx RT hwinfo driver. |
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Enable LiteX hwinfo driver |
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Enable NXP kinetis mcux hwinfo driver. |
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Enable Nordic NRF hwinfo driver. |
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Enable Atmel SAM hwinfo driver. |
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Enable Atmel SAM0 hwinfo driver. |
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Enable hwinfo Shell for testing. |
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Enable STM32 hwinfo driver. |
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Enable I2C Driver Configuration |
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Enable I2C Port 0 |
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IRQ priority. |
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Enable nRF TWI Master without EasyDMA on port 0. |
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Enable nRF TWI Master with EasyDMA on port 0. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail. |
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Enable I2C Port 1 |
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Enable nRF TWI Master without EasyDMA on port 1. |
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Enable nRF TWI Master with EasyDMA on port 1. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail. |
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Enable I2C Port 2 |
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Enable nRF TWI Master with EasyDMA on port 2. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail. |
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Enable I2C Port 3 |
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Enable nRF TWI Master with EasyDMA on port 3. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail. |
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Enable I2C Port 4 |
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Enable I2C Port 5 |
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Enable I2C Port 6 |
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Enable I2C Port 7 |
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Enable library used for software driven (bit banging) I2C support |
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Enable support for I2C on the TI SimpleLink CC13xx / CC26xx series. |
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Enable the CC32XX I2C driver. |
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Enable the Design Ware I2C driver |
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Set the clock speed for I2C |
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Enable virtual I2C Slave EEPROM driver |
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Enables the ESP32 I2C driver |
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Port 0 IRQ line |
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Port 0 Receive LSB first |
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Port 0 Transmit LSB first |
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Port 1 IRQ line |
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Port 1 Receive LSB first |
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Port 1 Transmit LSB first |
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I2C timeout to receive a data bit in APB clock cycles |
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Enable the SiLabs Gecko I2C bus driver. |
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Enable software driven (bit banging) I2C support using GPIO pins |
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This tells the driver to configure the I2C device at boot, depending on the additional configuration options below. |
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This is the name of the GPIO device that controls the I2C lines. |
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This is the device name for the I2C device, and is included in the device struct. |
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This is the GPIO pin number for the I2S SCL line |
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This is the GPIO pin number for the I2S SDA line |
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This tells the driver to configure the I2C device at boot, depending on the additional configuration options below. |
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This is the name of the GPIO device that controls the I2C lines. |
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This is the device name for the I2C device, and is included in the device struct. |
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This is the GPIO pin number for the I2S SCL line |
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This is the GPIO pin number for the I2S SDA line |
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This tells the driver to configure the I2C device at boot, depending on the additional configuration options below. |
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This is the name of the GPIO device that controls the I2C lines. |
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This is the device name for the I2C device, and is included in the device struct. |
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This is the GPIO pin number for the I2S SCL line |
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This is the GPIO pin number for the I2S SDA line |
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This tells the driver to configure the I2C device at boot, depending on the additional configuration options below. |
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This is the name of the GPIO device that controls the I2C lines. |
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This is the device name for the I2C device, and is included in the device struct. |
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This is the GPIO pin number for the I2C SCL line |
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This is the GPIO pin number for the I2C SDA line |
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Enable the i.MX I2C driver. |
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I2C device driver initialization priority. |
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Enable support for Litex I2C driver |
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Enable the mcux I2C driver. |
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Enable the mcux LPI2C driver. |
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Enable the Nios-II I2C driver. |
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Enable support for nrfx TWI drivers for nRF MCU series. Peripherals with the same instance ID cannot be used together, e.g. I2C_0 and SPI_0. You may need to disable SPI_0 or SPI_1. |
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Enable the RV32M1 LPI2C driver. |
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Enable the SAM0 series SERCOM I2C driver. |
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This enables DMA driven transactions for the I2C peripheral. DMA driven mode requires fewer interrupts to handle the transaction and ensures that high speed modes are not delayed by data reloading. |
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Enable Atmel SAM MCU Family (TWI) I2C bus driver. |
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Enable Atmel SAM MCU Family (TWIHS) I2C bus driver. |
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I2C driver for ARM’s SBCon two-wire serial bus interface |
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Enable I2C Shell. The I2C shell currently support scanning. |
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Enable I2C support on SiFive Freedom |
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Enable I2C Slave Driver Configuration |
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I2C Slave device driver initialization priority. |
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Enable I2C support on the STM32 SoCs |
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Enable Interrupt support for the I2C Driver |
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Enable I2C support on the STM32 F1 and F4X family of processors. This driver also supports the F2 and L1 series. |
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Enable I2C support on the STM32 F0, F3, F7, L4, WBX, MP1, G0 and G4 family of processors. This driver also supports the L0 series. If I2C_SLAVE is enabled it selects I2C_STM32_INTERRUPT, since slave mode is only supported by this driver with interrupts enabled. |
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Enable the Microchip XEC I2C driver. |
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Enable support for the I2S (Inter-IC Sound) hardware bus. |
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Enable I2S controller port 1. |
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Enable I2S controller port 2. |
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Enable I2S controller port 3. |
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Enable I2S controller port 4. |
|
Enable I2S controller port 5. |
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Enable Inter Sound (I2S) bus driver for Intel_S1000 based on Synchronous Serial Port (SSP) module. |
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DMA channel number to use for I2S1 RX transfer. |
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DMA channel number to use for I2S1 TX transfer. |
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I2S 1 device name |
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DMA channel number to use for I2S2 RX transfer. |
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DMA channel number to use for I2S2 TX transfer. |
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I2S 2 device name |
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DMA channel number to use for I2S3 RX transfer. |
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DMA channel number to use for I2S3 TX transfer. |
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I2S 3 device name |
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Name of the DMA device this device driver can use. |
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Interrupt priority |
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Device driver initialization priority. |
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Enable Inter Sound (I2S) bus driver for Atmel SAM MCU family based on Synchronous Serial Controller (SSC) module. |
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DMA channel number to use for RX transfers. |
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DMA channel number to use for TX transfers. |
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Interrupt priority |
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I2S 0 device name |
|
If enabled RF signal is connected to RF pin. It will be configured as an output or an input depending on whether the receiver is working in master or slave mode. If disabled RF signal is disconnected from RF pin and connected internally to TF (Transmitter Frame Synchro signal). |
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If enabled RK signal is connected to RK pin. It will be configured as an output or an input depending on whether the receiver is working in master or slave mode. If disabled RK signal is disconnected from RK pin and connected internally to TK (Transmitter Clock signal). |
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PB5 |
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PD10 |
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PD26 |
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Name of the DMA device this device driver can use. |
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RX queue length |
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TX queue length |
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Enable I2S support on the STM32 family of processors. (Tested on the STM32F4 series) |
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Division factor for the audio PLL (PLLI2S) VCO input clock. PLLM factor should be selected to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63 |
|
Multiply factor for the audio PLL (PLLI2S) VCO output clock. PLLN factor should be selected to ensure that the VCO output frequency ranges from 100 to 432 MHz. Allowed values: 50-432 |
|
Division factor for the I2S clock. PLLR factor should be selected to ensure that the I2S clock frequency is less than or equal to 192MHz. Allowed values: 2-7 |
|
RX queue length |
|
TX queue length |
|
Enable it if I2S clock should be provided by the PLLI2S. If not enabled the clock will be provided by HSI/HSE. |
|
Number of retries when reading failed or device not ready. |
|
IEEE 802.15.4 drivers options |
|
TI CC1200 Driver support |
|
Set the CCA threshold. See datasheet’s AGC_CS_THR register for more information. Do not touch this unless you know what you are doing. |
|
This option sets the driver name |
|
This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic. |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware cc1200 requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack. |
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This is the byte 4 of the MAC address. |
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This is the byte 5 of the MAC address. |
|
This is the byte 6 of the MAC address. |
|
This is the byte 7 of the MAC address. |
|
Generate a random MAC address dynamically. |
|
Use TI CC1200 RF pre-sets |
|
868MHz - 50Kbps - 2-GFSK - IEEE 802.15.4g compliant - ETSI |
|
920MHz - 50Kbps - 2-GFSK - IEEE 802.15.4g compliant - ARIB |
|
434MHz - 50Kbps - 2-GFSK - IEEE 802.15.4g compliant - ETSI |
|
Set the gain adjustment. See datasheet’s AGC_GAIN_ADJUST register for more information. Do not touch this unless you know what you are doing. |
|
This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size. |
|
This sets the XOSC value, it must be between 38400 and 40000. This value should follow what has been set in the RF settings via SmartRF tool. Do not touch this unless you know what you are doing. |
|
TI CC13xx / CC26xx IEEE 802.15.4 driver support |
|
This option sets the driver name. |
|
Set the initialization priority number. |
|
This option sets the driver’s stack size for its internal RX thread. |
|
TI CC2520 Driver support |
|
This option will expose the hardware AES encryption from CC2520. Such feature should not be used for anything but 802.15.4 security. The crypto device exposed will only support synchronous CCM operation. |
|
This option sets the driver name for the crypto part found on CC2520. |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. It should be initialized after CC2520 as it shares the same runtime context. |
|
This option sets the driver name |
|
This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic. |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware cc2520 requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack. |
|
This is the byte 4 of the MAC address. |
|
This is the byte 5 of the MAC address. |
|
This is the byte 6 of the MAC address. |
|
This is the byte 7 of the MAC address. |
|
Generate a random MAC address dynamically. |
|
This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size. |
|
NXP KW41Z Driver support |
|
This option sets the driver name. Do not change it unless you know what you are doing. |
|
Set the initialization priority number. Do not change it unless you know what you are doing. It has to start before the net stack. |
|
NXP MCR20A Driver support |
|
This option sets the driver name |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware mcr20a requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack. |
|
This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size. |
|
nRF52 series IEEE 802.15.4 Driver |
|
This option sets the driver name |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. |
|
This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size. |
|
This option enables using the drivers in a so-called “raw” mode, i.e. without a MAC stack (the net L2 layer for 802.15.4 will not be built). Used only for very specific cases, such as wpan_serial and wpanusb samples. |
|
ATMEL RF2XX Driver support |
|
This option sets the driver name |
|
Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware rf2xx requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack. |
|
This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size. |
|
UART PIPE fake radio driver support for QEMU |
|
UART PIPE Driver name |
|
This option assure the driver will process just frames addressed to him. |
|
This is the byte 4 of the MAC address. |
|
This is the byte 5 of the MAC address. |
|
This is the byte 6 of the MAC address. |
|
This is the byte 7 of the MAC address. |
|
Generate a random MAC address dynamically. |
|
Enable driver for IIS3DHHC SPI-based accelerometer sensor. |
|
Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin. |
|
Enable Sensor at 1KHz |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for ILI9340 display driver. |
|
Adafruit 2.2” TFT 1480 |
|
Seeed 2.8” TFT v2.0 |
|
RGB565 |
|
RGB888 |
|
Enable support for Intel’s GMM and Neural Network Accelerator |
|
Device driver initialization priority. |
|
Max. number of unique neural network models required in the system |
|
Maximum number of pending inference requests in the driver |
|
Name of the GNA device this device driver can use. |
|
Sets GNA operation mode for power saving Levels are: 0 ALWAYS_ON, GNA is always on with very minimal power save 1 CLOCK_GATED, GNA clock is gated when not active 2 POWER_GATED, GNA clock and power are gated when not active 3 ALWAYS_OFF, GNA is tuned off and never used in the system |
|
This option signifies that the target has an IO-APIC device. This capability allows IO-APIC-dependent code to be included. |
|
At boot, mask all IOAPIC RTEs if they may be in an undefined state. You don’t need this if the RTEs are either all guaranteed to be masked when the OS starts up, or a previous boot stage has done some IOAPIC configuration that needs to be preserved. |
|
This option indicates the maximum number of Redirection Table Entries (RTEs) (one per IRQ available to the IO-APIC) made available to the kernel, regardless of the number provided by the hardware itself. For most efficient usage of memory, it should match the number of IRQ lines needed by devices connected to the IO-APIC. |
|
Include interrupt-based inter-processor mailboxes drivers in system configuration |
|
Enable the receiving side of IPM console |
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Enable the sending side of IPM console |
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Each instance of the IPM console receiver driver creates a worker thread to print out incoming messages from the remote CPU. Specify the stack size for these threads here. |
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Driver for NXP i.MX messaging unit |
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There will be a single message type with id 0 and a maximum size of 16 bytes. |
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There will be four message types with ids 0, 1, 2 or 3 and a maximum size of 4 bytes each. |
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There will be two message types with ids 0 or 1 and a maximum size of 8 bytes each. |
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Driver for MCUX mailbox |
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Driver for SSE 200 MHU (Message Handling Unit) |
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Enable IPM Message Channel 0 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Enable IPM Message Channel 10 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Enable IPM Message Channel 11 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Enable IPM Message Channel 12 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Enable IPM Message Channel 13 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Enable IPM Message Channel 14 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Enable IPM Message Channel 15 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Enable IPM Message Channel 1 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Enable IPM Message Channel 2 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Enable IPM Message Channel 3 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Enable IPM Message Channel 4 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Enable IPM Message Channel 5 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Enable IPM Message Channel 6 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Enable IPM Message Channel 7 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Enable IPM Message Channel 8 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Enable IPM Message Channel 9 |
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IPM Message RX Channel |
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IPM Message TX Channel |
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Driver for Nordic nRF messaging unit, based on nRF IPC peripheral HW. |
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Enable this option if the IPM device should have a single instance, instead of one per IPC message channel. |
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Driver for stm32 IPCC mailboxes |
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use to define the Processor ID for IPCC access |
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Enable driver for the ISL29035 light sensor. |
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105 ms |
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0.0256 ms |
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0.41 ms |
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6.5 ms |
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1 |
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16 |
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4 |
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8 |
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16000 |
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1000 |
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4000 |
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64000 |
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Sensing mode for ambient light spectrum. |
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Sensing mode for infrared spectrum. |
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Priority of thread used to handle the timer and threshold triggers. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable IWDG driver for STM32 line of MCUs |
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Enable this setting to allow IWDG to be automatically started during device initialization. Note that once IWDG is started it must be reloaded before the counter reaches 0, otherwise the MCU will be reset. |
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Set timeout value for IWDG in microseconds. The min timeout supported is 0.1ms, the max timeout is 26214.4ms. |
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Include Keyboard scan drivers in system config. |
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Enable driver for the FT5336 capacitive touch panel controller. |
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Sample period (ms) |
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Keyboard scan device driver initialization priority. |
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Enable the Microchip XEC Kscan IO driver. |
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Adjust the value to your keyboard columns. The maximum column size for the Microchip XEC family is 18 (from 0 to 17). |
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Determines the time in msecs for debouncing a key press. |
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Determines the time in msecs for debouncing a key release. |
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Defines the poll period in msecs between between matrix scans. |
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Adjust the value to your keyboard rows. The maximum column size for the Microchip XEC family is 8 (from 0 to 7). |
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The value depends on your debugging needs. This generates an encoded trace of events without going to debug logging to avoid timing impact on running code. The buffer is post analyzed via the debugger. |
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Include LED drivers in the system configuration. |
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System initialization priority for LED drivers. |
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Include LED strip drivers in the system configuration. |
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System initialization priority for LED strip drivers. |
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Enable the Gecko leuart driver. |
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Enable SPI/I2C-based driver for LIS2DH, LIS3DH, LSM303DLHC, LIS2DH12, LSM303AGR triaxial accelerometer sensors. |
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+/-16g |
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+/-2g |
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+/-4g |
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+/-8g |
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Set at runtime |
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1Hz |
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10Hz |
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25Hz |
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50Hz |
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100Hz |
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200Hz |
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400Hz |
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1.6KHz |
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5KHz |
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1.25KHz |
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Set at runtime |
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high resolution (12 bit) |
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low power (8 bit) |
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normal (10 bit) |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable driver for LIS2DS12 accelerometer sensor driver |
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Enable/disable temperature |
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Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are: 0: Full Scale selected at runtime 2: +/- 2g 4: +/- 4g 8: +/- 8g 16: +/- 16g |
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Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 25Hz 3: 50Hz 4: 100Hz 5: 200Hz 6: 400Hz 7: 800Hz |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable driver for LIS2DW12 accelerometer sensor driver |
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16G |
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2G |
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4G |
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8G |
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Set at runtime (Default 2G) |
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int1 |
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int2 |
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100 Hz |
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12.5 Hz |
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1600 Hz |
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1.6 Hz |
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200 Hz |
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25 Hz |
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400 Hz |
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50 Hz |
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800 Hz |
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Set at runtime (Default 100 Hz) |
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single |
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Specify the sensor power mode 0: Low Power M1 1: Low Power M2 2: Low Power M3 3: Low Power M4 4: High Performance |
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Enable pulse (single/double tap) detection |
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When double-tap recognition is enabled, this register expresses the maximum time between two successive detected taps to determine a double-tap event. Where 0 equals 16*1/ODR and 1LSB = 32*1/ODR. |
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Expected quiet time after a tap detection: this register represents the time after the first detected tap in which there must not be any overthreshold event. Where 0 equals 2*1/ODR and 1LSB = 4*1/ODR. |
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Maximum duration of over-threshold event: this register represents the maximum time of an over-threshold signal detection to be recognized as a tap event. Where 0 equals 4*1/ODR and 1LSB = 8*1/ODR. |
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Threshold to start the pulse-event detection procedure on the X-axis. Threshold values for each axis are unsigned 5-bit corresponding to an 2g acceleration full-scale range. |
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Threshold to start the pulse-event detection procedure on the Y-axis. Threshold values for each axis are unsigned 5-bit corresponding to an 2g acceleration full-scale range. |
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Threshold to start the pulse-event detection procedure on the Z-axis. Threshold values for each axis are unsigned 5-bit corresponding to an 2g acceleration full-scale range. |
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Enable X axis for pulse |
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Enable Y axis for pulse |
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Enable Z axis for pulse |
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single/double |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable driver for LIS2MDL I2C-based magnetometer sensor. |
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Set magnetometer sampling frequency (ODR) at runtime (default: 10 Hz) |
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Enable SPI 4wire mode (separated MISO and MOSI lines) |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable driver for LIS3MDL I2C-based magnetometer. |
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Magnetometer full-scale range. An X value for the config represents a range of +/- X gauss. Valid values are 4, 8, 12 and 16. |
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Magnetometer output data rate expressed in samples per second. Data rates supported by the chip are 0.625, 1.25, 2.5, 5, 10, 20, 40, 80, 155, 300, 560 and 1000. |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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This module implements a kernel device driver for LiteX Timer. |
|
This option selects local APIC as the interrupt controller. |
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This option specifies the base address of the Local APIC device. |
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A special situation may occur when a processor raises its task priority to be greater than or equal to the level of the interrupt for which the processor INTR signal is currently being asserted. If at the time the INTA cycle is issued, the interrupt that was to be dispensed has become masked (programmed by software), the local APIC will deliver a spurious-interrupt vector. Dispensing the spurious-interrupt vector does not affect the ISR, so the handler for this vector should return without an EOI. From x86 manual Volume 3 Section 10.9. |
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IDT vector to use for spurious LOAPIC interrupts. Note that some arches (P6, Pentium) ignore the low 4 bits and fix them at 0xF. If this value is left at -1 the last entry in the IDT will be used. |
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This option selects LOAPIC timer as a system timer. |
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This option specifies the IRQ used by the LOAPIC timer. |
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This options specifies the IRQ priority used by the LOAPIC timer. |
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Include LoRa drivers in the system configuration. |
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System initialization priority for LoRa drivers. |
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Enable LoRa driver for Semtech SX1276. |
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Enable LED driver for LP3943. LP3943 LED driver has 16 channels each with multi-programmable states at a specified rate. Each channel can drive up to 25 mA per LED. |
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Enable LED driver for LP5562. LP5562 LED driver has 4 channels (RGBW). Each channel can drive up to 25.5 mA per LED. |
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Enable LED strip driver for daisy chains of LPD880x (LPD8803, LPD8806, or compatible) devices. Each LPD880x LED driver chip has some output channels (3 channels for LPD8803, 6 for LPD8806), whose PWM duty cycle can be set at 7 bit resolution via a reduced SPI interface (MOSI and CLK lines only). Each chip also includes data and clock out pins for daisy chaining LED strips. |
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Enable driver for LPS22HB I2C-based pressure and temperature sensor. |
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Sensor output data rate expressed in samples per second. Data rates supported by the chip are 1, 10, 25, 50, 75. |
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Enable driver for LPS22HH I2C-based pressure and temperature sensor. |
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Sensor output data rate expressed in samples per second. Data rates supported by the chip are: 0: ODR selected at runtime 1: 1Hz 2: 10Hz 3: 25Hz 4: 50Hz 5: 75Hz 6: 100Hz 7: 200Hz |
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Priority of thread used by the driver to handle interrupts. |
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Stack size of thread used by the driver to handle interrupts. |
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Use global thread |
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No trigger |
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Use own thread |
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Enable driver for LPS25HB I2C-based pressure and temperature sensor. |
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Sensor output data rate expressed in samples per second. Data rates supported by the chip are 1, 7, 13, 25. |
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Enable support for LPUART1 port in the driver. Say y here if you want to use LPUART1 device. |
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Enable driver for LSM303DLHC I2C-based triaxial magnetometer sensor. |
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0: 0.75Hz 1: 1.5 Hz 2: 3Hz 3: 7.5Hz 4: 15Hz 5: 30Hz 6: 75Hz 7: 220Hz |
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1: +/-1.3 gauss 2: +/-1.9 gauss 3: +/-2.5 gauss 4: +/-4 gauss 5: +/-4.7 gauss 6: +/-5.6 gauss 7: +/-8.1 gauss |
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Enable driver for LSM6DS0 I2C-based accelerometer and gyroscope sensor. |
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Enable/disable accelerometer X axis totally by stripping everything related in driver. |
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Enable/disable accelerometer Y axis totally by stripping everything related in driver. |
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Enable/disable accelerometer Z axis totally by stripping everything related in driver. |
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Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are 2, 4, 8 and 16. |
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Specify the default accelerometer output data rate expressed in samples per second (Hz). Data rates supported by the chip are 0, 10, 50, 119, 238, 476, 952. |
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Enable/disable temperature totally by stripping everything related in driver. |
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Enable/disable gyroscope X axis totally by stripping everything related in driver. |
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Enable/disable gyroscope Y axis totally by stripping everything related in driver. |
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Enable/disable gyroscope Z axis totally by stripping everything related in driver. |
|
Specify the default gyroscope full-scale range. An X value for the config represents a range of +/- X degree per second. Valid values are 245, 500 and 2000. |
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Specify the default gyroscope output data rate expressed in samples per second (Hz). Data rates supported by the chip are 0, 15, 60, 119, 238, 476, 952. |
|
Enable driver for LSM6DSL accelerometer and gyroscope sensor. |
|
Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are: 0: Full Scale selected at runtime 2: +/- 2g 4: +/- 4g 8: +/- 8g 16: +/- 16g |
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Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz |
|
Enable/disable temperature |
|
LIS2MDL |
|
LPS22HB |
|
Specify the default gyroscope full-scale range. An X value for the config represents a range of +/- X degree per second. Valid values are: 0: Full Scale selected at runtime 125: +/- 125dps 245: +/- 245dps 500: +/- 500dps 1000: +/- 1000dps 2000: +/- 2000dps |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz |
|
Enable/disable internal sensorhub |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LSM6DSO accelerometer and gyroscope sensor. |
|
Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are: 0: Full Scale selected at runtime 2: +/- 2g 4: +/- 4g 8: +/- 8g 16: +/- 16g |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz |
|
Enable/disable temperature |
|
Enable HTS221 as external sensor |
|
Enable LIS2MDL as external sensor |
|
Enable LPS22HB as external sensor |
|
Enable LPS22HH as external sensor |
|
Specify the default gyroscope full-scale range. An X value for the config represents a range of +/- X degree per second. Valid values are: 0: Full Scale selected at runtime 125: +/- 125dps 250: +/- 250dps 500: +/- 500dps 1000: +/- 1000dps 2000: +/- 2000dps |
|
Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz |
|
int1 |
|
int2 |
|
Enable/disable internal sensorhub. You can enable a maximum of two external sensors (if more than two are enabled the system would enumerate only the first two found) |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable driver for LSM9DS0 I2C-based gyroscope sensor. |
|
2000 DPS |
|
245 DPS |
|
500 DPS |
|
Enable alteration of full-scale attribute at runtime. |
|
190 Hz |
|
380 Hz |
|
760 Hz |
|
95 Hz |
|
Enable alteration of sampling rate frequency at runtime. |
|
Specify the internal thread stack size. |
|
Enable triggers |
|
Enable data ready trigger |
|
Enable driver for LSM9DS0 I2C-based MFD sensor. |
|
Enable/disable accelerometer totally by stripping everything related in driver. |
|
Enable accelerometer X axis |
|
Enable accelerometer Y axis |
|
Enable accelerometer Z axis |
|
16G |
|
2G |
|
4G |
|
6G |
|
8G |
|
Enable alteration of accelerometer full-scale attribute at runtime. |
|
0 Hz (power down) |
|
100 Hz |
|
12.5 Hz |
|
1600 Hz |
|
200 Hz |
|
25 Hz |
|
3.125 Hz |
|
400 Hz |
|
50 Hz |
|
6.25 Hz |
|
800 Hz |
|
Enable alteration of accelerometer sampling rate attribute at runtime. |
|
Enable/disable magnetometer totally by stripping everything related in driver. |
|
12 Gauss |
|
2 Gauss |
|
4 Gauss |
|
8 Gauss |
|
Enable alteration of magnetometer full-scale attribute at runtime. |
|
100 Hz |
|
12.5 Hz |
|
25 Hz |
|
3.125 Hz |
|
50 Hz |
|
6.25 Hz |
|
Enable alteration of magnetometer sampling rate attribute at runtime. |
|
Enable/disable temperature sensor totally by stripping everything related in driver. |
|
MAX30101 Pulse Oximeter and Heart Rate Sensor |
|
Set the ADC’s full-scale range. 0 = 7.81 pA/LSB 1 = 15.63 pA/LSB 2 = 31.25 pA/LSB 3 = 62.5 pA/LSB |
|
Set the trigger for the FIFO_A_FULL interrupt |
|
Controls the behavior of the FIFO when the FIFO becomes completely filled with data. If set, the FIFO address rolls over to zero and the FIFO continues to fill with new data. If not set, then the FIFO is not updated until FIFO_DATA is read or the WRITE/READ pointer positions are changed. |
|
Set to operate in heart rate only mode. The red LED channel is active. |
|
Set the pulse amplitude to control the LED1 (red) current. The actual measured LED current for each part can vary significantly due to the trimming methodology. 0x00 = 0.0 mA 0x01 = 0.2 mA 0x02 = 0.4 mA 0x0f = 3.1 mA 0xff = 50.0 mA |
|
Set the pulse amplitude to control the LED2 (IR) current. The actual measured LED current for each part can vary significantly due to the trimming methodology. 0x00 = 0.0 mA 0x01 = 0.2 mA 0x02 = 0.4 mA 0x0f = 3.1 mA 0xff = 50.0 mA |
|
Set the pulse amplitude to control the LED3 (green) current. The actual measured LED current for each part can vary significantly due to the trimming methodology. 0x00 = 0.0 mA 0x01 = 0.2 mA 0x02 = 0.4 mA 0x0f = 3.1 mA 0xff = 50.0 mA |
|
Set to operate in multi-LED mode. The green, red, and/or IR LED channels are active. |
|
Set which LED and pulse amplitude are active in time slot 1. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA |
|
Set which LED and pulse amplitude are active in time slot 2. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA |
|
Set which LED and pulse amplitude are active in time slot 3. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA |
|
Set which LED and pulse amplitude are active in time slot 4. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA |
|
To reduce the amount of data throughput, adjacent samples (in each individual channel) can be averaged and decimated on the chip by setting this register. Set to 0 for no averaging. 0 = 1 sample (no averaging) 1 = 2 samples 2 = 4 samples 3 = 8 samples 4 = 16 samples 5 = 32 samples 6 = 32 samples 7 = 32 samples |
|
Set to operate in SpO2 mode. The red and IR LED channels are active. |
|
Set the effective sampling rate with one sample consisting of one pulse/conversion per active LED channel. In SpO2 mode, these means one IR pulse/conversion and one red pulse/conversion per sample period. 0 = 50 Hz 1 = 100 Hz 2 = 200 Hz 3 = 400 Hz 4 = 800 Hz 5 = 1000 Hz 6 = 1600 Hz 7 = 3200 Hz |
|
Enable driver for MAX44009 light sensors. |
|
The maximum number of interrupt inputs to any aggregator in the system. |
|
This module implements a kernel device driver for the Microchip XEC series RTOS timer and provides the standard “system clock driver” interfaces. |
|
Enable driver for MCP9808 temperature sensor. |
|
MCP9808 thread priority |
|
Sensor delayed work thread stack size |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
16 MHz |
|
1 MHz |
|
250 kHz |
|
32768 Hz |
|
32 MHz |
|
4 MHz |
|
62500 Hz |
|
8 MHz |
|
Disabled |
|
If this option is set, the driver does not perform a hardware reset and the CLK_OUT frequency is not set, instead these settings are performed during the initialization of the SoC. |
|
Rocktech rk043fn02h-ct |
|
Byte alignment in the frame buffer memory pool. |
|
Maximum block size in the frame buffer memory pool. |
|
Minimum block size in the frame buffer memory pool. |
|
Number of blocks in the frame buffer memory pool. |
|
Enable this to be able to display images and text on the 5x5 LED matrix display on the BBC micro:bit. |
|
This value specifies the maximum length of strings that can be displayed using the mb_display_string() and mb_display_print() APIs. |
|
Enable config options for modem drivers. |
|
This generic command handler uses a modem interface to process incoming data and hand it back to the modem driver via callbacks defined for: - modem responses - unsolicited messages - specified handlers for current operation To configure this layer for use, create a modem_cmd_handler_data object and pass it’s reference to modem_cmd_handler_init() along with the modem_cmd_handler reference from your modem_context object. |
|
This option sets the maximum number of parameters which may be parsed by the command handler. This is also limited by the length of the match_buf (match_buf_len) field as it needs to be large enough to hold a single line of data (ending with /r). |
|
This driver allows modem drivers to communicate with an interface using custom defined protocols. Driver doesn’t inspect received data and all aspects of received protocol data are handled by application work method provided. This driver combines abstractions for: modem interface, command handler, pin config and socket handling each of which will need to be configured. |
|
Maximum number of modem contexts to handle. For most purposes this should stay at 1. |
|
Enabling this setting will turn on VERY heavy debugging from the modem context helper. Do NOT leave on for production. |
|
Specify Access Point Name, i.e. the name to identify Internet IP GPRS cellular data context. |
|
The GSM modem is initialized in POST_KERNEL using priority in the range 0-99. |
|
This setting is used in the AT+COPS command to set the MCC/MNO for the network connection context. This value is specific to the network provider and may need to be changed if auto is not selected. |
|
Enable GSM modems that support standard AT commands and PPP. |
|
UART device name the modem is connected to |
|
To configure this layer for use, create a modem_iface_uart_data object and pass it’s reference to modem_iface_uart_init() along with the modem_iface reference from your modem_context object and the UART device name. |
|
This driver allows modem drivers to communicate over UART with custom defined protocols. Driver doesn’t inspect received data and all aspects of received protocol data are handled by application via work method provided. This driver differs from the pipe UART driver in that callbacks are executed in a different work queue and data is passed around in k_pipe structures. |
|
Maximum number of modem receiver contexts to handle. For most purposes this should stay at 1. |
|
Activate shell module that provides modem utilities like sending a command to the modem UART. |
|
This layer provides much of the groundwork for keeping track of modem “sockets” throughout their lifecycle (from the initial offload API calls through the command handler call back layers). To configure this layer for use, create a modem_socket_config object with your socket data and pass it’s reference to modem_socket_init(). |
|
As the modem indicates more data is available to be received, these values are organized into “packets”. This setting limits the maximum number of packet sizes the socket can keep track of. |
|
Choose this setting to enable u-blox SARA-R4 LTE-CatM1/NB-IoT modem driver. |
|
Enable support for SARA-R4 modem |
|
This setting is used in the AT+CGDCONT command to set the APN name for the network connection context. This value is specific to the network provider and may need to be changed. |
|
u-blox SARA-R4 device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
|
This setting is used in the AT+COPS command to set the MCC/MNO for the network connection context. This value is specific to the network provider and may need to be changed if auto is not selected. |
|
Driver name |
|
Choose this setting to use a modem GPIO pin as network indication. |
|
This setting is used to configure one of the modem’s GPIO pins as a network status indication. See the manual for the gpio ids and how they map to pin numbers. |
|
This stack is used by the u-blox SARA-R4 RX thread. |
|
This stack is used by the work queue to pass off net_pkt data to the rest of the network stack, letting the rx thread continue processing data. |
|
Enable support for SARA-U2 modem |
|
Choose this setting to enable Wistron WNC-M14A2A LTE-M modem driver. NOTE: Currently the pin settings only work with FRDM K64F shield. |
|
This setting is used in the AT%PDNSET command to set the APN name for the network connection context. Normally, don’t need to change this value. |
|
WNC-M14A2A device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
|
This stack is used by the WNCM14A2A RX thread. |
|
This stack is used by the work queue to pass off net_pkt data to the rest of the network stack, letting the rx thread continue processing data. |
|
Enable driver for MPU6050 I2C-based six-axis motion tracking device. |
|
Magnetometer full-scale range. An X value for the config represents a range of +/- X g. Valid values are 2, 4, 8 and 16. |
|
Gyroscope full-scale range. An X value for the config represents a range of +/- X degrees/second. Valid values are 250, 500, 1000, 2000. |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable this config option if the AK8975 sensor is part of a MPU9150 chip. |
|
I2C address of the MPU9150. If the driver for MPU6050 is enabled, its address will be used and this option made unavailable. |
|
Enable driver for MS5607 pressure and temperature sensor. |
|
x1024 |
|
x2048 |
|
x256 |
|
x4096 |
|
x512 |
|
x1024 |
|
x2048 |
|
x256 |
|
x4096 |
|
x512 |
|
Enable driver for MS5837 pressure and temperature sensor. |
|
Multiple levels of interrupts are normally used to increase the number of addressable interrupts in a system. For example, if two levels are used, a second level interrupt aggregator would combine all interrupts routed to it into one IRQ line in the first level interrupt controller. If three levels are used, a third level aggregator combines its input interrupts into one IRQ line at the second level. The number of interrupt levels is usually determined by the hardware. (The term “aggregator” here means “interrupt controller”.) |
|
Use the host terminal (where the native_posix binary was launched) for the Zephyr console |
|
Device driver initialization priority. |
|
No current use. Kept only as there is plans to start using these drivers with the shell |
|
Zephyr’s printk messages will be directed to the host terminal stdout. |
|
This module implements a kernel device driver for the native_posix HW timer model |
|
In ms, polling period for stdin |
|
Connect this UART to its own pseudoterminal. This is the preferred option for users who want to use Zephyr’s shell. Moreover this option does not conflict with any other native_posix backend which may use the calling shell standard input/output. |
|
Connect this UART to the stdin & stdout of the calling shell/terminal which invoked the native_posix executable. This is good enough for automated testing, or when feeding from a file/pipe. Note that other, non UART messages, will also be printed to the terminal. This option should NOT be used in conjunction with NATIVE_POSIX_STDIN_CONSOLE It is strongly discouraged to try to use this option with the new shell interactively, as the default terminal configuration is NOT appropriate for interactive use. |
|
If the native_posix executable is called with the –attach_uart command line option, this will be the default command which will be run to attach a new terminal to the 1st UART. Note that this command must have one, and only one, ‘%s’ as placeholder for the pseudoterminal device name (e.g. /dev/pts/35) This is only applicable if the UART_0 is configured to use its own PTY with NATIVE_UART_0_ON_OWN_PTY. The 2nd UART will not be affected by this option. |
|
Net loopback driver |
|
Point-to-point (PPP) UART based driver |
|
This option sets the driver name |
|
This options sets the size of the UART pipe buffer where data is being read to. |
|
If you have a reliable link, then it might make sense to disable this as it takes some time to verify the received packet. |
|
Enable support for Neural Network Accelerators |
|
Enable support for nrfx QSPI driver with EasyDMA. |
|
When CONFIG_FLASH_PAGE_LAYOUT is used this driver will support that API. By default the page size corresponds to the block size (65536). Other option include the sector size (4096). |
|
Device driver initialization priority. |
|
Quad Enable bit number in Status Register |
|
Enable DPPI allocator |
|
Enable PPI allocator |
|
Enable TIMER driver |
|
Enable TIMER0 instance |
|
Enable TIMER1 instance |
|
Enable TIMER2 instance |
|
Enable TIMER3 instance |
|
Enable TIMER4 instance |
|
Enable support for nrfx WDT instance 0. |
|
Enable support for nrfx WDT instance 1. |
|
This module implements a kernel device driver for the nRF Real Time Counter NRF_RTC1 and provides the standard “system clock driver” interfaces. |
|
The number of level 2 interrupt aggregators to support. Each aggregator can manage at most MAX_IRQ_PER_AGGREGATOR level 2 interrupts. |
|
The number of level 3 interrupt aggregators to support. Each aggregator can manage at most MAX_IRQ_PER_AGGREGATOR level 3 interrupts. |
|
Enable driver for OPT3001 light sensors. |
|
Antenna connected to PA_BOOST pin. |
|
Antenna connected to PA_RFO pin. |
|
Enable LED driver for PCA9633. PCA9633 LED driver has 4 channels each with multi-programmable states. Each channel can drive up to 25 mA per LED. |
|
This option enables support for new PCI(e) drivers. |
|
Use Message-Signaled Interrupts where possible. With this option enabled, PCI(e) devices which support MSI will be configured (at runtime) to use them. This is typically required for PCIe devices to generate interrupts at all. |
|
Enable commands for debugging PCI(e) using the built-in shell. |
|
Enable board pinmux driver |
|
Enable driver for ARM V2M Beetle Pin multiplexer. |
|
Enable the TI SimpleLink CC13xx / CC26xx pinmux driver. |
|
Enable driver for ESP32 Pin multiplexer. |
|
Enable driver for ARC HSDK I/O pin mux. |
|
Pinmux driver initialization priority. Pinmux driver almost certainly should be initialized before the rest of hardware devices (which may need specific pins already configured for them), and usually after generic GPIO drivers. Thus, its priority should be between KERNEL_INIT_PRIORITY_DEFAULT and KERNEL_INIT_PRIORITY_DEVICE. There are exceptions to this rule for particular boards. Don’t change this value unless you know what you are doing. |
|
Enable driver for Intel S1000 I/O multiplexer. |
|
Enable the MCUX pinmux driver. |
|
Enable the MCUX LPC pinmux driver. |
|
Enable Port 0. |
|
Pinmux Port 0 driver name |
|
Enable Port 1. |
|
Pinmux Port 1 driver name |
|
Enable Port A. |
|
Pinmux Port A driver name |
|
Enable Port B. |
|
Pinmux Port B driver name |
|
Enable Port C. |
|
Pinmux Port C driver name |
|
Enable Port D. |
|
Pinmux Port D driver name |
|
Enable Port E. |
|
Pinmux Port E driver name |
|
The name of the pinmux driver. |
|
Enable the RV32M1 pinmux driver. |
|
Enable Port A. |
|
Pinmux Port A driver name |
|
Enable Port B. |
|
Pinmux Port B driver name |
|
Enable Port C. |
|
Pinmux Port C driver name |
|
Enable Port D. |
|
Pinmux Port D driver name |
|
Enable Port E. |
|
Pinmux Port E driver name |
|
Enable support for the Atmel SAM0 PORT pin multiplexer. |
|
Enable driver for the SiFive Freedom SOC pinmux driver |
|
SIFIVE pinmux 0 driver name |
|
Enable pin multiplexer for STM32 MCUs |
|
This option controls the priority of pinmux device initialization. Higher priority ensures that the device is initialized earlier in the startup cycle. Note that the pinmux device needs to be initialized after clock control device, but possibly before all other devices. If unsure, leave at default value 2 |
|
Enable the Microchip XEC pinmux driver. |
|
Enable Port 000-036 or what would be equivalent to Port A. |
|
Pinmux Port 000_036 driver name |
|
Enable Port 040-076 or what would be equivalent to Port B |
|
Pinmux Port 040_076 driver name |
|
Enable Port 100-136 or what would be equivalent to Port C |
|
Pinmux Port 100_136 driver name |
|
Enable Port 140-176 or what would be equivalent to Port C |
|
Pinmux Port 140_176 driver name |
|
Enable Port 200-236 or what would be equivalent to Port D |
|
Pinmux Port 200_236 driver name |
|
Enable Port 240-276 or what would be equivalent to Port E |
|
Pinmux Port 200_276 driver name |
|
Platform Level Interrupt Controller provides support for external interrupt lines defined by the RISC-V SoC; |
|
Enable driver for pms7003 particulate matter sensor. |
|
Driver name |
|
UART device |
|
This is only necessary if a ppp connection should be established with a Microsoft Windows PC. |
|
Specify a MAC address for the PPP interface in the form of six hex 8-bit chars separated by colons (e.g.: aa:33:cc:22:e2:c0). The default is an empty string, which means the code will make 00:00:5E:00:53:XX, where XX will be random. |
|
Include PS/2 drivers in system config. |
|
PS/2 device driver initialization priority. There isn’t any critical component relying on this priority at the moment. |
|
Enable the Microchip XEC PS2 IO driver. The driver also depends on the KBC 8042 keyboard controller. |
|
Enable PS2 0. |
|
Enable PS2 1. |
|
Enable options for Precision Time Protocol Clock drivers. |
|
Enable MCUX PTP clock support. |
|
Enable SAM GMAC PTP Clock support. |
|
Enable config options for PWM drivers. |
|
Enable PWM port 0 |
|
Enable PWM port 1 |
|
Enable PWM port 2 |
|
Enable PWM port 3 |
|
Enable PWM port 4 |
|
Enable driver to utilize PWM on the DesignWare Timer IP block. Care must be taken if one is also to use the timer feature, as they both use the same set of registers. |
|
Specify the device name for the DesignWare PWM driver. |
|
Enable support for i.MX pwm driver. |
|
This option enables the PWM LED driver for ESP32 family of processors. Say y if you wish to use PWM LED port on ESP32. |
|
Specify the device name for the PWM driver. |
|
Set high speed channels |
|
Enable channel 0 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 1 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 2 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 3 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 4 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 5 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 6 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 7 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Set high speed timers |
|
Set timer 0 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 1 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 2 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 3 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set low speed channels |
|
Enable channel 0 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 1 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 2 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 3 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 4 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 5 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 6 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Enable channel 7 |
|
GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39. |
|
Timer source channel, allowed values: 0 - 4. |
|
Set low speed timers |
|
Set timer 0 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 1 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 2 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Set timer 3 |
|
PWM timer precision, allowed values: 10 - 15. |
|
Set frequency |
|
Enable support for LiteX PWM driver |
|
PWM device driver initialization priority. |
|
Enable mcux pwm driver. |
|
Enable support for mcux ftm pwm driver. |
|
Enable driver to utilize PWM on the Nordic Semiconductor nRF5x series. This implementation provides up to 3 pins using one HF timer, two PPI channels per pin and one GPIOTE config per pin. |
|
Enable support for nrfx Hardware PWM driver for nRF52 MCU series. |
|
Enable driver for PCA9685 I2C-based PWM chip. |
|
Enable config options for the PCA9685 I2C-based PWM chip #0. |
|
Specify the device name for the PCA9685 I2C-based PWM chip #0. |
|
Specify the I2C slave address for the PCA9685 I2C-based PWM chip #0. |
|
Specify the device name of the I2C master device to which this PCA9685 chip #0 is binded. |
|
Device driver initialization priority. |
|
Loop count for PWM Software Reset when disabling PWM channel. |
|
Enable the RV32M1 TPM PWM driver. |
|
Enable PWM driver for Atmel SAM MCUs. |
|
Enable the PWM related shell commands. |
|
Enable the PWM driver for the SiFive Freedom platform |
|
SiFive PWM Driver Initialization Priority |
|
This option enables the PWM driver for STM32 family of processors. Say y if you wish to use PWM port on STM32 MCU. |
|
Enable output for PWM1 in the driver. Say y here if you want to use PWM1 output. |
|
Enable output for PWM10 in the driver. Say y here if you want to use PWM10 output. |
|
Enable output for PWM11 in the driver. Say y here if you want to use PWM11 output. |
|
Enable output for PWM12 in the driver. Say y here if you want to use PWM12 output. |
|
Enable output for PWM13 in the driver. Say y here if you want to use PWM13 output. |
|
Enable output for PWM14 in the driver. Say y here if you want to use PWM14 output. |
|
Enable output for PWM15 in the driver. Say y here if you want to use PWM15 output. |
|
Enable output for PWM16 in the driver. Say y here if you want to use PWM16 output. |
|
Enable output for PWM17 in the driver. Say y here if you want to use PWM17 output. |
|
Enable output for PWM18 in the driver. Say y here if you want to use PWM18 output. |
|
Enable output for PWM19 in the driver. Say y here if you want to use PWM19 output. |
|
Enable output for PWM2 in the driver. Say y here if you want to use PWM2 output. |
|
Enable output for PWM20 in the driver. Say y here if you want to use PWM20 output. |
|
Enable output for PWM3 in the driver. Say y here if you want to use PWM3 output. |
|
Enable output for PWM4 in the driver. Say y here if you want to use PWM4 output. |
|
Enable output for PWM5 in the driver. Say y here if you want to use PWM5 output. |
|
Enable output for PWM6 in the driver. Say y here if you want to use PWM6 output. |
|
Enable output for PWM7 in the driver. Say y here if you want to use PWM7 output. |
|
Enable output for PWM8 in the driver. Say y here if you want to use PWM8 output. |
|
Enable output for PWM9 in the driver. Say y here if you want to use PWM9 output. |
|
Enable driver to utilize PWM on the Microchip XEC IP block. |
|
Enable support for nrfx QDEC driver for nRF MCU series. |
|
Qemu (without -icount) has trouble keeping time when the host process needs to timeshare. The host OS will routinely schedule out a process at timescales equivalent to the guest tick rate. With traditional ticks delivered regularly by the hardware, that’s mostly OK as it looks like a late interrupt. But in tickless mode, the driver needs some CPU in order to schedule the tick in the first place. If that gets delayed across a tick boundary, time gets wonky. This tunable is a hint to the driver to disable tickless accounting on qemu. Use it only on tests that are known to have problems. |
|
Emit console messages to a RAM buffer “ram_console” which can be examined at runtime with a debugger. Useful in board bring-up if there aren’t any working serial drivers. |
|
Size of the RAM console buffer. Messages will wrap around if the length is exceeded. |
|
This module implements a kernel device driver for the generic RISCV machine timer driver. It provides the standard “system clock driver” interfaces. |
|
Emit console messages to a RAM buffer that is then read by the Segger J-Link software and displayed on a computer in real-time. Requires support for Segger J-Link on the companion IC onboard. |
|
Number of TX retries before dropping the byte and assuming that RTT session is inactive. |
|
Sleep period between TX retry attempts. During RTT session, host pulls data periodically. Period starts from 1-2 milliseconds and can be increased if traffic on RTT increases (also from host to device). In case of heavy traffic data can be lost and it may be necessary to increase delay or number of retries. |
|
If enabled RTT console will busy wait between TX retries when console assumes that RTT session is active. In case of heavy traffic data can be lost and it may be necessary to increase delay or number of retries. |
|
Select this option to enable support for the RV32M1 INTMUX driver. This provides a level 2 interrupt controller for the SoC. The INTMUX peripheral combines level 2 interrupts into eight channels; each channel has its own level 1 interrupt to the core. |
|
Enable support for INTMUX channel 0. |
|
Enable support for INTMUX channel 1. |
|
Enable support for INTMUX channel 2. |
|
Enable support for INTMUX channel 3. |
|
Enable support for INTMUX channel 4. |
|
Enable support for INTMUX channel 5. |
|
Enable support for INTMUX channel 6. |
|
Enable support for INTMUX channel 7. |
|
Boot time initialization priority for INTMUX driver. Don’t change the default unless you know what you are doing. |
|
This module implements a kernel device driver for using the LPTMR peripheral as the system clock. It provides the standard “system clock driver” interfaces. |
|
Enable EIC driver for SAM0 series of devices. This is required for GPIO interrupt support. |
|
This module implements a kernel device driver for the Atmel SAM0 series Real Time Counter and provides the standard “system clock driver” interfaces. |
|
Enable SDL based emulated display compliant with display driver API. |
|
ARGB 8888 |
|
BGR 565 |
|
Mono Black=0 |
|
Mono Black=1 |
|
RGB 565 |
|
RGB 888 |
|
SDL display device name |
|
X resolution for SDL display |
|
Y resolution for SDL display |
|
Size of the buffer for terminal input of target, from host |
|
Size of the buffer for terminal output of target, up to host |
|
Maximum number of down-buffers |
|
Maximum number of up-buffers |
|
Use a simple byte-loop instead of standard memcpy |
|
Block: Wait until there is space in the buffer. |
|
Skip. Do not block, output nothing. |
|
Trim: Do not block, output as much as fits. |
|
Size of buffer for RTT printf to bulk-send chars via RTT |
|
Include sensor drivers in system config |
|
Sensor initialization priority. |
|
This shell provides access to basic sensor data. |
|
Enable options for serial drivers. |
|
This is an option to be enabled by individual serial driver to signal that there is a serial driver. This is being used by other drivers which are dependent on serial. |
|
This is an option to be enabled by individual serial driver to signal that the driver and hardware supports async operation. |
|
This is an option to be enabled by individual serial driver to signal that the driver and hardware supports interrupts. |
|
Include shared interrupt support in system. Shared interrupt support is NOT required in most systems. If in doubt answer no. |
|
Provide an instance of the shared interrupt driver when system configuration requires that multiple devices share an interrupt. |
|
Provide an instance of the shared interrupt driver when system configuration requires that multiple devices share an interrupt. |
|
Shared IRQ are initialized on POST_KERNEL init level. They have to be initialized before any device that uses them. |
|
Configures the maximum number of clients allowed per shared instance of the shared interrupt driver. To conserve RAM set this value to the lowest practical value. |
|
Enable driver for SHT3xD temperature and humidity sensors. |
|
0.5 |
|
1 |
|
10 |
|
2 |
|
4 |
|
periodic data acquisition |
|
high |
|
low |
|
medium |
|
single shot |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable I2C-based driver for Si7006 Temperature and Humidity Sensor. |
|
Enable driver for SI7060 temperature sensors. |
|
If enabled, SPI 0 is reserved for accessing the SPI flash ROM and a driver interface won’t be instantiated for SPI 0. Beware disabling this option on HiFive 1! The SPI flash ROM is where the program is stored, and if this driver initializes the interface for peripheral control the FE310 will crash on boot. |
|
SLIP driver |
|
This option sets the driver name |
|
Specify a MAC address for the SLIP interface in the form of six hex 8-bit chars separated by colons (e.g.: aa:33:cc:22:e2:c0). The default is an empty string, which means the code will make 00:00:5E:00:53:XX, where XX will be random. |
|
This option enables statistics support for SLIP driver. |
|
In TAP the Ethernet frames are transferred over SLIP. |
|
Enable Silicon Labs Gecko series internal flash driver. |
|
Enables the MCUX flash shim driver. WARNING: This driver will disable the system interrupts for the duration of the flash erase/write operations. This will have an impact on the overall system performance - whether this is acceptable or not will depend on the use case. |
|
Enables the Nios-II QSPI flash driver. |
|
Specify the device name for the QSPI flash driver. |
|
Enables Nordic Semiconductor nRF flash driver. |
|
When this option is enabled writing chunks less than minimal write block size parameter (imposed by manufacturer) is possible but operation is more complex and requires basic user knowledge about NVMC controller. |
|
Enable synchronization between flash memory driver and radio. |
|
Enable operations on UICR. Once enabled UICR are written or read as ordinary flash memory. Erase is possible for whole UICR at once. |
|
Enables the RV32M1 flash shim driver. WARNING: This driver will disable the system interrupts for the duration of the flash erase/write operations. This will have an impact on the overall system performance - whether this is acceptable or not will depend on the use case. |
|
Enable the Atmel SAM series internal flash driver. |
|
Enable the Atmel SAM0 series internal flash driver. |
|
Emulate a device with byte-sized pages by doing a read/modify/erase/write. |
|
Enable STM32F0x, STM32F3x, STM32F4x, STM32F7x, STM32L4x, STM32WBx, STM32G0x or STM32G4x series flash driver. |
|
Allow enabling the nRF SPI Master with EasyDMA, despite Product Anomaly Notice 58 (SPIM: An additional byte is clocked out when RXD.MAXCNT == 1 and TXD.MAXCNT <= 1). Without this override, the SPI Master is only available without EasyDMA. Note that the ‘SPIM’ and ‘SPIS’ drivers use EasyDMA, while the ‘SPI’ driver does not. Use this option ONLY if you are certain that transactions with RXD.MAXCNT == 1 and TXD.MAXCNT <= 1 will NOT be executed. |
|
Enable support for the SPI hardware bus. |
|
Enable SPI controller port 0. |
|
Over-read character. Character clocked out after an over-read of the transmit buffer. |
|
Enable nRF SPI Master without EasyDMA on port 0. |
|
Enable nRF SPI Master with EasyDMA on port 0. |
|
Enable nRF SPI Slave with EasyDMA on port 0. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM. |
|
This sets the supported operation modes at runtime, by the SPI port 0, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 1. |
|
Over-read character. Character clocked out after an over-read of the transmit buffer. |
|
Enable nRF SPI Master without EasyDMA on port 1. |
|
Enable nRF SPI Master with EasyDMA on port 1. |
|
Enable nRF SPI Slave with EasyDMA on port 1. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM. |
|
This sets the supported operation modes at runtime, by the SPI port 1, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 2. |
|
Over-read character. Character clocked out after an over-read of the transmit buffer. |
|
Enable nRF SPI Master without EasyDMA on port 2. |
|
Enable nRF SPI Master with EasyDMA on port 2. |
|
Enable nRF SPI Slave with EasyDMA on port 2. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM. |
|
This sets the supported operation modes at runtime, by the SPI port 2, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 3. |
|
Over-read character. Character clocked out after an over-read of the transmit buffer. |
|
Number of 64 MHz clock cycles (15.625 ns) delay from the sampling edge of SCK (leading or trailing, depending on the CPHA setting used) until the input serial data on MISO is actually sampled. |
|
Enable nRF SPI Master with EasyDMA on port 3. |
|
Enable nRF SPI Slave with EasyDMA on port 3. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM. |
|
This sets the supported operation modes at runtime, by the SPI port 3, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 4. |
|
Over-read character. Character clocked out after an over-read of the transmit buffer. |
|
Number of 64 MHz clock cycles (15.625 ns) delay from the sampling edge of SCK (leading or trailing, depending on the CPHA setting used) until the input serial data on MISO is actually sampled. |
|
Enable nRF SPI Master with EasyDMA on port 4. |
|
This sets the supported operation modes at runtime, by the SPI port 4, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 5. |
|
This sets the supported operation modes at runtime, by the SPI port 5, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 6. |
|
This sets the supported operation modes at runtime, by the SPI port 6, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 7. |
|
This sets the supported operation modes at runtime, by the SPI port 7, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 8. |
|
This sets the supported operation modes at runtime, by the SPI port 8, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
This option enables the asynchronous API calls. |
|
Enable support for the TI SimpleLink CC13xx / CC26xx SPI peripheral |
|
Enable support for Designware’s SPI controllers. |
|
In some case, e.g. ARC HS Development kit, the peripheral space of DesignWare SPI only allows word access, byte access will raise exception. |
|
SPI IP block registers are part of user extended auxiliary registers and thus their access is different than memory mapped registers. |
|
Corresponds to the SSI_TX_FIFO_DEPTH and SSI_RX_FIFO_DEPTH of the DesignWare Synchronous Serial Interface. Depth ranges from 2-256. |
|
Enable clock gating |
|
Clock controller’s subsystem |
|
Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated. |
|
Enable clock gating |
|
Clock controller’s subsystem |
|
Single interrupt line for all interrupts |
|
Enable clock gating |
|
Clock controller’s subsystem |
|
Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated. |
|
Enable clock gating |
|
Clock controller’s subsystem |
|
Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated. |
|
SPI NOR Flash Winbond W25QXXDV |
|
This is the device ID of the flash chip to use, which is 0x00ef4015 for the W25QXXDV |
|
SPI flash device name |
|
This is the flash capacity in bytes. |
|
This is the wait delay (in us) to allow for CS switching to take effect |
|
This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic. |
|
Device driver initialization priority. Device is connected to SPI bus, it has to be initialized after SPI driver. |
|
This is the maximum size of a page program operation. Writing data over this page boundary will split the write operation into two pages. |
|
Enable the SPI peripherals on Gecko |
|
Device driver initialization priority. |
|
Enable the SPI peripherals on LiteX |
|
Enable support for mcux spi driver. |
|
Enable support for mcux flexcomm spi driver. |
|
Enable support for mcux spi driver. |
|
SPI NOR Flash |
|
This is the wait delay (in us) to allow for CS switching to take effect |
|
When CONFIG_FLASH_PAGE_LAYOUT is used this driver will support that API. By default the page size corresponds to the block size (65536). Other options include the 32K-byte erase size (32768), the sector size (4096), or any non-zero multiple of the sector size. |
|
Where supported deep power-down mode can reduce current draw to as little as 0.1% of standby current. However it takes some milliseconds to enter and exit from this mode. Select this option for applications where device power management is not enabled, the flash remains inactive for long periods, and when used the impact of waiting for mode enter and exit delays is acceptable. |
|
Device driver initialization priority. Device is connected to SPI bus, it has to be initialized after SPI driver. |
|
Enable support for nrfx SPI drivers for nRF MCU series. Peripherals with the same instance ID cannot be used together, e.g. SPI_0 and I2C_0. You may need to disable I2C_0 or I2C_1. |
|
SPIM peripherals cannot transmit data directly from flash. Therefore, a buffer in RAM needs to be provided for each instance of SPI driver using SPIM peripheral, so that the driver can copy there a chunk of data from flash and transmit it. The size is specified in bytes. A size of 0 means that this feature should be disabled, and the application must then take care of not supplying buffers located in flash to the driver, otherwise such transfers will fail. |
|
Enable the Simple SPI controller |
|
Enable the RV32M1 LPSPI driver. |
|
Enable support for the SAM SPI driver. |
|
Enable support for the SAM0 SERCOM SPI driver. |
|
Enable SPI0 at boot |
|
PA11 |
|
PB2 |
|
PA31 |
|
PA9 |
|
PB14 |
|
PC4 |
|
PD25 |
|
PA10 |
|
PA30 |
|
PB2 |
|
PD12 |
|
PA22 |
|
PA3 |
|
PA5 |
|
PD27 |
|
Enable SPI1 at boot |
|
PC25 |
|
PC28 |
|
PD0 |
|
PC29 |
|
PD1 |
|
PC30 |
|
PD2 |
|
Enable the SPI peripherals on SiFive Freedom processors |
|
Enables Driver SPI slave operations. Slave support depends on the driver and the hardware it runs on. |
|
Enable SPI support on the STM32 family of processors. |
|
Enable Interrupt support for the SPI Driver of STM32 family. |
|
Use Slave Select pin instead of software Slave Select. |
|
Enable support for the Microchip XEC QMSPI driver. |
|
Enable driver for SSD1306 display driver. |
|
Default SSD1306 controller |
|
SSD16XX default contrast. |
|
SSD16XX reverse video mode. |
|
Enable SH1106 compatible mode |
|
Enable driver for SSD16XX compatible controller. |
|
Enable driver for ST7789V display driver. |
|
RGB565 |
|
RGB888 |
|
LPTIM clock value |
|
Use LSE as LPTIM clock |
|
Use LSI as LPTIM clock |
|
LPTIM AutoReload value |
|
This module implements a kernel device driver for the LowPower Timer and provides the standard “system clock driver” interfaces. |
|
Enable driver for STTS751 I2C-based temperature sensor. |
|
Sensor output data rate expressed in conversions per second. Data rates supported by the chip are: 0: 1 conv every 16 sec 1: 1 conv every 8 sec 2: 1 conv every 4 sec 3: 1 conv every 2 sec 4: 1 conv every sec 5: 2 convs every sec 6: 4 convs every sec 7: 8 convs every sec 8: 16 convs every sec 9: 32 convs every sec |
|
HIGH temperature threshold to trigger an alarm |
|
LOW temperature threshold to trigger an alarm |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Programmable Interrupt Controller for the SweRV EH1 RISC-V CPU; |
|
Enable driver for SX9500 I2C-based SAR proximity sensor. |
|
The SX9500 offers 4 separate proximity channels. Choose which one you are using. Valid numbers are 0 to 3. |
|
Thread priority |
|
Sensor delayed work thread stack size |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
This option enables the sys_clock_disable() API in the kernel. It is needed by some subsystems (which will automatically select it), but is rarely needed by applications. |
|
This options can be used to set a specific initialization priority value for the system clock driver. As driver initialization might need the clock to be running already, you should let the default value as it is (0). |
|
When true, the timer driver is not required to maintain a correct system uptime count when the system enters idle. Some platforms may take advantage of this to reduce the overhead from regular interrupts required to handle counter wraparound conditions. |
|
Enable driver for NXP Kinetis temperature sensor. |
|
ADC oversampling to use for the temperature sensor and bandgap voltage readings. Oversampling can help in providing more stable readings. |
|
ADC resolution to use for the temperature sensor and bandgap voltage readings. |
|
Enable driver for nRF5 temperature sensor. |
|
Enable driver for the TH02 temperature sensor. |
|
Timer drivers should select this flag if they are capable of supporting tickless operation. That is, a call to z_clock_set_timeout() with a number of ticks greater than one should be expected not to produce a call to z_clock_announce() (really, not to produce an interrupt at all) until the specified expiration. |
|
The dualtimer (DTMR) present in the platform is used as a timer. This option enables the support for the timer. |
|
The drivers select this option automatically when needed. Do not modify this unless you have a very good reason for it. |
|
The timers (TMR) present in the platform are used as timers. This option enables the support for the timers. |
|
Enable driver for TI temperature and humidity sensors. |
|
Enable driver for TMP007 infrared thermopile sensors. |
|
Priority of thread used by the driver to handle interrupts. |
|
Stack size of thread used by the driver to handle interrupts. |
|
Use global thread |
|
No trigger |
|
Use own thread |
|
Enable the driver for Texas Instruments TMP112 High-Accuracy Digital Temperature Sensors. The TMP102 is compatible with the TMP112 but is less accurate and has been successfully tested with this driver. |
|
Enable driver for TMP116 temperature sensor. |
|
The x86 implementation of LOAPIC k_cycle_get_32() relies on the x86 TSC. This runs at the CPU speed and not the bus speed. If set to 0, the value of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC will be used instead; many MCUs these values are the same. |
|
This option enables UART Asynchronous API support on port 0. |
|
If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up. |
|
This option enables UART interrupt support on port 0. |
|
Enable flow control. If selected, additionally two pins, RTS and CTS have to be configured. |
|
If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel |
|
Timer instance |
|
Enable parity bit. |
|
Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC. |
|
Enable nRF UART without EasyDMA on port 0. |
|
Enable nRF UART with EasyDMA on port 0. |
|
Enable support for USART1 port in the driver. Say y here if you want to use USART1 device. |
|
Enable support for UART10 port in the driver. Say y here if you want to use UART10 device. |
|
This option enables UART Asynchronous API support on port 1. |
|
If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up. |
|
This option enables UART interrupt support on port 1. |
|
Enable flow control. If selected, additionally two pins, RTS and CTS have to be configured. |
|
If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel |
|
Timer instance |
|
Enable parity bit. |
|
Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC. |
|
Enable nRF UART with EasyDMA on port 1. |
|
Enable support for USART2 port in the driver. Say y here if you want to use USART2 device. |
|
This option enables UART Asynchronous API support on port 2. |
|
If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up. |
|
This option enables UART interrupt support on port 2. |
|
Enable flow control. If selected, additionally two pins, RTS and CTS have to be configured. |
|
If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel |
|
Timer instance |
|
Enable parity bit. |
|
Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC. |
|
Enable nRF UART with EasyDMA on port 2. |
|
Enable support for USART3 port in the driver. Say y here if you want to use USART3 device. |
|
This option enables UART Asynchronous API support on port 3. |
|
If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up. |
|
This option enables UART interrupt support on port 3. |
|
Enable flow control. If selected, additionally two pins, RTS and CTS have to be configured. |
|
If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel |
|
Timer instance |
|
Enable parity bit. |
|
Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC. |
|
Enable nRF UART with EasyDMA on port 3. |
|
Enable support for U(S)ART4 port in the driver. Say y here if you want to use U(S)ART4 device. |
|
Enable support for U(S)ART5 port in the driver. Say y here if you want to use U(S)ART5 device. |
|
Enable support for USART6 port in the driver. Say y here if you want to use USART6 device. |
|
Enable support for U(S)ART7 port in the driver. Say y here if you want to use U(S)ART7 device. |
|
Enable support for U(S)ART8 port in the driver. Say y here if you want to use U(S)ART8 device. |
|
Enable support for UART9 port in the driver. Say y here if you want to use UART9 device. |
|
Enable the Altera JTAG UART driver, built in to many Nios II CPU designs. |
|
This option enables new asynchronous UART API. |
|
Enable the TI SimpleLink CC13xx / CC26xx UART driver. |
|
Enable UART 0. |
|
Enable UART 1. |
|
This option enables the CC32XX UART driver, for UART_0. |
|
This option enables the UART driver for ARM CMSDK APB UART. |
|
Enable this option to use one UART for console. Make sure CONFIG_UART_CONSOLE_ON_DEV_NAME is also set correctly. |
|
This option allows a debug server agent such as GDB to take over the handling of traffic that goes through the console logic. The debug server looks at characters received and decides to handle them itself if they are some sort of control characters, or let the regular console code handle them if they are of no special significance to it. |
|
Device driver initialization priority. Console has to be initialized after the UART driver it uses. |
|
Enables the UART console to receive mcumgr frames for image upgrade and device management. When enabled, the UART console does not process mcumgr frames, but it hands them up to a higher level module (e.g., the shell). If unset, incoming mcumgr frames are dropped. |
|
This option specifies the name of UART device to be used for UART console. |
|
This enables the API to send extra commands to drivers. This allows drivers to expose hardware specific functions. Says no if not sure. |
|
Enable the ESP32 UART using ROM routines. |
|
Enable the Gecko uart driver. |
|
This option enables the UART driver for NXP i.MX7 family processors. |
|
Enable support for UART1 port in the driver. Say y here if you want to use UART1 device. |
|
Enable support for UART2 port in the driver. Say y here if you want to use UART2 device. |
|
Enable support for UART3 port in the driver. Say y here if you want to use UART3 device. |
|
Enable support for UART4 port in the driver. Say y here if you want to use UART4 device. |
|
Enable support for UART5 port in the driver. Say y here if you want to use UART5 device. |
|
Enable support for UART6 port in the driver. Say y here if you want to use UART6 device. |
|
Enable support for UART7 port in the driver. Say y here if you want to use UART7 device. |
|
This option enables interrupt support for UART allowing console input and other UART based drivers. |
|
This enables the API for apps to control the serial line, such as baud rate, CTS and RTS. Implementation is up to individual driver. Says no if not sure. |
|
This option enables LiteUART serial driver. |
|
Enable the mcumgr UART driver. This driver allows the application to communicate over UART using the mcumgr protocol for image upgrade and device management. The driver doesn’t inspect received data (as contrary to console UART driver) and all aspects of received protocol data are handled by an application provided callback. |
|
This option specifies the name of UART device to be used for mcumgr UART. |
|
Specifies the number of the mcumgr UART receive buffers. Receive buffers hold received mcumgr fragments prior to reassembly. This setting’s value must satisfy the following relation: UART_MCUMGR_RX_BUF_COUNT * UART_MCUMGR_RX_BUF_SIZE >= MCUMGR_SMP_UART_MTU |
|
Specifies the size of the mcumgr UART receive buffer, in bytes. This value must be large enough to accommodate any line sent by an mcumgr client. |
|
Enable the MCUX uart driver. |
|
Enable UART 0. |
|
Enable UART 1. |
|
Enable UART 2. |
|
Enable UART 3. |
|
Enable UART 4. |
|
Enable UART 5. |
|
Enable the MCUX USART driver. |
|
Enable USART 0. |
|
Enable the MCUX LPSCI driver. |
|
Enable UART 0. |
|
Enable the MCUX LPUART driver. |
|
Enable UART 0. |
|
Enable UART 1. |
|
Enable UART 2. |
|
Enable UART 3. |
|
Enable UART 4. |
|
This option enables the Mi-V serial driver. |
|
This tells the driver to configure the UART port at boot, depending on the additional configuration options below. |
|
This option enables the MSP432P4XX UART driver, for UART_0. |
|
This enables a UART driver for the POSIX ARCH with up to 2 UARTs. For the first UART port, the driver can be configured to either connect to the terminal from which native_posix was run, or into one dedicated pseudoterminal for that UART. |
|
Useful if you need to have another serial connection to host. This is used for example in PPP (Point-to-Point Protocol) implementation. |
|
This is the device name for UART, and is included in the device struct. |
|
Enable support for nrfx UART drivers for nRF MCU series. Peripherals with the same instance ID cannot be used together, e.g. UART_0 and UARTE_0. |
|
This option enables the NS16550 serial driver. This driver can be used for the serial hardware available on x86 boards. |
|
In some case, e.g. ARC HS Development kit, the peripheral space of ns 16550 (DesignWare UART) only allows word access, byte access will raise exception. |
|
This enables the API for apps to send commands to driver. Says n if not sure. |
|
This enables the API for apps to control the serial line, such as CTS and RTS. Says n if not sure. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
Options used for port initialization. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
Options used for port initialization. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
Options used for port initialization. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
Options used for port initialization. |
|
This enables support for 64-bytes FIFO if UART controller is 16750. |
|
This enables the UART driver for the MetaWare nSim simulator. |
|
Enable pipe UART driver. This driver allows application to communicate over UART with custom defined protocol. Driver doesn’t inspect received data (as contrary to console UART driver) and all aspects of received protocol data are handled by application provided callback. |
|
This option specifies the name of UART device to be used for pipe UART. |
|
This option enables the UART driver for the PL011 |
|
Build the driver to utilize UART controller Port 0. |
|
When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to the UART driver. |
|
Build the driver to utilize UART controller Port 1. |
|
When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to the UART driver. |
|
This option enables the UART driver for PSoC6 family of processors. |
|
Enable support for UART_5 on port 5 in the driver. |
|
Enable support for UART_6 on port 12 in the driver. |
|
This option enables access RTT channel as UART device. |
|
Enable UART on (default) RTT channel 0. Default channel has to be configured in non-blocking skip mode. |
|
Enable UART on RTT channel 1 |
|
Size of the RTT down buffer for UART 1 reception. |
|
Size of the RTT up buffer for UART 1 transmission. |
|
Enable UART on RTT channel 2 |
|
Size of the RTT down buffer for UART 2 reception. |
|
Size of the RTT up buffer for UART 2 transmission. |
|
Enable UART on RTT channel 3 |
|
Size of the RTT down buffer for UART 3 reception. |
|
Size of the RTT up buffer for UART 3 transmission. |
|
Enable the RV32M1 LPUART driver. |
|
Enable UART 0. |
|
Enable UART 1. |
|
Enable UART 2. |
|
Enable UART 3. |
|
This option enables the UARTx driver for Atmel SAM MCUs. |
|
This option enables the SERCOMx USART driver for Atmel SAM0 MCUs. |
|
Enable UART0 at boot. |
|
Enable UART1 at boot. |
|
PA4 |
|
PA6 |
|
PD26 |
|
Enable UART2 at boot |
|
Enable UART3 at boot |
|
PD30 |
|
PD31 |
|
Enable UART4 at boot |
|
PD19 |
|
PD3 |
|
This option enables the SiFive Freedom serial driver. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
Port 0 Interrupt Priority |
|
Port 0 RX Threshold at which the RX FIFO interrupt triggers. |
|
Port 0 TX Threshold at which the TX FIFO interrupt triggers. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
Port 1 Interrupt Priority |
|
Port 1 RX Threshold at which the RX FIFO interrupt triggers. |
|
Port 1 TX Threshold at which the TX FIFO interrupt triggers. |
|
This option enables the Stellaris serial driver. This specific driver can be used for the serial hardware available at the Texas Instrument LM3S6965 board. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
This option enables the UART driver for STM32 family of processors. Say y if you wish to use serial port on STM32 MCU. |
|
This option enables the UART driver for Xilinx MPSoC platforms. |
|
This option enables the USARTx driver for Atmel SAM MCUs. |
|
Enable USART0 at boot |
|
Enable USART1 at boot |
|
Enable USART2 at boot |
|
Enable USB drivers. |
|
Kinetis and RT EHCI USB Device Controller Driver. |
|
SAM family USB HS device controller Driver. |
|
SAM0 family USB device controller Driver. |
|
Enable USB support on the STM32 F0, F1, F2, F3, F4, F7, L0, L4 and G4 family of processors. |
|
Say Y if your board uses USB DISCONNECT pin to enable the pull-up resistor on USB DP. |
|
Designware USB Device Controller Driver. |
|
Indicates whether or not USB specification version 2.0 is supported |
|
Kinetis USB Device Controller Driver. |
|
Native Posix USB Device Controller Driver. |
|
nRF USB Device Controller Driver |
|
Size of the driver’s internal event queue. Required size will depend on number of endpoints (class instances) in use. |
|
Size of the stack for the work queue thread that is used in the driver for handling the events from the USBD ISR, i.e. executing endpoint callbacks and providing proper notifications to the USB device stack. |
|
Enable this option to use the USB UART for console output. The output can be viewed from the USB host via /dev/ttyACM* port. Note that console inputs from the USB UART are not functional yet. Also since the USB layer currently doesn’t support multiple interfaces, this shouldn’t be selected in conjunction with, say, USB Mass Storage. |
|
Enable this option to use flow control on the console. The uart console waits until the DTR is asserted by the host. Note: Disabling this might lead to missing console prints. |
|
Enable Segger J-Link RTT libraries for platforms that support it. Selection of this option enables use of RTT for various subsystems. Note that by enabling this option, RTT buffers consume more RAM. |
|
IRQ implementation for LiteX VexRiscv |
|
Enable support for the VIDEO. |
|
Alignment of the video pool’s buffer |
|
Number of maximum sized buffer in the video pool |
|
Size of the largest buffer in the video pool |
|
NXP MCUX CMOS Sensor Interface (CSI) driver |
|
Enable driver for MT9M114 CMOS digital image sensor device. |
|
Enable video pattern generator (for testing purposes). |
|
Enable driver for VL53L0X I2C-based time of flight sensor. |
|
Threshold used for proximity detection when sensor is used with SENSOR_CHAN_PROX. |
|
Include support for watchdogs. |
|
Enable CMSDK APB Watchdog (WDOG_CMSDK_APB) Driver for ARM family of MCUs. |
|
Enable this setting to allow WDOG to be automatically started during device initialization. Note that once WDOG is started it must be reloaded before the counter reaches 0, otherwise the MCU will be reset. |
|
Set the IRQ line used by the WDT device. Very few lines can be chosen here, as it must be a level 4 interrupt. |
|
Set the IRQ line used by the WDT device. Very few lines can be chosen here, as it must be a level 4 interrupt. |
|
Disable watchdog at Zephyr system startup. |
|
Enable WDT driver for ESP32. |
|
Enable WDOG driver for Silicon Labs Gecko MCUs. |
|
Enable the mcux wdog driver. |
|
Enable the mcux wdog32 driver. |
|
Enable multistage operation of watchdog timeouts. |
|
Enable support for nrfx WDT driver for nRF MCU series. |
|
Enable WDT driver for Atmel SAM MCUs. |
|
Enable WDT driver for Atmel SAM0 MCUs. |
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Enable WDT driver for Microchip XEC MCU series. |
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add support for Wi-Fi Drivers |
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Inventek eS-WiFi support |
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Driver name |
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This option sets the priority of the esWiFi threads. Do not touch it unless you know what you are doing. |
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Wi-Fi device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system. |
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Enable support for Full-MAC Wi-Fi devices. |
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SimpleLink Wi-Fi driver support |
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SimpleLink uses the “FastConnect” feature to reconnect to the previously connected AP on startup. Should the Wi-Fi connection timeout, the SimpleLink driver will fail to initialize, and LOG an error. |
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Set the maximum size of a network packet going through the chip. This sets the size of each buffer, in each buffer pool. Do not modify it unless you know what you are doing. |
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The number of times, separated by a one second interval, to retry a request for the network list. |
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Driver name |
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The number of results to request on a Wi-Fi scan operation. Actual number returned may be less. Maximum is 30. |
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WINC1500 driver support |
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Set the number of buffer the driver will have access to in each of its buffer pools. |
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This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic. |
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Set the maximum size of a network packet going through the chip. This sets the size of each buffer, in each buffer pools. Do not modify it unless you know what you are doing. |
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Driver name |
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Set the number of sockets that can be managed through the driver and the chip. |
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Region Asia |
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Region Europe |
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Region North America |
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This option sets the priority of the thread handling WINC1500 HAL callbacks. Do not touch it unless you know what you are doing. |
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This option sets the size of the stack used by the thread handling WINC1500 HAL callbacks. Do not touch it unless you know what you are doing. |
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Enable LED strip driver for daisy chains of WS2812-ish (or WS2812B, WS2813, SK6812, or compatible) devices. |
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The GPIO driver does bit-banging with inline assembly, and is not available on all SoCs. |
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The SPI driver is portable, but requires significantly more memory (1 byte of overhead per bit of pixel data). |
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Enable WWDG driver for STM32 line of MCUs |
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If your local APIC supports x2APIC mode, turn this on. |
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This module implements a kernel device driver for the Xilinx ZynqMP platform provides the standard “system clock driver” interfaces. If unchecked, no timer will be used. |
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This is the index of TTC timer picked to provide system clock. |
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Device driver initialization priority. |
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Use simulator console to print messages. |
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Enables a system timer driver for Xtensa based on the CCOUNT and CCOMPARE special registers. |
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Index of the CCOMPARE register (and associated interrupt) used for the system timer. Xtensa CPUs have hard-configured interrupt priorities associated with each timer, and some of them can be unmaskable (and thus not usable by OS code that need synchronization, like the timer subsystem!). Choose carefully. Generally you want the timer with the highest priority maskable interrupt. |