Zephyr API Documentation
3.0.0
A Scalable Open Source RTOS
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3.0.0 |
Go to the source code of this file.
Macros | |
#define | PCA9420_SW1_VOLTAGE_RANGE |
#define | PCA9420_SW2_VOLTAGE_RANGE |
#define | PCA9420_LDO1_VOLTAGE_RANGE |
#define | PCA9420_LDO2_VOLTAGE_RANGE |
#define | PCA9420_CURRENT_LIMIT_LEVELS |
#define | PCA9420_DEV_INFO 0x00U |
Device Information register. More... | |
#define | PCA9420_TOP_INT 0x01U |
Top level interrupt status. More... | |
#define | PCA9420_SUB_INT0 0x02U |
Sub level interrupt 0 indication. More... | |
#define | PCA9420_SUB_INT0_MASK 0x03U |
Sub level interrupt 0 mask. More... | |
#define | PCA9420_SUB_INT1 0x04U |
Sub level interrupt 1 indication. More... | |
#define | PCA9420_SUB_INT1_MASK 0x05U |
Sub level interrupt 1 mask. More... | |
#define | PCA9420_SUB_INT2 0x06U |
Sub level interrupt 2 indication. More... | |
#define | PCA9420_SUB_INT2_MASK 0x07U |
Sub level interrupt 2 mask. More... | |
#define | PCA9420_TOP_CNTL0 0x09U |
Top level system ctrl 0. More... | |
#define | PCA9420_TOP_CNTL1 0x0AU |
Top level system ctrl 1. More... | |
#define | PCA9420_TOP_CNTL2 0x0BU |
Top level system ctrl 2. More... | |
#define | PCA9420_TOP_CNTL3 0x0CU |
Top level system ctrl 3. More... | |
#define | PCA9420_TOP_CNTL4 0x0DU |
Top level system ctrl 4. More... | |
#define | PCA9420_CHG_CNTL0 0x10U |
Charger cntl reg 0. More... | |
#define | PCA9420_CHG_CNTL1 0x11U |
Charger cntl reg 1. More... | |
#define | PCA9420_CHG_CNTL2 0x12U |
Charger cntl reg 2. More... | |
#define | PCA9420_CHG_CNTL3 0x13U |
Charger cntl reg 3. More... | |
#define | PCA9420_CHG_CNTL4 0x14U |
Charger cntl reg 4. More... | |
#define | PCA9420_CHG_CNTL5 0x15U |
Charger cntl reg 5. More... | |
#define | PCA9420_CHG_CNTL6 0x16U |
Charger cntl reg 6. More... | |
#define | PCA9420_CHG_CNTL7 0x17U |
Charger cntl reg 7. More... | |
#define | PCA9420_CHG_STATUS_0 0x18U |
Charger status reg 0. More... | |
#define | PCA9420_CHG_STATUS_1 0x19U |
Charger status reg 1. More... | |
#define | PCA9420_CHG_STATUS_2 0x1AU |
Charger status reg 2. More... | |
#define | PCA9420_CHG_STATUS_3 0x1BU |
Charger status reg 3. More... | |
#define | PCA9420_REG_STATUS 0x20U |
Regulator status indication. More... | |
#define | PCA9420_ACT_DISCHARGE_CNTL_1 0x21U |
Active discharge control register. More... | |
#define | PCA9420_MODECFG_0_0 0x22U |
Mode configuration for mode 0_0. More... | |
#define | PCA9420_MODECFG_0_1 0x23U |
Mode configuration for mode 0_1. More... | |
#define | PCA9420_MODECFG_0_2 0x24U |
Mode configuration for mode 0_2. More... | |
#define | PCA9420_MODECFG_0_3 0x25U |
Mode configuration for mode 0_3. More... | |
#define | PCA9420_MODECFG_1_0 0x26U |
Mode configuration for mode 1_0. More... | |
#define | PCA9420_MODECFG_1_1 0x27U |
Mode configuration for mode 1_1. More... | |
#define | PCA9420_MODECFG_1_2 0x28U |
Mode configuration for mode 1_2. More... | |
#define | PCA9420_MODECFG_1_3 0x29U |
Mode configuration for mode 1_3. More... | |
#define | PCA9420_MODECFG_2_0 0x2AU |
Mode configuration for mode 2_0. More... | |
#define | PCA9420_MODECFG_2_1 0x2BU |
Mode configuration for mode 2_1. More... | |
#define | PCA9420_MODECFG_2_2 0x2CU |
Mode configuration for mode 2_2. More... | |
#define | PCA9420_MODECFG_2_3 0x2DU |
Mode configuration for mode 2_3. More... | |
#define | PCA9420_MODECFG_3_0 0x2EU |
Mode configuration for mode 3_0. More... | |
#define | PCA9420_MODECFG_3_1 0x2FU |
Mode configuration for mode 3_1. More... | |
#define | PCA9420_MODECFG_3_2 0x30U |
Mode configuration for mode 3_2. More... | |
#define | PCA9420_MODECFG_3_3 0x31U |
Mode configuration for mode 3_3. More... | |
#define | PCA9420_DEV_INFO_DEV_ID_MASK 0xF0U |
Device ID mask. More... | |
#define | PCA9420_DEV_INFO_DEV_ID_SHIFT 0x04U |
#define | PCA9420_DEV_INFO_DEV_REV_MASK 0x0FU |
Device revision mask. More... | |
#define | PCA9420_DEV_INFO_DEV_REV_SHIFT 0x00U |
#define | PCA9420_TOP_INT_SYS_INT_MASK 0x01U |
System level interrupt trigger. More... | |
#define | PCA9420_TOP_INT_SYS_INT_SHIFT 0x03U |
#define | PCA9420_TOP_INT_CHG_INT_MASK 0x01U |
charger block interrupt trigger More... | |
#define | PCA9420_TOP_INT_CHG_INT_SHIFT 0x02U |
#define | PCA9420_TOP_INT_SW_INT_MASK 0x01U |
buck regulator interrupt trigger More... | |
#define | PCA9420_TOP_INT_SW_INT_SHIFT 0x01U |
#define | PCA9420_TOP_INT_LDO_INT_MASK 0x01U |
ldo block interrupt trigger More... | |
#define | PCA9420_TOP_INT_LDO_INT_SHIFT 0x00U |
#define | PCA9420_TOP_CNTL0_VIN_ILIM_SEL_MASK 0xE0U |
VIN input current limit selection. More... | |
#define | PCA9420_TOP_CNTL0_VIN_ILIM_SEL_SHIFT 0x05U |
#define | PCA9420_TOP_CNTL3_MODE_I2C_MASK 0x18U |
I2C Mode control mask. More... | |
#define | PCA9420_TOP_CNTL3_MODE_I2C_SHIFT 0x03U |
#define | PCA9420_MODECFG_0_SHIP_EN_MASK 0x80U |
Mode ship enable mask. More... | |
#define | PCA9420_MODECFG_0_MODE_CTRL_SEL_MASK 0x40U |
#define | PCA9420_MODECFG_0_SW1_OUT_MASK 0x3FU |
Mode output voltage mask. More... | |
#define | PCA9420_MODECFG_1_ON_CFG_MASK 0x40U |
#define | PCA9420_MODECFG_1_SW2_OUT_MASK 0x3FU |
SW2_OUT offset and voltage level mask. More... | |
#define | PCA9420_MODECFG_2_LDO1_OUT_MASK 0xF0U |
LDO1_OUT voltage level mask. More... | |
#define | PCA9420_MODECFG_2_LDO1_OUT_SHIFT 0x04U |
#define | PCA9420_MODECFG_2_SW1_EN_MASK 0x08U |
SW1 Enable. More... | |
#define | PCA9420_MODECFG_2_SW1_EN_VAL 0x08U |
#define | PCA9420_MODECFG_2_SW2_EN_MASK 0x04U |
SW2 Enable. More... | |
#define | PCA9420_MODECFG_2_SW2_EN_VAL 0x04U |
#define | PCA9420_MODECFG_2_LDO1_EN_MASK 0x02U |
LDO1 Enable. More... | |
#define | PCA9420_MODECFG_2_LDO1_EN_VAL 0x02U |
#define | PCA9420_MODECFG_2_LDO2_EN_MASK 0x01U |
LDO2 Enable. More... | |
#define | PCA9420_MODECFG_2_LDO2_EN_VAL 0x01U |
#define | PCA9420_MODECFG_3_WDIMER_MASK 0xC0U |
Watchdog timer setting mask. More... | |
#define | PCA9420_MODECFG_3_LDO2_OUT_MASK 0x3FU |
LDO2_OUT offset and voltage level mask. More... | |
#define PCA9420_ACT_DISCHARGE_CNTL_1 0x21U |
Active discharge control register.
#define PCA9420_CHG_CNTL0 0x10U |
Charger cntl reg 0.
Battery charger registers
#define PCA9420_CHG_CNTL1 0x11U |
Charger cntl reg 1.
#define PCA9420_CHG_CNTL2 0x12U |
Charger cntl reg 2.
#define PCA9420_CHG_CNTL3 0x13U |
Charger cntl reg 3.
#define PCA9420_CHG_CNTL4 0x14U |
Charger cntl reg 4.
#define PCA9420_CHG_CNTL5 0x15U |
Charger cntl reg 5.
#define PCA9420_CHG_CNTL6 0x16U |
Charger cntl reg 6.
#define PCA9420_CHG_CNTL7 0x17U |
Charger cntl reg 7.
#define PCA9420_CHG_STATUS_0 0x18U |
Charger status reg 0.
#define PCA9420_CHG_STATUS_1 0x19U |
Charger status reg 1.
#define PCA9420_CHG_STATUS_2 0x1AU |
Charger status reg 2.
#define PCA9420_CHG_STATUS_3 0x1BU |
Charger status reg 3.
#define PCA9420_CURRENT_LIMIT_LEVELS |
#define PCA9420_DEV_INFO 0x00U |
Device Information register.
Register memory map. See datasheet for more details. General purpose registers
#define PCA9420_DEV_INFO_DEV_ID_MASK 0xF0U |
Device ID mask.
Define the Register Masks of PCA9420.
#define PCA9420_DEV_INFO_DEV_ID_SHIFT 0x04U |
#define PCA9420_DEV_INFO_DEV_REV_MASK 0x0FU |
Device revision mask.
#define PCA9420_DEV_INFO_DEV_REV_SHIFT 0x00U |
#define PCA9420_LDO1_VOLTAGE_RANGE |
#define PCA9420_LDO2_VOLTAGE_RANGE |
#define PCA9420_MODECFG_0_0 0x22U |
Mode configuration for mode 0_0.
#define PCA9420_MODECFG_0_1 0x23U |
Mode configuration for mode 0_1.
#define PCA9420_MODECFG_0_2 0x24U |
Mode configuration for mode 0_2.
#define PCA9420_MODECFG_0_3 0x25U |
Mode configuration for mode 0_3.
#define PCA9420_MODECFG_0_MODE_CTRL_SEL_MASK 0x40U |
#define PCA9420_MODECFG_0_SHIP_EN_MASK 0x80U |
Mode ship enable mask.
#define PCA9420_MODECFG_0_SW1_OUT_MASK 0x3FU |
Mode output voltage mask.
#define PCA9420_MODECFG_1_0 0x26U |
Mode configuration for mode 1_0.
#define PCA9420_MODECFG_1_1 0x27U |
Mode configuration for mode 1_1.
#define PCA9420_MODECFG_1_2 0x28U |
Mode configuration for mode 1_2.
#define PCA9420_MODECFG_1_3 0x29U |
Mode configuration for mode 1_3.
#define PCA9420_MODECFG_1_ON_CFG_MASK 0x40U |
#define PCA9420_MODECFG_1_SW2_OUT_MASK 0x3FU |
SW2_OUT offset and voltage level mask.
#define PCA9420_MODECFG_2_0 0x2AU |
Mode configuration for mode 2_0.
#define PCA9420_MODECFG_2_1 0x2BU |
Mode configuration for mode 2_1.
#define PCA9420_MODECFG_2_2 0x2CU |
Mode configuration for mode 2_2.
#define PCA9420_MODECFG_2_3 0x2DU |
Mode configuration for mode 2_3.
#define PCA9420_MODECFG_2_LDO1_EN_MASK 0x02U |
LDO1 Enable.
#define PCA9420_MODECFG_2_LDO1_EN_VAL 0x02U |
#define PCA9420_MODECFG_2_LDO1_OUT_MASK 0xF0U |
LDO1_OUT voltage level mask.
#define PCA9420_MODECFG_2_LDO1_OUT_SHIFT 0x04U |
#define PCA9420_MODECFG_2_LDO2_EN_MASK 0x01U |
LDO2 Enable.
#define PCA9420_MODECFG_2_LDO2_EN_VAL 0x01U |
#define PCA9420_MODECFG_2_SW1_EN_MASK 0x08U |
SW1 Enable.
#define PCA9420_MODECFG_2_SW1_EN_VAL 0x08U |
#define PCA9420_MODECFG_2_SW2_EN_MASK 0x04U |
SW2 Enable.
#define PCA9420_MODECFG_2_SW2_EN_VAL 0x04U |
#define PCA9420_MODECFG_3_0 0x2EU |
Mode configuration for mode 3_0.
#define PCA9420_MODECFG_3_1 0x2FU |
Mode configuration for mode 3_1.
#define PCA9420_MODECFG_3_2 0x30U |
Mode configuration for mode 3_2.
#define PCA9420_MODECFG_3_3 0x31U |
Mode configuration for mode 3_3.
#define PCA9420_MODECFG_3_LDO2_OUT_MASK 0x3FU |
LDO2_OUT offset and voltage level mask.
#define PCA9420_MODECFG_3_WDIMER_MASK 0xC0U |
Watchdog timer setting mask.
#define PCA9420_REG_STATUS 0x20U |
Regulator status indication.
Regulator status indication registers
#define PCA9420_SUB_INT0 0x02U |
Sub level interrupt 0 indication.
#define PCA9420_SUB_INT0_MASK 0x03U |
Sub level interrupt 0 mask.
#define PCA9420_SUB_INT1 0x04U |
Sub level interrupt 1 indication.
#define PCA9420_SUB_INT1_MASK 0x05U |
Sub level interrupt 1 mask.
#define PCA9420_SUB_INT2 0x06U |
Sub level interrupt 2 indication.
#define PCA9420_SUB_INT2_MASK 0x07U |
Sub level interrupt 2 mask.
#define PCA9420_SW1_VOLTAGE_RANGE |
#define PCA9420_SW2_VOLTAGE_RANGE |
#define PCA9420_TOP_CNTL0 0x09U |
Top level system ctrl 0.
#define PCA9420_TOP_CNTL0_VIN_ILIM_SEL_MASK 0xE0U |
VIN input current limit selection.
#define PCA9420_TOP_CNTL0_VIN_ILIM_SEL_SHIFT 0x05U |
#define PCA9420_TOP_CNTL1 0x0AU |
Top level system ctrl 1.
#define PCA9420_TOP_CNTL2 0x0BU |
Top level system ctrl 2.
#define PCA9420_TOP_CNTL3 0x0CU |
Top level system ctrl 3.
#define PCA9420_TOP_CNTL3_MODE_I2C_MASK 0x18U |
I2C Mode control mask.
#define PCA9420_TOP_CNTL3_MODE_I2C_SHIFT 0x03U |
#define PCA9420_TOP_CNTL4 0x0DU |
Top level system ctrl 4.
#define PCA9420_TOP_INT 0x01U |
Top level interrupt status.
#define PCA9420_TOP_INT_CHG_INT_MASK 0x01U |
charger block interrupt trigger
#define PCA9420_TOP_INT_CHG_INT_SHIFT 0x02U |
#define PCA9420_TOP_INT_LDO_INT_MASK 0x01U |
ldo block interrupt trigger
#define PCA9420_TOP_INT_LDO_INT_SHIFT 0x00U |
#define PCA9420_TOP_INT_SW_INT_MASK 0x01U |
buck regulator interrupt trigger
#define PCA9420_TOP_INT_SW_INT_SHIFT 0x01U |
#define PCA9420_TOP_INT_SYS_INT_MASK 0x01U |
System level interrupt trigger.
#define PCA9420_TOP_INT_SYS_INT_SHIFT 0x03U |