8#ifndef ZEPHYR_INCLUDE_CACHE_H_
9#define ZEPHYR_INCLUDE_CACHE_H_
17#include <zephyr/arch/cpu.h>
23#if defined(CONFIG_EXTERNAL_CACHE)
26#elif defined(CONFIG_ARCH_CACHE)
42#define _CPU DT_PATH(cpus, cpu_0)
54#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
67#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
80#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
93#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
94 cache_instr_disable();
109#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
110 return cache_data_flush_all();
126#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
127 return cache_instr_flush_all();
143#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
144 return cache_data_invd_all();
160#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
161 return cache_instr_invd_all();
177#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
178 return cache_data_flush_and_invd_all();
194#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
195 return cache_instr_flush_and_invd_all();
221static ALWAYS_INLINE int z_impl_sys_cache_data_flush_range(
void *addr,
size_t size)
223#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
224 return cache_data_flush_range(addr, size);
253#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
254 return cache_instr_flush_range(addr, size);
284static ALWAYS_INLINE int z_impl_sys_cache_data_invd_range(
void *addr,
size_t size)
286#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
287 return cache_data_invd_range(addr, size);
317#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
318 return cache_instr_invd_range(addr, size);
348static ALWAYS_INLINE int z_impl_sys_cache_data_flush_and_invd_range(
void *addr,
size_t size)
350#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
351 return cache_data_flush_and_invd_range(addr, size);
381#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
382 return cache_instr_flush_and_invd_range(addr, size);
408#ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
409 return cache_data_line_size_get();
410#elif (CONFIG_DCACHE_LINE_SIZE != 0)
411 return CONFIG_DCACHE_LINE_SIZE;
413 return DT_PROP_OR(_CPU, d_cache_line_size, 0);
435#ifdef CONFIG_ICACHE_LINE_SIZE_DETECT
436 return cache_instr_line_size_get();
437#elif (CONFIG_ICACHE_LINE_SIZE != 0)
438 return CONFIG_ICACHE_LINE_SIZE;
440 return DT_PROP_OR(_CPU, i_cache_line_size, 0);
444#ifdef CONFIG_LIBMETAL
445static ALWAYS_INLINE void sys_cache_flush(
void *addr,
size_t size)
451#include <syscalls/cache.h>
Public APIs for architectural cache controller drivers.
#define ALWAYS_INLINE
Definition: common.h:129
Public APIs for external cache controller drivers.
static ALWAYS_INLINE int sys_cache_data_flush_all(void)
Flush the d-cache.
Definition: cache.h:107
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_all(void)
Flush and Invalidate the i-cache.
Definition: cache.h:192
static ALWAYS_INLINE size_t sys_cache_instr_line_size_get(void)
Get the the i-cache line size.
Definition: cache.h:433
static ALWAYS_INLINE void sys_cache_instr_disable(void)
Disable the i-cache.
Definition: cache.h:91
int sys_cache_data_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the d-cache.
int sys_cache_data_invd_range(void *addr, size_t size)
Invalidate an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
Flush an address range in the i-cache.
Definition: cache.h:251
static ALWAYS_INLINE int sys_cache_instr_flush_all(void)
Flush the i-cache.
Definition: cache.h:124
static ALWAYS_INLINE size_t sys_cache_data_line_size_get(void)
Get the the d-cache line size.
Definition: cache.h:406
int sys_cache_data_flush_range(void *addr, size_t size)
Flush an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the i-cache.
Definition: cache.h:379
static ALWAYS_INLINE void sys_cache_data_disable(void)
Disable the d-cache.
Definition: cache.h:65
static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
Invalidate an address range in the i-cache.
Definition: cache.h:315
static ALWAYS_INLINE void sys_cache_data_enable(void)
Enable the d-cache.
Definition: cache.h:52
static ALWAYS_INLINE void sys_cache_instr_enable(void)
Enable the i-cache.
Definition: cache.h:78
static ALWAYS_INLINE int sys_cache_data_invd_all(void)
Invalidate the d-cache.
Definition: cache.h:141
static ALWAYS_INLINE int sys_cache_data_flush_and_invd_all(void)
Flush and Invalidate the d-cache.
Definition: cache.h:175
static ALWAYS_INLINE int sys_cache_instr_invd_all(void)
Invalidate the i-cache.
Definition: cache.h:158
#define DT_PROP_OR(node_id, prop, default_value)
Like DT_PROP(), but with a fallback to default_value.
Definition: devicetree.h:776
#define ENOTSUP
Unsupported value.
Definition: errno.h:115