Zephyr API Documentation  3.5.0
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cache.h
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1/*
2 * Copyright (c) 2015 Wind River Systems, Inc.
3 * Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#ifndef ZEPHYR_INCLUDE_CACHE_H_
9#define ZEPHYR_INCLUDE_CACHE_H_
10
16#include <zephyr/kernel.h>
17#include <zephyr/arch/cpu.h>
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23#if defined(CONFIG_EXTERNAL_CACHE)
25
26#elif defined(CONFIG_ARCH_CACHE)
27#include <zephyr/arch/cache.h>
28
29#endif
30
42#define _CPU DT_PATH(cpus, cpu_0)
43
53{
54#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
55 cache_data_enable();
56#endif
57}
58
66{
67#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
68 cache_data_disable();
69#endif
70}
71
79{
80#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
81 cache_instr_enable();
82#endif
83}
84
92{
93#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
94 cache_instr_disable();
95#endif
96}
97
108{
109#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
110 return cache_data_flush_all();
111#endif
112 return -ENOTSUP;
113}
114
125{
126#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
127 return cache_instr_flush_all();
128#endif
129 return -ENOTSUP;
130}
131
142{
143#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
144 return cache_data_invd_all();
145#endif
146 return -ENOTSUP;
147}
148
159{
160#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
161 return cache_instr_invd_all();
162#endif
163 return -ENOTSUP;
164}
165
176{
177#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
178 return cache_data_flush_and_invd_all();
179#endif
180 return -ENOTSUP;
181}
182
193{
194#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
195 return cache_instr_flush_and_invd_all();
196#endif
197 return -ENOTSUP;
198}
199
219__syscall_always_inline int sys_cache_data_flush_range(void *addr, size_t size);
220
221static ALWAYS_INLINE int z_impl_sys_cache_data_flush_range(void *addr, size_t size)
222{
223#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
224 return cache_data_flush_range(addr, size);
225#endif
226 ARG_UNUSED(addr);
227 ARG_UNUSED(size);
228
229 return -ENOTSUP;
230}
231
251static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
252{
253#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
254 return cache_instr_flush_range(addr, size);
255#endif
256 ARG_UNUSED(addr);
257 ARG_UNUSED(size);
258
259 return -ENOTSUP;
260}
261
282__syscall_always_inline int sys_cache_data_invd_range(void *addr, size_t size);
283
284static ALWAYS_INLINE int z_impl_sys_cache_data_invd_range(void *addr, size_t size)
285{
286#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
287 return cache_data_invd_range(addr, size);
288#endif
289 ARG_UNUSED(addr);
290 ARG_UNUSED(size);
291
292 return -ENOTSUP;
293}
294
315static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
316{
317#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
318 return cache_instr_invd_range(addr, size);
319#endif
320 ARG_UNUSED(addr);
321 ARG_UNUSED(size);
322
323 return -ENOTSUP;
324}
325
346__syscall_always_inline int sys_cache_data_flush_and_invd_range(void *addr, size_t size);
347
348static ALWAYS_INLINE int z_impl_sys_cache_data_flush_and_invd_range(void *addr, size_t size)
349{
350#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
351 return cache_data_flush_and_invd_range(addr, size);
352#endif
353 ARG_UNUSED(addr);
354 ARG_UNUSED(size);
355
356 return -ENOTSUP;
357}
358
379static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
380{
381#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
382 return cache_instr_flush_and_invd_range(addr, size);
383#endif
384 ARG_UNUSED(addr);
385 ARG_UNUSED(size);
386
387 return -ENOTSUP;
388}
389
407{
408#ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
409 return cache_data_line_size_get();
410#elif (CONFIG_DCACHE_LINE_SIZE != 0)
411 return CONFIG_DCACHE_LINE_SIZE;
412#else
413 return DT_PROP_OR(_CPU, d_cache_line_size, 0);
414#endif
415}
416
434{
435#ifdef CONFIG_ICACHE_LINE_SIZE_DETECT
436 return cache_instr_line_size_get();
437#elif (CONFIG_ICACHE_LINE_SIZE != 0)
438 return CONFIG_ICACHE_LINE_SIZE;
439#else
440 return DT_PROP_OR(_CPU, i_cache_line_size, 0);
441#endif
442}
443
444#ifdef CONFIG_LIBMETAL
445static ALWAYS_INLINE void sys_cache_flush(void *addr, size_t size)
446{
447 sys_cache_data_flush_range(addr, size);
448}
449#endif
450
451#include <syscalls/cache.h>
452#ifdef __cplusplus
453}
454#endif
455
460#endif /* ZEPHYR_INCLUDE_CACHE_H_ */
Public APIs for architectural cache controller drivers.
#define ALWAYS_INLINE
Definition: common.h:129
Public APIs for external cache controller drivers.
static ALWAYS_INLINE int sys_cache_data_flush_all(void)
Flush the d-cache.
Definition: cache.h:107
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_all(void)
Flush and Invalidate the i-cache.
Definition: cache.h:192
static ALWAYS_INLINE size_t sys_cache_instr_line_size_get(void)
Get the the i-cache line size.
Definition: cache.h:433
static ALWAYS_INLINE void sys_cache_instr_disable(void)
Disable the i-cache.
Definition: cache.h:91
int sys_cache_data_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the d-cache.
int sys_cache_data_invd_range(void *addr, size_t size)
Invalidate an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
Flush an address range in the i-cache.
Definition: cache.h:251
static ALWAYS_INLINE int sys_cache_instr_flush_all(void)
Flush the i-cache.
Definition: cache.h:124
static ALWAYS_INLINE size_t sys_cache_data_line_size_get(void)
Get the the d-cache line size.
Definition: cache.h:406
int sys_cache_data_flush_range(void *addr, size_t size)
Flush an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the i-cache.
Definition: cache.h:379
static ALWAYS_INLINE void sys_cache_data_disable(void)
Disable the d-cache.
Definition: cache.h:65
static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
Invalidate an address range in the i-cache.
Definition: cache.h:315
static ALWAYS_INLINE void sys_cache_data_enable(void)
Enable the d-cache.
Definition: cache.h:52
static ALWAYS_INLINE void sys_cache_instr_enable(void)
Enable the i-cache.
Definition: cache.h:78
static ALWAYS_INLINE int sys_cache_data_invd_all(void)
Invalidate the d-cache.
Definition: cache.h:141
static ALWAYS_INLINE int sys_cache_data_flush_and_invd_all(void)
Flush and Invalidate the d-cache.
Definition: cache.h:175
static ALWAYS_INLINE int sys_cache_instr_invd_all(void)
Invalidate the i-cache.
Definition: cache.h:158
#define DT_PROP_OR(node_id, prop, default_value)
Like DT_PROP(), but with a fallback to default_value.
Definition: devicetree.h:776
#define ENOTSUP
Unsupported value.
Definition: errno.h:115
Public kernel APIs.