Cache Interface

Functions
static ALWAYS_INLINE void	sys_cache_data_enable (void)
	Enable the d-cache.
static ALWAYS_INLINE void	sys_cache_data_disable (void)
	Disable the d-cache.
static ALWAYS_INLINE void	sys_cache_instr_enable (void)
	Enable the i-cache.
static ALWAYS_INLINE void	sys_cache_instr_disable (void)
	Disable the i-cache.
static ALWAYS_INLINE int	sys_cache_data_flush_all (void)
	Flush the d-cache.
static ALWAYS_INLINE int	sys_cache_instr_flush_all (void)
	Flush the i-cache.
static ALWAYS_INLINE int	sys_cache_data_invd_all (void)
	Invalidate the d-cache.
static ALWAYS_INLINE int	sys_cache_instr_invd_all (void)
	Invalidate the i-cache.
static ALWAYS_INLINE int	sys_cache_data_flush_and_invd_all (void)
	Flush and Invalidate the d-cache.
static ALWAYS_INLINE int	sys_cache_instr_flush_and_invd_all (void)
	Flush and Invalidate the i-cache.
int	sys_cache_data_flush_range (void *addr, size_t size)
	Flush an address range in the d-cache.
static ALWAYS_INLINE int	sys_cache_instr_flush_range (void *addr, size_t size)
	Flush an address range in the i-cache.
int	sys_cache_data_invd_range (void *addr, size_t size)
	Invalidate an address range in the d-cache.
static ALWAYS_INLINE int	sys_cache_instr_invd_range (void *addr, size_t size)
	Invalidate an address range in the i-cache.
int	sys_cache_data_flush_and_invd_range (void *addr, size_t size)
	Flush and Invalidate an address range in the d-cache.
static ALWAYS_INLINE int	sys_cache_instr_flush_and_invd_range (void *addr, size_t size)
	Flush and Invalidate an address range in the i-cache.
static ALWAYS_INLINE size_t	sys_cache_data_line_size_get (void)
	Get the the d-cache line size.
static ALWAYS_INLINE size_t	sys_cache_instr_line_size_get (void)
	Get the the i-cache line size.

Detailed Description

Function Documentation

sys_cache_data_disable()

static ALWAYS_INLINE void sys_cache_data_disable ( void  )

static

#include <zephyr/cache.h>

Disable the d-cache.

Disable the data cache

sys_cache_data_enable()

static ALWAYS_INLINE void sys_cache_data_enable ( void  )

static

#include <zephyr/cache.h>

Enable the d-cache.

Enable the data cache

sys_cache_data_flush_all()

static ALWAYS_INLINE int sys_cache_data_flush_all ( void  )

static

#include <zephyr/cache.h>

Flush the d-cache.

Flush the whole data cache.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

sys_cache_data_flush_and_invd_all()

static ALWAYS_INLINE int sys_cache_data_flush_and_invd_all ( void  )

static

#include <zephyr/cache.h>

Flush and Invalidate the d-cache.

Flush and Invalidate the whole data cache.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

sys_cache_data_flush_and_invd_range()

int sys_cache_data_flush_and_invd_range	(	void *	addr,
		size_t	size
	)

#include <zephyr/cache.h>

Flush and Invalidate an address range in the d-cache.

Flush and Invalidate the specified address range of the data cache.

Note

the cache operations act on cache line. When multiple data structures share the same cache line being flushed, all the portions of the data structures sharing the same line will be flushed before being invalidated. This is usually not a problem because writing back is a non-destructive process that could be triggered by hardware at any time, so having an aligned addr or a padded size is not strictly necessary.

Parameters

addr	Starting address to flush and invalidate.
size	Range size.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

sys_cache_data_flush_range()

int sys_cache_data_flush_range	(	void *	addr,
		size_t	size
	)

#include <zephyr/cache.h>

Flush an address range in the d-cache.

Flush the specified address range of the data cache.

Note

the cache operations act on cache line. When multiple data structures share the same cache line being flushed, all the portions of the data structures sharing the same line will be flushed. This is usually not a problem because writing back is a non-destructive process that could be triggered by hardware at any time, so having an aligned addr or a padded size is not strictly necessary.

Parameters

addr	Starting address to flush.
size	Range size.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

sys_cache_data_invd_all()

static ALWAYS_INLINE int sys_cache_data_invd_all ( void  )

static

#include <zephyr/cache.h>

Invalidate the d-cache.

Invalidate the whole data cache.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

sys_cache_data_invd_range()

int sys_cache_data_invd_range	(	void *	addr,
		size_t	size
	)

#include <zephyr/cache.h>

Invalidate an address range in the d-cache.

Invalidate the specified address range of the data cache.

Note

the cache operations act on cache line. When multiple data structures share the same cache line being invalidated, all the portions of the non-read-only data structures sharing the same line will be invalidated as well. This is a destructive process that could lead to data loss and/or corruption. When addr is not aligned to the cache line and/or size is not a multiple of the cache line size the behaviour is undefined.

Parameters

addr	Starting address to invalidate.
size	Range size.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

sys_cache_data_line_size_get()

static ALWAYS_INLINE size_t sys_cache_data_line_size_get ( void  )

static

#include <zephyr/cache.h>

Get the the d-cache line size.

The API is provided to get the data cache line.

The cache line size is calculated (in order of priority):

• At run-time when CONFIG_DCACHE_LINE_SIZE_DETECT is set.
• At compile time using the value set in CONFIG_DCACHE_LINE_SIZE .
• At compile time using the d-cache-line-size CPU0 property of the DT.
• 0 otherwise

Return values

size	Size of the d-cache line.
0	If the d-cache is not enabled.

sys_cache_instr_disable()

static ALWAYS_INLINE void sys_cache_instr_disable ( void  )

static

#include <zephyr/cache.h>

Disable the i-cache.

Disable the instruction cache

sys_cache_instr_enable()

static ALWAYS_INLINE void sys_cache_instr_enable ( void  )

static

#include <zephyr/cache.h>

Enable the i-cache.

Enable the instruction cache

sys_cache_instr_flush_all()

static ALWAYS_INLINE int sys_cache_instr_flush_all ( void  )

static

#include <zephyr/cache.h>

Flush the i-cache.

Flush the whole instruction cache.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

sys_cache_instr_flush_and_invd_all()

static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_all ( void  )

static

#include <zephyr/cache.h>

Flush and Invalidate the i-cache.

Flush and Invalidate the whole instruction cache.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

sys_cache_instr_flush_and_invd_range()

static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range ( void *  addr, size_t  size  )

static

#include <zephyr/cache.h>

Flush and Invalidate an address range in the i-cache.

Flush and Invalidate the specified address range of the instruction cache.

Note

the cache operations act on cache line. When multiple data structures share the same cache line being flushed, all the portions of the data structures sharing the same line will be flushed before being invalidated. This is usually not a problem because writing back is a non-destructive process that could be triggered by hardware at any time, so having an aligned addr or a padded size is not strictly necessary.

Parameters

addr	Starting address to flush and invalidate.
size	Range size.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

sys_cache_instr_flush_range()

static ALWAYS_INLINE int sys_cache_instr_flush_range ( void *  addr, size_t  size  )

static

#include <zephyr/cache.h>

Flush an address range in the i-cache.

Flush the specified address range of the instruction cache.

Note

the cache operations act on cache line. When multiple data structures share the same cache line being flushed, all the portions of the data structures sharing the same line will be flushed. This is usually not a problem because writing back is a non-destructive process that could be triggered by hardware at any time, so having an aligned addr or a padded size is not strictly necessary.

Parameters

addr	Starting address to flush.
size	Range size.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

sys_cache_instr_invd_all()

static ALWAYS_INLINE int sys_cache_instr_invd_all ( void  )

static

#include <zephyr/cache.h>

Invalidate the i-cache.

Invalidate the whole instruction cache.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

sys_cache_instr_invd_range()

static ALWAYS_INLINE int sys_cache_instr_invd_range ( void *  addr, size_t  size  )

static

#include <zephyr/cache.h>

Invalidate an address range in the i-cache.

Invalidate the specified address range of the instruction cache.

Note

the cache operations act on cache line. When multiple data structures share the same cache line being invalidated, all the portions of the non-read-only data structures sharing the same line will be invalidated as well. This is a destructive process that could lead to data loss and/or corruption. When addr is not aligned to the cache line and/or size is not a multiple of the cache line size the behaviour is undefined.

Parameters

addr	Starting address to invalidate.
size	Range size.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

sys_cache_instr_line_size_get()

static ALWAYS_INLINE size_t sys_cache_instr_line_size_get ( void  )

static

#include <zephyr/cache.h>

Get the the i-cache line size.

The API is provided to get the instruction cache line.

The cache line size is calculated (in order of priority):

• At run-time when CONFIG_ICACHE_LINE_SIZE_DETECT is set.
• At compile time using the value set in CONFIG_ICACHE_LINE_SIZE .
• At compile time using the i-cache-line-size CPU0 property of the DT.
• 0 otherwise

Return values

size	Size of the d-cache line.
0	If the d-cache is not enabled.