stm32u5_clock.h File Reference

Go to the source code of this file.

Macros
#define	STM32_SRC_PLL1_P   0x001
	Domain clocks.
#define	STM32_SRC_PLL1_Q   0x002
#define	STM32_SRC_PLL1_R   0x003
#define	STM32_SRC_PLL2_P   0x004
#define	STM32_SRC_PLL2_Q   0x005
#define	STM32_SRC_PLL2_R   0x006
#define	STM32_SRC_PLL3_P   0x007
#define	STM32_SRC_PLL3_Q   0x008
#define	STM32_SRC_PLL3_R   0x009
#define	STM32_SRC_HSE   0x00A
	Fixed clocks
#define	STM32_SRC_LSE   0x00B
#define	STM32_SRC_LSI   0x00C
#define	STM32_SRC_HSI16   0x00D
#define	STM32_SRC_HSI48   0x00E
#define	STM32_SRC_MSIS   0x00F
#define	STM32_SRC_MSIK   0x010
#define	STM32_SRC_SYSCLK   0x011
	Core clock.
#define	STM32_CLOCK_BUS_AHB1   0x088
	Clock muxes.
#define	STM32_CLOCK_BUS_AHB2   0x08C
#define	STM32_CLOCK_BUS_AHB2_2   0x090
#define	STM32_CLOCK_BUS_AHB3   0x094
#define	STM32_CLOCK_BUS_APB1   0x09C
#define	STM32_CLOCK_BUS_APB1_2   0x0A0
#define	STM32_CLOCK_BUS_APB2   0x0A4
#define	STM32_CLOCK_BUS_APB3   0x0A8
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3
#define	STM32_CLOCK_REG_MASK   0xFFU
#define	STM32_CLOCK_REG_SHIFT   0U
#define	STM32_CLOCK_SHIFT_MASK   0x1FU
#define	STM32_CLOCK_SHIFT_SHIFT   8U
#define	STM32_CLOCK_MASK_MASK   0x7U
#define	STM32_CLOCK_MASK_SHIFT   13U
#define	STM32_CLOCK_VAL_MASK   0x7U
#define	STM32_CLOCK_VAL_SHIFT   16U
#define	STM32_CLOCK(val, mask, shift, reg)
	STM32U5 clock configuration bit field.
#define	CCIPR1_REG   0xE0
	RCC_CCIPRx register offset (RM0456.pdf)
#define	CCIPR2_REG   0xE4
#define	CCIPR3_REG   0xE8
#define	BDCR_REG   0xF0
	RCC_BDCR register offset.
#define	USART1_SEL(val)   STM32_CLOCK(val, 3, 0, CCIPR1_REG)
	Device domain clocks selection helpers.
#define	USART2_SEL(val)   STM32_CLOCK(val, 3, 2, CCIPR1_REG)
#define	USART3_SEL(val)   STM32_CLOCK(val, 3, 4, CCIPR1_REG)
#define	USART4_SEL(val)   STM32_CLOCK(val, 3, 6, CCIPR1_REG)
#define	USART5_SEL(val)   STM32_CLOCK(val, 3, 8, CCIPR1_REG)
#define	I2C1_SEL(val)   STM32_CLOCK(val, 3, 10, CCIPR1_REG)
#define	I2C2_SEL(val)   STM32_CLOCK(val, 3, 12, CCIPR1_REG)
#define	I2C4_SEL(val)   STM32_CLOCK(val, 3, 14, CCIPR1_REG)
#define	SPI2_SEL(val)   STM32_CLOCK(val, 3, 16, CCIPR1_REG)
#define	LPTIM2_SEL(val)   STM32_CLOCK(val, 3, 18, CCIPR1_REG)
#define	SPI1_SEL(val)   STM32_CLOCK(val, 3, 20, CCIPR1_REG)
#define	SYSTICK_SEL(val)   STM32_CLOCK(val, 3, 22, CCIPR1_REG)
#define	FDCAN1_SEL(val)   STM32_CLOCK(val, 3, 24, CCIPR1_REG)
#define	ICKLK_SEL(val)   STM32_CLOCK(val, 3, 26, CCIPR1_REG)
#define	TIMIC_SEL(val)   STM32_CLOCK(val, 7, 29, CCIPR1_REG)
#define	MDF1_SEL(val)   STM32_CLOCK(val, 7, 0, CCIPR2_REG)
	CCIPR2 devices.
#define	SAI1_SEL(val)   STM32_CLOCK(val, 7, 5, CCIPR2_REG)
#define	SAI2_SEL(val)   STM32_CLOCK(val, 7, 8, CCIPR2_REG)
#define	SAE_SEL(val)   STM32_CLOCK(val, 1, 11, CCIPR2_REG)
#define	RNG_SEL(val)   STM32_CLOCK(val, 3, 12, CCIPR2_REG)
#define	SDMMC_SEL(val)   STM32_CLOCK(val, 1, 14, CCIPR2_REG)
#define	OCTOSPI_SEL(val)   STM32_CLOCK(val, 3, 20, CCIPR2_REG)
#define	LPUART1_SEL(val)   STM32_CLOCK(val, 7, 0, CCIPR3_REG)
	CCIPR3 devices.
#define	SPI3_SEL(val)   STM32_CLOCK(val, 3, 3, CCIPR3_REG)
#define	I2C3_SEL(val)   STM32_CLOCK(val, 3, 6, CCIPR3_REG)
#define	LPTIM34_SEL(val)   STM32_CLOCK(val, 3, 8, CCIPR3_REG)
#define	LPTIM1_SEL(val)   STM32_CLOCK(val, 3, 10, CCIPR3_REG)
#define	ADCDAC_SEL(val)   STM32_CLOCK(val, 7, 12, CCIPR3_REG)
#define	DAC1_SEL(val)   STM32_CLOCK(val, 1, 15, CCIPR3_REG)
#define	ADF1_SEL(val)   STM32_CLOCK(val, 7, 16, CCIPR3_REG)
#define	RTC_SEL(val)   STM32_CLOCK(val, 3, 8, BDCR_REG)
	BDCR devices.

Macro Definition Documentation

ADCDAC_SEL

#define ADCDAC_SEL

(

val

)

STM32_CLOCK(val, 7, 12, CCIPR3_REG)

ADF1_SEL

#define ADF1_SEL

(

val

)

STM32_CLOCK(val, 7, 16, CCIPR3_REG)

BDCR_REG

#define BDCR_REG   0xF0

RCC_BDCR register offset.

CCIPR1_REG

#define CCIPR1_REG   0xE0

RCC_CCIPRx register offset (RM0456.pdf)

CCIPR2_REG

#define CCIPR2_REG   0xE4

CCIPR3_REG

#define CCIPR3_REG   0xE8

DAC1_SEL

#define DAC1_SEL

(

val

)

STM32_CLOCK(val, 1, 15, CCIPR3_REG)

FDCAN1_SEL

#define FDCAN1_SEL

(

val

)

STM32_CLOCK(val, 3, 24, CCIPR1_REG)

I2C1_SEL

#define I2C1_SEL

(

val

)

STM32_CLOCK(val, 3, 10, CCIPR1_REG)

I2C2_SEL

#define I2C2_SEL

(

val

)

STM32_CLOCK(val, 3, 12, CCIPR1_REG)

I2C3_SEL

#define I2C3_SEL

(

val

)

STM32_CLOCK(val, 3, 6, CCIPR3_REG)

I2C4_SEL

#define I2C4_SEL

(

val

)

STM32_CLOCK(val, 3, 14, CCIPR1_REG)

ICKLK_SEL

#define ICKLK_SEL

(

val

)

STM32_CLOCK(val, 3, 26, CCIPR1_REG)

LPTIM1_SEL

#define LPTIM1_SEL

(

val

)

STM32_CLOCK(val, 3, 10, CCIPR3_REG)

LPTIM2_SEL

#define LPTIM2_SEL

(

val

)

STM32_CLOCK(val, 3, 18, CCIPR1_REG)

LPTIM34_SEL

#define LPTIM34_SEL

(

val

)

STM32_CLOCK(val, 3, 8, CCIPR3_REG)

LPUART1_SEL

#define LPUART1_SEL

(

val

)

STM32_CLOCK(val, 7, 0, CCIPR3_REG)

CCIPR3 devices.

MDF1_SEL

#define MDF1_SEL

(

val

)

STM32_CLOCK(val, 7, 0, CCIPR2_REG)

CCIPR2 devices.

OCTOSPI_SEL

#define OCTOSPI_SEL

(

val

)

STM32_CLOCK(val, 3, 20, CCIPR2_REG)

RNG_SEL

#define RNG_SEL

(

val

)

STM32_CLOCK(val, 3, 12, CCIPR2_REG)

RTC_SEL

#define RTC_SEL

(

val

)

STM32_CLOCK(val, 3, 8, BDCR_REG)

BDCR devices.

SAE_SEL

#define SAE_SEL

(

val

)

STM32_CLOCK(val, 1, 11, CCIPR2_REG)

SAI1_SEL

#define SAI1_SEL

(

val

)

STM32_CLOCK(val, 7, 5, CCIPR2_REG)

SAI2_SEL

#define SAI2_SEL

(

val

)

STM32_CLOCK(val, 7, 8, CCIPR2_REG)

SDMMC_SEL

#define SDMMC_SEL

(

val

)

STM32_CLOCK(val, 1, 14, CCIPR2_REG)

SPI1_SEL

#define SPI1_SEL

(

val

)

STM32_CLOCK(val, 3, 20, CCIPR1_REG)

SPI2_SEL

#define SPI2_SEL

(

val

)

STM32_CLOCK(val, 3, 16, CCIPR1_REG)

SPI3_SEL

#define SPI3_SEL

(

val

)

STM32_CLOCK(val, 3, 3, CCIPR3_REG)

STM32_CLOCK

#define STM32_CLOCK	(		val,
			mask,
			shift,
			reg
	)

Value:

        ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |    \
         (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |      \
         (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
         (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))

STM32U5 clock configuration bit field.

• reg (1/2/3) [ 0 : 7 ]
• shift (0..31) [ 8 : 12 ]
• mask (0x1, 0x3, 0x7) [ 13 : 15 ]
• val (0..7) [ 16 : 18 ]

Parameters

reg	RCC_CCIPRx register offset
shift	Position within RCC_CCIPRx.
mask	Mask for the RCC_CCIPRx field.
val	Clock value (0, 1, ... 7).

STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x088

Clock muxes.

Bus clocks

STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2   0x08C

STM32_CLOCK_BUS_AHB2_2

#define STM32_CLOCK_BUS_AHB2_2   0x090

STM32_CLOCK_BUS_AHB3

#define STM32_CLOCK_BUS_AHB3   0x094

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x09C

STM32_CLOCK_BUS_APB1_2

#define STM32_CLOCK_BUS_APB1_2   0x0A0

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x0A4

STM32_CLOCK_BUS_APB3

#define STM32_CLOCK_BUS_APB3   0x0A8

STM32_CLOCK_MASK_MASK

#define STM32_CLOCK_MASK_MASK   0x7U

STM32_CLOCK_MASK_SHIFT

#define STM32_CLOCK_MASK_SHIFT   13U

STM32_CLOCK_REG_MASK

#define STM32_CLOCK_REG_MASK   0xFFU

STM32_CLOCK_REG_SHIFT

#define STM32_CLOCK_REG_SHIFT   0U

STM32_CLOCK_SHIFT_MASK

#define STM32_CLOCK_SHIFT_MASK   0x1FU

STM32_CLOCK_SHIFT_SHIFT

#define STM32_CLOCK_SHIFT_SHIFT   8U

STM32_CLOCK_VAL_MASK

#define STM32_CLOCK_VAL_MASK   0x7U

STM32_CLOCK_VAL_SHIFT

#define STM32_CLOCK_VAL_SHIFT   16U

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

STM32_SRC_HSE

#define STM32_SRC_HSE   0x00A

Fixed clocks

STM32_SRC_HSI16

#define STM32_SRC_HSI16   0x00D

STM32_SRC_HSI48

#define STM32_SRC_HSI48   0x00E

STM32_SRC_LSE

#define STM32_SRC_LSE   0x00B

STM32_SRC_LSI

#define STM32_SRC_LSI   0x00C

STM32_SRC_MSIK

#define STM32_SRC_MSIK   0x010

STM32_SRC_MSIS

#define STM32_SRC_MSIS   0x00F

STM32_SRC_PLL1_P

#define STM32_SRC_PLL1_P   0x001

Domain clocks.

PLL outputs

STM32_SRC_PLL1_Q

#define STM32_SRC_PLL1_Q   0x002

STM32_SRC_PLL1_R

#define STM32_SRC_PLL1_R   0x003

STM32_SRC_PLL2_P

#define STM32_SRC_PLL2_P   0x004

STM32_SRC_PLL2_Q

#define STM32_SRC_PLL2_Q   0x005

STM32_SRC_PLL2_R

#define STM32_SRC_PLL2_R   0x006

STM32_SRC_PLL3_P

#define STM32_SRC_PLL3_P   0x007

STM32_SRC_PLL3_Q

#define STM32_SRC_PLL3_Q   0x008

STM32_SRC_PLL3_R

#define STM32_SRC_PLL3_R   0x009

STM32_SRC_SYSCLK

#define STM32_SRC_SYSCLK   0x011

Core clock.

SYSTICK_SEL

#define SYSTICK_SEL

(

val

)

STM32_CLOCK(val, 3, 22, CCIPR1_REG)

TIMIC_SEL

#define TIMIC_SEL

(

val

)

STM32_CLOCK(val, 7, 29, CCIPR1_REG)

USART1_SEL

#define USART1_SEL

(

val

)

STM32_CLOCK(val, 3, 0, CCIPR1_REG)

Device domain clocks selection helpers.

CCIPR1 devices

USART2_SEL

#define USART2_SEL

(

val

)

STM32_CLOCK(val, 3, 2, CCIPR1_REG)

USART3_SEL

#define USART3_SEL

(

val

)

STM32_CLOCK(val, 3, 4, CCIPR1_REG)

USART4_SEL

#define USART4_SEL

(

val

)

STM32_CLOCK(val, 3, 6, CCIPR1_REG)

USART5_SEL

#define USART5_SEL

(

val

)

STM32_CLOCK(val, 3, 8, CCIPR1_REG)