gd32a50x-clocks.h File Reference

#include "gd32-clocks-common.h"

Go to the source code of this file.

Macros
Register offsets
#define	GD32_AHBEN_OFFSET   0x14U
#define	GD32_APB1EN_OFFSET   0x1CU
#define	GD32_APB2EN_OFFSET   0x18U
Clock enable/disable definitions for peripherals
#define	GD32_CLOCK_DMA0   GD32_CLOCK_CONFIG(AHBEN, 0U)
#define	GD32_CLOCK_DMA1   GD32_CLOCK_CONFIG(AHBEN, 1U)
#define	GD32_CLOCK_SRAMSP   GD32_CLOCK_CONFIG(AHBEN, 2U)
#define	GD32_CLOCK_DMAMUX   GD32_CLOCK_CONFIG(AHBEN, 3U)
#define	GD32_CLOCK_FMCSP   GD32_CLOCK_CONFIG(AHBEN, 4U)
#define	GD32_CLOCK_CRC   GD32_CLOCK_CONFIG(AHBEN, 6U)
#define	GD32_CLOCK_MFCOM   GD32_CLOCK_CONFIG(AHBEN, 14U)
#define	GD32_CLOCK_GPIOA   GD32_CLOCK_CONFIG(AHBEN, 17U)
#define	GD32_CLOCK_GPIOB   GD32_CLOCK_CONFIG(AHBEN, 18U)
#define	GD32_CLOCK_GPIOC   GD32_CLOCK_CONFIG(AHBEN, 19U)
#define	GD32_CLOCK_GPIOD   GD32_CLOCK_CONFIG(AHBEN, 20U)
#define	GD32_CLOCK_GPIOE   GD32_CLOCK_CONFIG(AHBEN, 21U)
#define	GD32_CLOCK_GPIOF   GD32_CLOCK_CONFIG(AHBEN, 22U)
#define	GD32_CLOCK_TIMER1   GD32_CLOCK_CONFIG(APB1EN, 0U)
#define	GD32_CLOCK_TIMER5   GD32_CLOCK_CONFIG(APB1EN, 4U)
#define	GD32_CLOCK_TIMER6   GD32_CLOCK_CONFIG(APB1EN, 5U)
#define	GD32_CLOCK_WWDGT   GD32_CLOCK_CONFIG(APB1EN, 11U)
#define	GD32_CLOCK_SPI1   GD32_CLOCK_CONFIG(APB1EN, 14U)
#define	GD32_CLOCK_USART1   GD32_CLOCK_CONFIG(APB1EN, 17U)
#define	GD32_CLOCK_USART2   GD32_CLOCK_CONFIG(APB1EN, 18U)
#define	GD32_CLOCK_I2C0   GD32_CLOCK_CONFIG(APB1EN, 21U)
#define	GD32_CLOCK_I2C1   GD32_CLOCK_CONFIG(APB1EN, 22U)
#define	GD32_CLOCK_BKP   GD32_CLOCK_CONFIG(APB1EN, 26U)
#define	GD32_CLOCK_PMU   GD32_CLOCK_CONFIG(APB1EN, 28U)
#define	GD32_CLOCK_DAC   GD32_CLOCK_CONFIG(APB1EN, 29U)
#define	GD32_CLOCK_SYSCFG   GD32_CLOCK_CONFIG(APB2EN, 0U)
#define	GD32_CLOCK_CMP   GD32_CLOCK_CONFIG(APB2EN, 1U)
#define	GD32_CLOCK_ADC0   GD32_CLOCK_CONFIG(APB2EN, 9U)
#define	GD32_CLOCK_ADC1   GD32_CLOCK_CONFIG(APB2EN, 10U)
#define	GD32_CLOCK_TIMER0   GD32_CLOCK_CONFIG(APB2EN, 11U)
#define	GD32_CLOCK_SPI0   GD32_CLOCK_CONFIG(APB2EN, 12U)
#define	GD32_CLOCK_TIMER7   GD32_CLOCK_CONFIG(APB2EN, 13U)
#define	GD32_CLOCK_USART0   GD32_CLOCK_CONFIG(APB2EN, 14U)
#define	GD32_CLOCK_TIMER19   GD32_CLOCK_CONFIG(APB2EN, 20U)
#define	GD32_CLOCK_TIMER20   GD32_CLOCK_CONFIG(APB2EN, 21U)
#define	GD32_CLOCK_TRIGSEL   GD32_CLOCK_CONFIG(APB2EN, 29U)
#define	GD32_CLOCK_CAN0   GD32_CLOCK_CONFIG(APB2EN, 30U)
#define	GD32_CLOCK_CAN1   GD32_CLOCK_CONFIG(APB2EN, 31U)

Macro Definition Documentation

GD32_AHBEN_OFFSET

#define GD32_AHBEN_OFFSET   0x14U

GD32_APB1EN_OFFSET

#define GD32_APB1EN_OFFSET   0x1CU

GD32_APB2EN_OFFSET

#define GD32_APB2EN_OFFSET   0x18U

GD32_CLOCK_ADC0

#define GD32_CLOCK_ADC0   GD32_CLOCK_CONFIG(APB2EN, 9U)

GD32_CLOCK_ADC1

#define GD32_CLOCK_ADC1   GD32_CLOCK_CONFIG(APB2EN, 10U)

GD32_CLOCK_BKP

#define GD32_CLOCK_BKP   GD32_CLOCK_CONFIG(APB1EN, 26U)

GD32_CLOCK_CAN0

#define GD32_CLOCK_CAN0   GD32_CLOCK_CONFIG(APB2EN, 30U)

GD32_CLOCK_CAN1

#define GD32_CLOCK_CAN1   GD32_CLOCK_CONFIG(APB2EN, 31U)

GD32_CLOCK_CMP

#define GD32_CLOCK_CMP   GD32_CLOCK_CONFIG(APB2EN, 1U)

GD32_CLOCK_CRC

#define GD32_CLOCK_CRC   GD32_CLOCK_CONFIG(AHBEN, 6U)

GD32_CLOCK_DAC

#define GD32_CLOCK_DAC   GD32_CLOCK_CONFIG(APB1EN, 29U)

GD32_CLOCK_DMA0

#define GD32_CLOCK_DMA0   GD32_CLOCK_CONFIG(AHBEN, 0U)

GD32_CLOCK_DMA1

#define GD32_CLOCK_DMA1   GD32_CLOCK_CONFIG(AHBEN, 1U)

GD32_CLOCK_DMAMUX

#define GD32_CLOCK_DMAMUX   GD32_CLOCK_CONFIG(AHBEN, 3U)

GD32_CLOCK_FMCSP

#define GD32_CLOCK_FMCSP   GD32_CLOCK_CONFIG(AHBEN, 4U)

GD32_CLOCK_GPIOA

#define GD32_CLOCK_GPIOA   GD32_CLOCK_CONFIG(AHBEN, 17U)

GD32_CLOCK_GPIOB

#define GD32_CLOCK_GPIOB   GD32_CLOCK_CONFIG(AHBEN, 18U)

GD32_CLOCK_GPIOC

#define GD32_CLOCK_GPIOC   GD32_CLOCK_CONFIG(AHBEN, 19U)

GD32_CLOCK_GPIOD

#define GD32_CLOCK_GPIOD   GD32_CLOCK_CONFIG(AHBEN, 20U)

GD32_CLOCK_GPIOE

#define GD32_CLOCK_GPIOE   GD32_CLOCK_CONFIG(AHBEN, 21U)

GD32_CLOCK_GPIOF

#define GD32_CLOCK_GPIOF   GD32_CLOCK_CONFIG(AHBEN, 22U)

GD32_CLOCK_I2C0

#define GD32_CLOCK_I2C0   GD32_CLOCK_CONFIG(APB1EN, 21U)

GD32_CLOCK_I2C1

#define GD32_CLOCK_I2C1   GD32_CLOCK_CONFIG(APB1EN, 22U)

GD32_CLOCK_MFCOM

#define GD32_CLOCK_MFCOM   GD32_CLOCK_CONFIG(AHBEN, 14U)

GD32_CLOCK_PMU

#define GD32_CLOCK_PMU   GD32_CLOCK_CONFIG(APB1EN, 28U)

GD32_CLOCK_SPI0

#define GD32_CLOCK_SPI0   GD32_CLOCK_CONFIG(APB2EN, 12U)

GD32_CLOCK_SPI1

#define GD32_CLOCK_SPI1   GD32_CLOCK_CONFIG(APB1EN, 14U)

GD32_CLOCK_SRAMSP

#define GD32_CLOCK_SRAMSP   GD32_CLOCK_CONFIG(AHBEN, 2U)

GD32_CLOCK_SYSCFG

#define GD32_CLOCK_SYSCFG   GD32_CLOCK_CONFIG(APB2EN, 0U)

GD32_CLOCK_TIMER0

#define GD32_CLOCK_TIMER0   GD32_CLOCK_CONFIG(APB2EN, 11U)

GD32_CLOCK_TIMER1

#define GD32_CLOCK_TIMER1   GD32_CLOCK_CONFIG(APB1EN, 0U)

GD32_CLOCK_TIMER19

#define GD32_CLOCK_TIMER19   GD32_CLOCK_CONFIG(APB2EN, 20U)

GD32_CLOCK_TIMER20

#define GD32_CLOCK_TIMER20   GD32_CLOCK_CONFIG(APB2EN, 21U)

GD32_CLOCK_TIMER5

#define GD32_CLOCK_TIMER5   GD32_CLOCK_CONFIG(APB1EN, 4U)

GD32_CLOCK_TIMER6

#define GD32_CLOCK_TIMER6   GD32_CLOCK_CONFIG(APB1EN, 5U)

GD32_CLOCK_TIMER7

#define GD32_CLOCK_TIMER7   GD32_CLOCK_CONFIG(APB2EN, 13U)

GD32_CLOCK_TRIGSEL

#define GD32_CLOCK_TRIGSEL   GD32_CLOCK_CONFIG(APB2EN, 29U)

GD32_CLOCK_USART0

#define GD32_CLOCK_USART0   GD32_CLOCK_CONFIG(APB2EN, 14U)

GD32_CLOCK_USART1

#define GD32_CLOCK_USART1   GD32_CLOCK_CONFIG(APB1EN, 17U)

GD32_CLOCK_USART2

#define GD32_CLOCK_USART2   GD32_CLOCK_CONFIG(APB1EN, 18U)

GD32_CLOCK_WWDGT

#define GD32_CLOCK_WWDGT   GD32_CLOCK_CONFIG(APB1EN, 11U)