PCI Express Controller Interface. More...

Data Structures
struct	pcie_ctrl_driver_api
	Structure providing callbacks to be implemented for devices that supports the PCI Express Controller API. More...

struct	pcie_ctrl_config
	Structure describing a device that supports the PCI Express Controller API. More...

Macros
#define	PCIE_RANGE_FORMAT(node_id, idx)

Typedefs
typedef uint32_t(*	pcie_ctrl_conf_read_t) (const struct device *dev, pcie_bdf_t bdf, unsigned int reg)
	Function called to read a 32-bit word from an endpoint's configuration space.

typedef void(*	pcie_ctrl_conf_write_t) (const struct device *dev, pcie_bdf_t bdf, unsigned int reg, uint32_t data)
	Function called to write a 32-bit word to an endpoint's configuration space.

typedef bool(*	pcie_ctrl_region_allocate_t) (const struct device dev, pcie_bdf_t bdf, bool mem, bool mem64, size_t bar_size, uintptr_t bar_bus_addr)
	Function called to allocate a memory region subset for an endpoint Base Address Register.

typedef bool(*	pcie_ctrl_region_get_allocate_base_t) (const struct device dev, pcie_bdf_t bdf, bool mem, bool mem64, size_t align, uintptr_t bar_base_addr)
	Function called to get the current allocation base of a memory region subset for an endpoint Base Address Register.

typedef bool(*	pcie_ctrl_region_translate_t) (const struct device dev, pcie_bdf_t bdf, bool mem, bool mem64, uintptr_t bar_bus_addr, uintptr_t bar_addr)
	Function called to translate an endpoint Base Address Register bus-centric address into Physical address.

Functions
uint32_t	pcie_generic_ctrl_conf_read (mm_reg_t cfg_addr, pcie_bdf_t bdf, unsigned int reg)
	Read a 32-bit word from a Memory-Mapped endpoint's configuration space.

void	pcie_generic_ctrl_conf_write (mm_reg_t cfg_addr, pcie_bdf_t bdf, unsigned int reg, uint32_t data)
	Write a 32-bit word to a Memory-Mapped endpoint's configuration space.

void	pcie_generic_ctrl_enumerate (const struct device *dev, pcie_bdf_t bdf_start)
	Start PCIe Endpoints enumeration.

static uint32_t	pcie_ctrl_conf_read (const struct device *dev, pcie_bdf_t bdf, unsigned int reg)
	Read a 32-bit word from an endpoint's configuration space.

static void	pcie_ctrl_conf_write (const struct device *dev, pcie_bdf_t bdf, unsigned int reg, uint32_t data)
	Write a 32-bit word to an endpoint's configuration space.

static bool	pcie_ctrl_region_allocate (const struct device dev, pcie_bdf_t bdf, bool mem, bool mem64, size_t bar_size, uintptr_t bar_bus_addr)
	Allocate a memory region subset for an endpoint Base Address Register.

static bool	pcie_ctrl_region_get_allocate_base (const struct device dev, pcie_bdf_t bdf, bool mem, bool mem64, size_t align, uintptr_t bar_base_addr)
	Function called to get the current allocation base of a memory region subset for an endpoint Base Address Register.

static bool	pcie_ctrl_region_translate (const struct device dev, pcie_bdf_t bdf, bool mem, bool mem64, uintptr_t bar_bus_addr, uintptr_t bar_addr)
	Translate an endpoint Base Address Register bus-centric address into Physical address.

Detailed Description

PCI Express Controller Interface.

Macro Definition Documentation

◆ PCIE_RANGE_FORMAT

#define PCIE_RANGE_FORMAT	(	node_id,
		idx
	)

#include <zephyr/drivers/pcie/controller.h>

Value:

{                                                                                       \
        .flags = DT_RANGES_CHILD_BUS_FLAGS_BY_IDX(node_id, idx),                        \
        .pcie_bus_addr = DT_RANGES_CHILD_BUS_ADDRESS_BY_IDX(node_id, idx),              \
        .host_map_addr = DT_RANGES_PARENT_BUS_ADDRESS_BY_IDX(node_id, idx),             \
        .map_length = DT_RANGES_LENGTH_BY_IDX(node_id, idx),                            \
},

Typedef Documentation

◆ pcie_ctrl_conf_read_t

typedef uint32_t(* pcie_ctrl_conf_read_t) (const struct device *dev, pcie_bdf_t bdf, unsigned int reg)

#include <zephyr/drivers/pcie/controller.h>

Function called to read a 32-bit word from an endpoint's configuration space.

Read a 32-bit word from an endpoint's configuration space with the PCI Express Controller configuration space access method (I/O port, memory mapped or custom method)

Parameters

dev	PCI Express Controller device pointer
bdf	PCI(e) endpoint
reg	the configuration word index (not address)

Returns: the word read (0xFFFFFFFFU if nonexistent endpoint or word)

◆ pcie_ctrl_conf_write_t

typedef void(* pcie_ctrl_conf_write_t) (const struct device *dev, pcie_bdf_t bdf, unsigned int reg, uint32_t data)

#include <zephyr/drivers/pcie/controller.h>

Function called to write a 32-bit word to an endpoint's configuration space.

Write a 32-bit word to an endpoint's configuration space with the PCI Express Controller configuration space access method (I/O port, memory mapped or custom method)

Parameters

dev	PCI Express Controller device pointer
bdf	PCI(e) endpoint
reg	the configuration word index (not address)
data	the value to write

◆ pcie_ctrl_region_allocate_t

typedef bool(* pcie_ctrl_region_allocate_t) (const struct device *dev, pcie_bdf_t bdf, bool mem, bool mem64, size_t bar_size, uintptr_t *bar_bus_addr)

#include <zephyr/drivers/pcie/controller.h>

Function called to allocate a memory region subset for an endpoint Base Address Register.

When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones via the Base Address Registers from I/O or Memory types.

This call allocates such zone in the PCI Express Controller memory regions if such region is available and space is still available.

Parameters

dev	PCI Express Controller device pointer
bdf	PCI(e) endpoint
mem	True if the BAR is of memory type
mem64	True if the BAR is of 64bit memory type
bar_size	Size in bytes of the Base Address Register as returned by HW
bar_bus_addr	bus-centric address allocated to be written in the BAR register

Returns: True if allocation was possible, False if allocation failed

◆ pcie_ctrl_region_get_allocate_base_t

typedef bool(* pcie_ctrl_region_get_allocate_base_t) (const struct device *dev, pcie_bdf_t bdf, bool mem, bool mem64, size_t align, uintptr_t *bar_base_addr)

#include <zephyr/drivers/pcie/controller.h>

Function called to get the current allocation base of a memory region subset for an endpoint Base Address Register.

When enumerating PCIe Endpoints, Type1 bridge endpoints requires a range of memory allocated by all endpoints in the bridged bus.

Parameters

dev	PCI Express Controller device pointer
bdf	PCI(e) endpoint
mem	True if the BAR is of memory type
mem64	True if the BAR is of 64bit memory type
align	size to take in account for alignment
bar_base_addr	bus-centric address allocation base

Returns: True if allocation was possible, False if allocation failed

◆ pcie_ctrl_region_translate_t

typedef bool(* pcie_ctrl_region_translate_t) (const struct device *dev, pcie_bdf_t bdf, bool mem, bool mem64, uintptr_t bar_bus_addr, uintptr_t *bar_addr)

#include <zephyr/drivers/pcie/controller.h>

Function called to translate an endpoint Base Address Register bus-centric address into Physical address.

When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones via the Base Address Registers from I/O or Memory types.

The bus-centric address set in this BAR register is not necessarily accessible from the CPU, thus must be translated by using the PCI Express Controller memory regions translation ranges to permit mapping from the CPU.

Parameters

dev	PCI Express Controller device pointer
bdf	PCI(e) endpoint
mem	True if the BAR is of memory type
mem64	True if the BAR is of 64bit memory type
bar_bus_addr	bus-centric address written in the BAR register
bar_addr	CPU-centric address translated from the bus-centric address

Returns: True if translation was possible, False if translation failed

Function Documentation

◆ pcie_ctrl_conf_read()

static uint32_t pcie_ctrl_conf_read	(	const struct device *	dev,
		pcie_bdf_t	bdf,
		unsigned int	reg
	)

inlinestatic

#include <zephyr/drivers/pcie/controller.h>

Read a 32-bit word from an endpoint's configuration space.

Read a 32-bit word from an endpoint's configuration space with the PCI Express Controller configuration space access method (I/O port, memory mapped or custom method)

Parameters

dev	PCI Express Controller device pointer
bdf	PCI(e) endpoint
reg	the configuration word index (not address)

Returns: the word read (0xFFFFFFFFU if nonexistent endpoint or word)

◆ pcie_ctrl_conf_write()

static void pcie_ctrl_conf_write	(	const struct device *	dev,
		pcie_bdf_t	bdf,
		unsigned int	reg,
		uint32_t	data
	)

inlinestatic

#include <zephyr/drivers/pcie/controller.h>

Write a 32-bit word to an endpoint's configuration space.

Write a 32-bit word to an endpoint's configuration space with the PCI Express Controller configuration space access method (I/O port, memory mapped or custom method)

Parameters

dev	PCI Express Controller device pointer
bdf	PCI(e) endpoint
reg	the configuration word index (not address)
data	the value to write

◆ pcie_ctrl_region_allocate()

static bool pcie_ctrl_region_allocate	(	const struct device *	dev,
		pcie_bdf_t	bdf,
		bool	mem,
		bool	mem64,
		size_t	bar_size,
		uintptr_t *	bar_bus_addr
	)

inlinestatic

#include <zephyr/drivers/pcie/controller.h>

Allocate a memory region subset for an endpoint Base Address Register.

When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones via the Base Address Registers from I/O or Memory types.

This call allocates such zone in the PCI Express Controller memory regions if such region is available and space is still available.

Parameters

dev	PCI Express Controller device pointer
bdf	PCI(e) endpoint
mem	True if the BAR is of memory type
mem64	True if the BAR is of 64bit memory type
bar_size	Size in bytes of the Base Address Register as returned by HW
bar_bus_addr	bus-centric address allocated to be written in the BAR register

Returns: True if allocation was possible, False if allocation failed

◆ pcie_ctrl_region_get_allocate_base()

static bool pcie_ctrl_region_get_allocate_base	(	const struct device *	dev,
		pcie_bdf_t	bdf,
		bool	mem,
		bool	mem64,
		size_t	align,
		uintptr_t *	bar_base_addr
	)

inlinestatic

#include <zephyr/drivers/pcie/controller.h>

Function called to get the current allocation base of a memory region subset for an endpoint Base Address Register.

When enumerating PCIe Endpoints, Type1 bridge endpoints requires a range of memory allocated by all endpoints in the bridged bus.

Parameters

dev	PCI Express Controller device pointer
bdf	PCI(e) endpoint
mem	True if the BAR is of memory type
mem64	True if the BAR is of 64bit memory type
align	size to take in account for alignment
bar_base_addr	bus-centric address allocation base

Returns: True if allocation was possible, False if allocation failed

◆ pcie_ctrl_region_translate()

static bool pcie_ctrl_region_translate	(	const struct device *	dev,
		pcie_bdf_t	bdf,
		bool	mem,
		bool	mem64,
		uintptr_t	bar_bus_addr,
		uintptr_t *	bar_addr
	)

inlinestatic

#include <zephyr/drivers/pcie/controller.h>

Translate an endpoint Base Address Register bus-centric address into Physical address.

When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones via the Base Address Registers from I/O or Memory types.

The bus-centric address set in this BAR register is not necessarily accessible from the CPU, thus must be translated by using the PCI Express Controller memory regions translation ranges to permit mapping from the CPU.

Parameters

dev	PCI Express Controller device pointer
bdf	PCI(e) endpoint
mem	True if the BAR is of memory type
mem64	True if the BAR is of 64bit memory type
bar_bus_addr	bus-centric address written in the BAR register
bar_addr	CPU-centric address translated from the bus-centric address

Returns: True if translation was possible, False if translation failed

◆ pcie_generic_ctrl_conf_read()

uint32_t pcie_generic_ctrl_conf_read	(	mm_reg_t	cfg_addr,
		pcie_bdf_t	bdf,
		unsigned int	reg
	)

#include <zephyr/drivers/pcie/controller.h>

Read a 32-bit word from a Memory-Mapped endpoint's configuration space.

Read a 32-bit word from an endpoint's configuration space from a Memory-Mapped configuration space access method, known as PCI Control Access Method (CAM) or PCIe Extended Control Access Method (ECAM).

Parameters

cfg_addr	Logical address of Memory-Mapped configuration space
bdf	PCI(e) endpoint
reg	the configuration word index (not address)

Returns: the word read (0xFFFFFFFFU if nonexistent endpoint or word)

◆ pcie_generic_ctrl_conf_write()

void pcie_generic_ctrl_conf_write	(	mm_reg_t	cfg_addr,
		pcie_bdf_t	bdf,
		unsigned int	reg,
		uint32_t	data
	)

#include <zephyr/drivers/pcie/controller.h>

Write a 32-bit word to a Memory-Mapped endpoint's configuration space.

Write a 32-bit word to an endpoint's configuration space from a Memory-Mapped configuration space access method, known as PCI Control Access Method (CAM) or PCIe Extended Control Access Method (ECAM).

Parameters

cfg_addr	Logical address of Memory-Mapped configuration space
bdf	PCI(e) endpoint
reg	the configuration word index (not address)
data	the value to write

◆ pcie_generic_ctrl_enumerate()

void pcie_generic_ctrl_enumerate	(	const struct device *	dev,
		pcie_bdf_t	bdf_start
	)

#include <zephyr/drivers/pcie/controller.h>

Start PCIe Endpoints enumeration.

Start a PCIe Endpoints enumeration from a Bus number. When on non-x86 architecture or when firmware didn't setup the PCIe Bus hierarchy, the PCIe bus complex must be enumerated to setup the Endpoints Base Address Registers.

Parameters

dev	PCI Express Controller device pointer
bdf_start	PCI(e) start endpoint (only bus & dev are used to start enumeration)

Data Structures

Macros

Typedefs

Functions

Detailed Description

Macro Definition Documentation

◆ PCIE_RANGE_FORMAT

Typedef Documentation

◆ pcie_ctrl_conf_read_t

◆ pcie_ctrl_conf_write_t

◆ pcie_ctrl_region_allocate_t

◆ pcie_ctrl_region_get_allocate_base_t

◆ pcie_ctrl_region_translate_t

Function Documentation

◆ pcie_ctrl_conf_read()

◆ pcie_ctrl_conf_write()

◆ pcie_ctrl_region_allocate()

◆ pcie_ctrl_region_get_allocate_base()

◆ pcie_ctrl_region_translate()

◆ pcie_generic_ctrl_conf_read()

◆ pcie_generic_ctrl_conf_write()

◆ pcie_generic_ctrl_enumerate()