Zephyr API Documentation  3.7.0
A Scalable Open Source RTOS
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intc_esp32c3.h File Reference
#include <stdint.h>
#include <stdbool.h>
#include <soc.h>

Go to the source code of this file.

Macros

#define ESP_INTR_FLAG_LEVEL1   (1<<1) /* Accept a Level 1 int vector, lowest priority */
 
#define ESP_INTR_FLAG_LEVEL2   (1<<2) /* Accept a Level 2 int vector */
 
#define ESP_INTR_FLAG_LEVEL3   (1<<3) /* Accept a Level 3 int vector */
 
#define ESP_INTR_FLAG_LEVEL4   (1<<4) /* Accept a Level 4 int vector */
 
#define ESP_INTR_FLAG_LEVEL5   (1<<5) /* Accept a Level 5 int vector */
 
#define ESP_INTR_FLAG_LEVEL6   (1<<6) /* Accept a Level 6 int vector */
 
#define ESP_INTR_FLAG_NMI   (1<<7) /* Accept a Level 7 int vector, highest priority */
 
#define ESP_INTR_FLAG_SHARED   (1<<8) /* Interrupt can be shared between ISRs */
 
#define ESP_INTR_FLAG_EDGE   (1<<9) /* Edge-triggered interrupt */
 
#define ESP_INTR_FLAG_IRAM   (1<<10) /* ISR can be called if cache is disabled */
 
#define ESP_INTR_FLAG_INTRDISABLED   (1<<11) /* Return with this interrupt disabled */
 
#define ESP_INTR_FLAG_LOWMED   (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3)
 
#define ESP_INTR_FLAG_HIGH
 
#define ESP_INTR_FLAG_LEVELMASK
 

Typedefs

typedef void(* isr_handler_t) (const void *arg)
 

Functions

void esp_intr_initialize (void)
 Initializes interrupt table to its defaults.
 
int esp_intr_alloc (int source, int flags, isr_handler_t handler, void *arg, void **ret_handle)
 Allocate an interrupt with the given parameters.
 
int esp_intr_disable (int source)
 Disable the interrupt associated with the source.
 
int esp_intr_enable (int source)
 Enable the interrupt associated with the source.
 
uint32_t esp_intr_get_enabled_intmask (int status_mask_number)
 Gets the current enabled interrupts.
 

Macro Definition Documentation

◆ ESP_INTR_FLAG_EDGE

#define ESP_INTR_FLAG_EDGE   (1<<9) /* Edge-triggered interrupt */

◆ ESP_INTR_FLAG_HIGH

#define ESP_INTR_FLAG_HIGH
Value:
#define ESP_INTR_FLAG_LEVEL5
Definition: intc_esp32c3.h:23
#define ESP_INTR_FLAG_LEVEL6
Definition: intc_esp32c3.h:24
#define ESP_INTR_FLAG_NMI
Definition: intc_esp32c3.h:25
#define ESP_INTR_FLAG_LEVEL4
Definition: intc_esp32c3.h:22

◆ ESP_INTR_FLAG_INTRDISABLED

#define ESP_INTR_FLAG_INTRDISABLED   (1<<11) /* Return with this interrupt disabled */

◆ ESP_INTR_FLAG_IRAM

#define ESP_INTR_FLAG_IRAM   (1<<10) /* ISR can be called if cache is disabled */

◆ ESP_INTR_FLAG_LEVEL1

#define ESP_INTR_FLAG_LEVEL1   (1<<1) /* Accept a Level 1 int vector, lowest priority */

◆ ESP_INTR_FLAG_LEVEL2

#define ESP_INTR_FLAG_LEVEL2   (1<<2) /* Accept a Level 2 int vector */

◆ ESP_INTR_FLAG_LEVEL3

#define ESP_INTR_FLAG_LEVEL3   (1<<3) /* Accept a Level 3 int vector */

◆ ESP_INTR_FLAG_LEVEL4

#define ESP_INTR_FLAG_LEVEL4   (1<<4) /* Accept a Level 4 int vector */

◆ ESP_INTR_FLAG_LEVEL5

#define ESP_INTR_FLAG_LEVEL5   (1<<5) /* Accept a Level 5 int vector */

◆ ESP_INTR_FLAG_LEVEL6

#define ESP_INTR_FLAG_LEVEL6   (1<<6) /* Accept a Level 6 int vector */

◆ ESP_INTR_FLAG_LEVELMASK

#define ESP_INTR_FLAG_LEVELMASK
Value:
#define ESP_INTR_FLAG_LEVEL3
Definition: intc_esp32c3.h:21
#define ESP_INTR_FLAG_LEVEL2
Definition: intc_esp32c3.h:20
#define ESP_INTR_FLAG_LEVEL1
Definition: intc_esp32c3.h:19

◆ ESP_INTR_FLAG_LOWMED

#define ESP_INTR_FLAG_LOWMED   (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3)

◆ ESP_INTR_FLAG_NMI

#define ESP_INTR_FLAG_NMI   (1<<7) /* Accept a Level 7 int vector, highest priority */

◆ ESP_INTR_FLAG_SHARED

#define ESP_INTR_FLAG_SHARED   (1<<8) /* Interrupt can be shared between ISRs */

Typedef Documentation

◆ isr_handler_t

typedef void(* isr_handler_t) (const void *arg)

Function Documentation

◆ esp_intr_alloc()

int esp_intr_alloc ( int  source,
int  flags,
isr_handler_t  handler,
void *  arg,
void **  ret_handle 
)

Allocate an interrupt with the given parameters.

This finds an interrupt that matches the restrictions as given in the flags parameter, maps the given interrupt source to it and hooks up the given interrupt handler (with optional argument) as well. If needed, it can return a handle for the interrupt as well.

Parameters
sourceThe interrupt source.
flagsAn ORred mask of the ESP_INTR_FLAG_* defines. These restrict the choice of interrupts that this routine can choose from. If this value is 0, it will default to allocating a non-shared interrupt of level 1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return from this function with the interrupt disabled.
handlerThe interrupt handler.
argOptional argument for passed to the interrupt handler
ret_handlePointer to a struct intr_handle_data_t pointer to store a handle that can later be used to request details or free the interrupt. Can be NULL if no handle is required.
Returns
-EINVAL if the combination of arguments is invalid. -ENODEV No free interrupt found with the specified flags 0 otherwise

◆ esp_intr_disable()

int esp_intr_disable ( int  source)

Disable the interrupt associated with the source.

Parameters
sourceThe interrupt source
Returns
-EINVAL if the combination of arguments is invalid. 0 otherwise

◆ esp_intr_enable()

int esp_intr_enable ( int  source)

Enable the interrupt associated with the source.

Parameters
sourceThe interrupt source
Returns
-EINVAL if the combination of arguments is invalid. 0 otherwise

◆ esp_intr_get_enabled_intmask()

uint32_t esp_intr_get_enabled_intmask ( int  status_mask_number)

Gets the current enabled interrupts.

Parameters
status_mask_numberthe status mask can be 0 or 1
Returns
bitmask of enabled interrupt sources

◆ esp_intr_initialize()

void esp_intr_initialize ( void  )

Initializes interrupt table to its defaults.