Zephyr API Documentation  3.7.0
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
Macros
stm32f1-afio.h File Reference

Go to the source code of this file.

Macros

#define STM32_REMAP_REG_MASK   0x1U
 
#define STM32_REMAP_REG_SHIFT   0U
 
#define STM32_REMAP_SHIFT_MASK   0x1FU
 
#define STM32_REMAP_SHIFT_SHIFT   1U
 
#define STM32_REMAP_MASK_MASK   0x3U
 
#define STM32_REMAP_MASK_SHIFT   6U
 
#define STM32_REMAP_VAL_MASK   0x3U
 
#define STM32_REMAP_VAL_SHIFT   8U
 
#define STM32_REMAP(val, mask, shift, reg)
 STM32F1 Remap configuration bit field.
 
#define STM32_REMAP_REG_GET(remap)    (((remap) >> STM32_REMAP_REG_SHIFT) & STM32_REMAP_REG_MASK)
 Obtain register field from remap configuration.
 
#define STM32_REMAP_SHIFT_GET(remap)    (((remap) >> STM32_REMAP_SHIFT_SHIFT) & STM32_REMAP_SHIFT_MASK)
 Obtain position field from remap configuration.
 
#define STM32_REMAP_MASK_GET(remap)    (((remap) >> STM32_REMAP_MASK_SHIFT) & STM32_REMAP_MASK_MASK)
 Obtain mask field from remap configuration.
 
#define STM32_REMAP_VAL_GET(remap)    (((remap) >> STM32_REMAP_VAL_SHIFT) & STM32_REMAP_VAL_MASK)
 Obtain value field from remap configuration.
 
#define STM32_AFIO_MAPR   0U
 
#define STM32_AFIO_MAPR2   1U
 
#define NO_REMAP   0
 Device not remappable.
 
#define SPI1_REMAP0   STM32_REMAP(0U, 0x1U, 0U, STM32_AFIO_MAPR)
 SPI1 (no remap)
 
#define SPI1_REMAP1   STM32_REMAP(1U, 0x1U, 0U, STM32_AFIO_MAPR)
 SPI1 (remap)
 
#define I2C1_REMAP0   STM32_REMAP(0U, 0x1U, 1U, STM32_AFIO_MAPR)
 I2C1 (no remap)
 
#define I2C1_REMAP1   STM32_REMAP(1U, 0x1U, 1U, STM32_AFIO_MAPR)
 I2C1 (remap)
 
#define USART1_REMAP0   STM32_REMAP(0U, 0x1U, 2U, STM32_AFIO_MAPR)
 USART1 (no remap)
 
#define USART1_REMAP1   STM32_REMAP(1U, 0x1U, 2U, STM32_AFIO_MAPR)
 USART1 (remap)
 
#define USART2_REMAP0   STM32_REMAP(0U, 0x1U, 3U, STM32_AFIO_MAPR)
 USART2 (no remap)
 
#define USART2_REMAP1   STM32_REMAP(1U, 0x1U, 3U, STM32_AFIO_MAPR)
 USART2 (remap)
 
#define USART3_REMAP0   STM32_REMAP(0U, 0x3U, 4U, STM32_AFIO_MAPR)
 USART3 (no remap)
 
#define USART3_REMAP1   STM32_REMAP(1U, 0x3U, 4U, STM32_AFIO_MAPR)
 USART3 (partial remap)
 
#define USART3_REMAP2   STM32_REMAP(3U, 0x3U, 4U, STM32_AFIO_MAPR)
 USART3 (full remap)
 
#define TIM1_REMAP0   STM32_REMAP(0U, 0x3U, 6U, STM32_AFIO_MAPR)
 TIM1 (no remap)
 
#define TIM1_REMAP1   STM32_REMAP(1U, 0x3U, 6U, STM32_AFIO_MAPR)
 TIM1 (partial remap)
 
#define TIM1_REMAP2   STM32_REMAP(3U, 0x3U, 6U, STM32_AFIO_MAPR)
 TIM1 (full remap)
 
#define TIM2_REMAP0   STM32_REMAP(0U, 0x3U, 8U, STM32_AFIO_MAPR)
 TIM2 (no remap)
 
#define TIM2_REMAP1   STM32_REMAP(1U, 0x3U, 8U, STM32_AFIO_MAPR)
 TIM2 (partial remap 1)
 
#define TIM2_REMAP2   STM32_REMAP(2U, 0x3U, 8U, STM32_AFIO_MAPR)
 TIM2 (partial remap 2)
 
#define TIM2_REMAP3   STM32_REMAP(3U, 0x3U, 8U, STM32_AFIO_MAPR)
 TIM2 (full remap)
 
#define TIM3_REMAP0   STM32_REMAP(0U, 0x3U, 10U, STM32_AFIO_MAPR)
 TIM3 (no remap)
 
#define TIM3_REMAP1   STM32_REMAP(1U, 0x3U, 10U, STM32_AFIO_MAPR)
 TIM3 (partial remap 1)
 
#define TIM3_REMAP2   STM32_REMAP(2U, 0x3U, 10U, STM32_AFIO_MAPR)
 TIM3 (partial remap 2)
 
#define TIM3_REMAP3   STM32_REMAP(3U, 0x3U, 10U, STM32_AFIO_MAPR)
 TIM3 (full remap)
 
#define TIM4_REMAP0   STM32_REMAP(0U, 0x1U, 12U, STM32_AFIO_MAPR)
 TIM4 (no remap)
 
#define TIM4_REMAP1   STM32_REMAP(1U, 0x1U, 12U, STM32_AFIO_MAPR)
 TIM4 (remap)
 
#define CAN_REMAP0   STM32_REMAP(0U, 0x3U, 13U, STM32_AFIO_MAPR)
 CAN (no remap)
 
#define CAN_REMAP1   STM32_REMAP(2U, 0x3U, 13U, STM32_AFIO_MAPR)
 CAN (partial remap)
 
#define CAN_REMAP2   STM32_REMAP(3U, 0x3U, 13U, STM32_AFIO_MAPR)
 CAN (full remap)
 
#define CAN1_REMAP0   CAN_REMAP0
 CAN1 alias.
 
#define CAN1_REMAP1   CAN_REMAP1
 
#define CAN1_REMAP2   CAN_REMAP2
 
#define ETH_REMAP0   STM32_REMAP(0U, 0x1U, 21U, STM32_AFIO_MAPR)
 ETH (no remap)
 
#define ETH_REMAP1   STM32_REMAP(1U, 0x1U, 21U, STM32_AFIO_MAPR)
 ETH (remap)
 
#define CAN2_REMAP0   STM32_REMAP(0U, 0x1U, 22U, STM32_AFIO_MAPR)
 CAN2 (no remap)
 
#define CAN2_REMAP1   STM32_REMAP(1U, 0x1U, 22U, STM32_AFIO_MAPR)
 CAN2 (remap)
 
#define SPI3_REMAP0   STM32_REMAP(0U, 0x1U, 28U, STM32_AFIO_MAPR)
 SPI3 (no remap)
 
#define SPI3_REMAP1   STM32_REMAP(1U, 0x1U, 28U, STM32_AFIO_MAPR)
 SPI3 (remap)
 
#define I2S3_REMAP0   SPI3_REMAP0
 I2S3 (SPI3) (no remap)
 
#define I2S3_REMAP1   SPI3_REMAP1
 I2S3 (SPI3) (remap)
 
#define TIM9_REMAP0   STM32_REMAP(0U, 0x1U, 5U, STM32_AFIO_MAPR2)
 TIM9 (no remap)
 
#define TIM9_REMAP1   STM32_REMAP(1U, 0x1U, 5U, STM32_AFIO_MAPR2)
 TIM9 (remap)
 
#define TIM10_REMAP0   STM32_REMAP(0U, 0x1U, 6U, STM32_AFIO_MAPR2)
 TIM10 (no remap)
 
#define TIM10_REMAP1   STM32_REMAP(1U, 0x1U, 6U, STM32_AFIO_MAPR2)
 TIM10 (remap)
 
#define TIM11_REMAP0   STM32_REMAP(0U, 0x1U, 7U, STM32_AFIO_MAPR2)
 TIM11 (no remap)
 
#define TIM11_REMAP1   STM32_REMAP(1U, 0x1U, 7U, STM32_AFIO_MAPR2)
 TIM11 (remap)
 
#define TIM13_REMAP0   STM32_REMAP(0U, 0x1U, 8U, STM32_AFIO_MAPR2)
 TIM13 (no remap)
 
#define TIM13_REMAP1   STM32_REMAP(1U, 0x1U, 8U, STM32_AFIO_MAPR2)
 TIM13 (remap)
 
#define TIM14_REMAP0   STM32_REMAP(0U, 0x1U, 9U, STM32_AFIO_MAPR2)
 TIM14 (no remap)
 
#define TIM14_REMAP1   STM32_REMAP(1U, 0x1U, 9U, STM32_AFIO_MAPR2)
 TIM14 (remap)
 
#define TIM15_REMAP0   STM32_REMAP(0U, 0x1U, 0U, STM32_AFIO_MAPR2)
 TIM15 (no remap)
 
#define TIM15_REMAP1   STM32_REMAP(1U, 0x1U, 0U, STM32_AFIO_MAPR2)
 TIM15 (remap)
 
#define TIM16_REMAP0   STM32_REMAP(0U, 0x1U, 1U, STM32_AFIO_MAPR2)
 TIM16 (no remap)
 
#define TIM16_REMAP1   STM32_REMAP(1U, 0x1U, 1U, STM32_AFIO_MAPR2)
 TIM16 (remap)
 
#define TIM17_REMAP0   STM32_REMAP(0U, 0x1U, 2U, STM32_AFIO_MAPR2)
 TIM17 (no remap)
 
#define TIM17_REMAP1   STM32_REMAP(1U, 0x1U, 2U, STM32_AFIO_MAPR2)
 TIM17 (remap)
 

Macro Definition Documentation

◆ CAN1_REMAP0

#define CAN1_REMAP0   CAN_REMAP0

CAN1 alias.

◆ CAN1_REMAP1

#define CAN1_REMAP1   CAN_REMAP1

◆ CAN1_REMAP2

#define CAN1_REMAP2   CAN_REMAP2

◆ CAN2_REMAP0

#define CAN2_REMAP0   STM32_REMAP(0U, 0x1U, 22U, STM32_AFIO_MAPR)

CAN2 (no remap)

◆ CAN2_REMAP1

#define CAN2_REMAP1   STM32_REMAP(1U, 0x1U, 22U, STM32_AFIO_MAPR)

CAN2 (remap)

◆ CAN_REMAP0

#define CAN_REMAP0   STM32_REMAP(0U, 0x3U, 13U, STM32_AFIO_MAPR)

CAN (no remap)

◆ CAN_REMAP1

#define CAN_REMAP1   STM32_REMAP(2U, 0x3U, 13U, STM32_AFIO_MAPR)

CAN (partial remap)

◆ CAN_REMAP2

#define CAN_REMAP2   STM32_REMAP(3U, 0x3U, 13U, STM32_AFIO_MAPR)

CAN (full remap)

◆ ETH_REMAP0

#define ETH_REMAP0   STM32_REMAP(0U, 0x1U, 21U, STM32_AFIO_MAPR)

ETH (no remap)

◆ ETH_REMAP1

#define ETH_REMAP1   STM32_REMAP(1U, 0x1U, 21U, STM32_AFIO_MAPR)

ETH (remap)

◆ I2C1_REMAP0

#define I2C1_REMAP0   STM32_REMAP(0U, 0x1U, 1U, STM32_AFIO_MAPR)

I2C1 (no remap)

◆ I2C1_REMAP1

#define I2C1_REMAP1   STM32_REMAP(1U, 0x1U, 1U, STM32_AFIO_MAPR)

I2C1 (remap)

◆ I2S3_REMAP0

#define I2S3_REMAP0   SPI3_REMAP0

I2S3 (SPI3) (no remap)

◆ I2S3_REMAP1

#define I2S3_REMAP1   SPI3_REMAP1

I2S3 (SPI3) (remap)

◆ NO_REMAP

#define NO_REMAP   0

Device not remappable.

◆ SPI1_REMAP0

#define SPI1_REMAP0   STM32_REMAP(0U, 0x1U, 0U, STM32_AFIO_MAPR)

SPI1 (no remap)

◆ SPI1_REMAP1

#define SPI1_REMAP1   STM32_REMAP(1U, 0x1U, 0U, STM32_AFIO_MAPR)

SPI1 (remap)

◆ SPI3_REMAP0

#define SPI3_REMAP0   STM32_REMAP(0U, 0x1U, 28U, STM32_AFIO_MAPR)

SPI3 (no remap)

◆ SPI3_REMAP1

#define SPI3_REMAP1   STM32_REMAP(1U, 0x1U, 28U, STM32_AFIO_MAPR)

SPI3 (remap)

◆ STM32_AFIO_MAPR

#define STM32_AFIO_MAPR   0U

◆ STM32_AFIO_MAPR2

#define STM32_AFIO_MAPR2   1U

◆ STM32_REMAP

#define STM32_REMAP (   val,
  mask,
  shift,
  reg 
)
Value:
((((reg) & STM32_REMAP_REG_MASK) << STM32_REMAP_REG_SHIFT) | \
(((shift) & STM32_REMAP_SHIFT_MASK) << STM32_REMAP_SHIFT_SHIFT) | \
(((mask) & STM32_REMAP_MASK_MASK) << STM32_REMAP_MASK_SHIFT) | \
(((val) & STM32_REMAP_VAL_MASK) << STM32_REMAP_VAL_SHIFT))
STM32_REMAP_VAL_SHIFT
#define STM32_REMAP_VAL_SHIFT
Definition: stm32f1-afio.h:17
STM32_REMAP_SHIFT_SHIFT
#define STM32_REMAP_SHIFT_SHIFT
Definition: stm32f1-afio.h:13
STM32_REMAP_SHIFT_MASK
#define STM32_REMAP_SHIFT_MASK
Definition: stm32f1-afio.h:12
STM32_REMAP_MASK_SHIFT
#define STM32_REMAP_MASK_SHIFT
Definition: stm32f1-afio.h:15
STM32_REMAP_MASK_MASK
#define STM32_REMAP_MASK_MASK
Definition: stm32f1-afio.h:14
STM32_REMAP_VAL_MASK
#define STM32_REMAP_VAL_MASK
Definition: stm32f1-afio.h:16
STM32_REMAP_REG_SHIFT
#define STM32_REMAP_REG_SHIFT
Definition: stm32f1-afio.h:11
STM32_REMAP_REG_MASK
#define STM32_REMAP_REG_MASK
Definition: stm32f1-afio.h:10

STM32F1 Remap configuration bit field.

  • reg (0/1) [ 0 : 0 ]
  • shift (0..31) [ 1 : 5 ]
  • mask (0x1, 0x3) [ 6 : 7 ]
  • val (0..3) [ 8 : 9 ]
Parameters
regAFIO_MAPRx register (MAPR, MAPR2).
shiftPosition within AFIO_MAPRx.
maskMask for the AFIO_MAPRx field.
valRemap value (0, 1, 2 or 3).

◆ STM32_REMAP_MASK_GET

#define STM32_REMAP_MASK_GET (   remap)     (((remap) >> STM32_REMAP_MASK_SHIFT) & STM32_REMAP_MASK_MASK)

Obtain mask field from remap configuration.

Parameters
remapRemap bit field value.

◆ STM32_REMAP_MASK_MASK

#define STM32_REMAP_MASK_MASK   0x3U

◆ STM32_REMAP_MASK_SHIFT

#define STM32_REMAP_MASK_SHIFT   6U

◆ STM32_REMAP_REG_GET

#define STM32_REMAP_REG_GET (   remap)     (((remap) >> STM32_REMAP_REG_SHIFT) & STM32_REMAP_REG_MASK)

Obtain register field from remap configuration.

Parameters
remapRemap bit field value.

◆ STM32_REMAP_REG_MASK

#define STM32_REMAP_REG_MASK   0x1U

◆ STM32_REMAP_REG_SHIFT

#define STM32_REMAP_REG_SHIFT   0U

◆ STM32_REMAP_SHIFT_GET

#define STM32_REMAP_SHIFT_GET (   remap)     (((remap) >> STM32_REMAP_SHIFT_SHIFT) & STM32_REMAP_SHIFT_MASK)

Obtain position field from remap configuration.

Parameters
remapRemap bit field value.

◆ STM32_REMAP_SHIFT_MASK

#define STM32_REMAP_SHIFT_MASK   0x1FU

◆ STM32_REMAP_SHIFT_SHIFT

#define STM32_REMAP_SHIFT_SHIFT   1U

◆ STM32_REMAP_VAL_GET

#define STM32_REMAP_VAL_GET (   remap)     (((remap) >> STM32_REMAP_VAL_SHIFT) & STM32_REMAP_VAL_MASK)

Obtain value field from remap configuration.

Parameters
remapRemap bit field value.

◆ STM32_REMAP_VAL_MASK

#define STM32_REMAP_VAL_MASK   0x3U

◆ STM32_REMAP_VAL_SHIFT

#define STM32_REMAP_VAL_SHIFT   8U

◆ TIM10_REMAP0

#define TIM10_REMAP0   STM32_REMAP(0U, 0x1U, 6U, STM32_AFIO_MAPR2)

TIM10 (no remap)

◆ TIM10_REMAP1

#define TIM10_REMAP1   STM32_REMAP(1U, 0x1U, 6U, STM32_AFIO_MAPR2)

TIM10 (remap)

◆ TIM11_REMAP0

#define TIM11_REMAP0   STM32_REMAP(0U, 0x1U, 7U, STM32_AFIO_MAPR2)

TIM11 (no remap)

◆ TIM11_REMAP1

#define TIM11_REMAP1   STM32_REMAP(1U, 0x1U, 7U, STM32_AFIO_MAPR2)

TIM11 (remap)

◆ TIM13_REMAP0

#define TIM13_REMAP0   STM32_REMAP(0U, 0x1U, 8U, STM32_AFIO_MAPR2)

TIM13 (no remap)

◆ TIM13_REMAP1

#define TIM13_REMAP1   STM32_REMAP(1U, 0x1U, 8U, STM32_AFIO_MAPR2)

TIM13 (remap)

◆ TIM14_REMAP0

#define TIM14_REMAP0   STM32_REMAP(0U, 0x1U, 9U, STM32_AFIO_MAPR2)

TIM14 (no remap)

◆ TIM14_REMAP1

#define TIM14_REMAP1   STM32_REMAP(1U, 0x1U, 9U, STM32_AFIO_MAPR2)

TIM14 (remap)

◆ TIM15_REMAP0

#define TIM15_REMAP0   STM32_REMAP(0U, 0x1U, 0U, STM32_AFIO_MAPR2)

TIM15 (no remap)

◆ TIM15_REMAP1

#define TIM15_REMAP1   STM32_REMAP(1U, 0x1U, 0U, STM32_AFIO_MAPR2)

TIM15 (remap)

◆ TIM16_REMAP0

#define TIM16_REMAP0   STM32_REMAP(0U, 0x1U, 1U, STM32_AFIO_MAPR2)

TIM16 (no remap)

◆ TIM16_REMAP1

#define TIM16_REMAP1   STM32_REMAP(1U, 0x1U, 1U, STM32_AFIO_MAPR2)

TIM16 (remap)

◆ TIM17_REMAP0

#define TIM17_REMAP0   STM32_REMAP(0U, 0x1U, 2U, STM32_AFIO_MAPR2)

TIM17 (no remap)

◆ TIM17_REMAP1

#define TIM17_REMAP1   STM32_REMAP(1U, 0x1U, 2U, STM32_AFIO_MAPR2)

TIM17 (remap)

◆ TIM1_REMAP0

#define TIM1_REMAP0   STM32_REMAP(0U, 0x3U, 6U, STM32_AFIO_MAPR)

TIM1 (no remap)

◆ TIM1_REMAP1

#define TIM1_REMAP1   STM32_REMAP(1U, 0x3U, 6U, STM32_AFIO_MAPR)

TIM1 (partial remap)

◆ TIM1_REMAP2

#define TIM1_REMAP2   STM32_REMAP(3U, 0x3U, 6U, STM32_AFIO_MAPR)

TIM1 (full remap)

◆ TIM2_REMAP0

#define TIM2_REMAP0   STM32_REMAP(0U, 0x3U, 8U, STM32_AFIO_MAPR)

TIM2 (no remap)

◆ TIM2_REMAP1

#define TIM2_REMAP1   STM32_REMAP(1U, 0x3U, 8U, STM32_AFIO_MAPR)

TIM2 (partial remap 1)

◆ TIM2_REMAP2

#define TIM2_REMAP2   STM32_REMAP(2U, 0x3U, 8U, STM32_AFIO_MAPR)

TIM2 (partial remap 2)

◆ TIM2_REMAP3

#define TIM2_REMAP3   STM32_REMAP(3U, 0x3U, 8U, STM32_AFIO_MAPR)

TIM2 (full remap)

◆ TIM3_REMAP0

#define TIM3_REMAP0   STM32_REMAP(0U, 0x3U, 10U, STM32_AFIO_MAPR)

TIM3 (no remap)

◆ TIM3_REMAP1

#define TIM3_REMAP1   STM32_REMAP(1U, 0x3U, 10U, STM32_AFIO_MAPR)

TIM3 (partial remap 1)

◆ TIM3_REMAP2

#define TIM3_REMAP2   STM32_REMAP(2U, 0x3U, 10U, STM32_AFIO_MAPR)

TIM3 (partial remap 2)

◆ TIM3_REMAP3

#define TIM3_REMAP3   STM32_REMAP(3U, 0x3U, 10U, STM32_AFIO_MAPR)

TIM3 (full remap)

◆ TIM4_REMAP0

#define TIM4_REMAP0   STM32_REMAP(0U, 0x1U, 12U, STM32_AFIO_MAPR)

TIM4 (no remap)

◆ TIM4_REMAP1

#define TIM4_REMAP1   STM32_REMAP(1U, 0x1U, 12U, STM32_AFIO_MAPR)

TIM4 (remap)

◆ TIM9_REMAP0

#define TIM9_REMAP0   STM32_REMAP(0U, 0x1U, 5U, STM32_AFIO_MAPR2)

TIM9 (no remap)

◆ TIM9_REMAP1

#define TIM9_REMAP1   STM32_REMAP(1U, 0x1U, 5U, STM32_AFIO_MAPR2)

TIM9 (remap)

◆ USART1_REMAP0

#define USART1_REMAP0   STM32_REMAP(0U, 0x1U, 2U, STM32_AFIO_MAPR)

USART1 (no remap)

◆ USART1_REMAP1

#define USART1_REMAP1   STM32_REMAP(1U, 0x1U, 2U, STM32_AFIO_MAPR)

USART1 (remap)

◆ USART2_REMAP0

#define USART2_REMAP0   STM32_REMAP(0U, 0x1U, 3U, STM32_AFIO_MAPR)

USART2 (no remap)

◆ USART2_REMAP1

#define USART2_REMAP1   STM32_REMAP(1U, 0x1U, 3U, STM32_AFIO_MAPR)

USART2 (remap)

◆ USART3_REMAP0

#define USART3_REMAP0   STM32_REMAP(0U, 0x3U, 4U, STM32_AFIO_MAPR)

USART3 (no remap)

◆ USART3_REMAP1

#define USART3_REMAP1   STM32_REMAP(1U, 0x3U, 4U, STM32_AFIO_MAPR)

USART3 (partial remap)

◆ USART3_REMAP2

#define USART3_REMAP2   STM32_REMAP(3U, 0x3U, 4U, STM32_AFIO_MAPR)

USART3 (full remap)