Macros
#define	X86_TIME_STAMP_COUNTER_MSR 0x00000010

#define	X86_SPEC_CTRL_MSR 0x00000048

#define	X86_SPEC_CTRL_MSR_IBRS BIT(0)

#define	X86_SPEC_CTRL_MSR_SSBD BIT(2)

#define	X86_APIC_BASE_MSR 0x0000001b

#define	X86_APIC_BASE_MSR_X2APIC BIT(10)

#define	X86_MTRR_DEF_TYPE_MSR 0x000002ff

#define	X86_MTRR_DEF_TYPE_MSR_ENABLE BIT(11)

#define	X86_X2APIC_BASE_MSR 0x00000800 /* .. thru 0x00000BFF */

#define	X86_EFER_MSR 0xC0000080U

#define	X86_EFER_MSR_SCE BIT(0)

#define	X86_EFER_MSR_LME BIT(8)

#define	X86_EFER_MSR_NXE BIT(11)

#define	X86_STAR_MSR 0xC0000081U

#define	X86_LSTAR_MSR 0xC0000082U

#define	X86_FMASK_MSR 0xC0000084U

#define	X86_FS_BASE 0xC0000100U

#define	X86_GS_BASE 0xC0000101U

#define	X86_KERNEL_GS_BASE 0xC0000102U

Macro Definition Documentation

◆ X86_APIC_BASE_MSR

#define X86_APIC_BASE_MSR 0x0000001b

◆ X86_APIC_BASE_MSR_X2APIC

#define X86_APIC_BASE_MSR_X2APIC BIT(10)

◆ X86_EFER_MSR

#define X86_EFER_MSR 0xC0000080U

◆ X86_EFER_MSR_LME

#define X86_EFER_MSR_LME BIT(8)

◆ X86_EFER_MSR_NXE

#define X86_EFER_MSR_NXE BIT(11)

◆ X86_EFER_MSR_SCE

#define X86_EFER_MSR_SCE BIT(0)

◆ X86_FMASK_MSR

#define X86_FMASK_MSR 0xC0000084U

◆ X86_FS_BASE

#define X86_FS_BASE 0xC0000100U

◆ X86_GS_BASE

#define X86_GS_BASE 0xC0000101U

◆ X86_KERNEL_GS_BASE

#define X86_KERNEL_GS_BASE 0xC0000102U

◆ X86_LSTAR_MSR

#define X86_LSTAR_MSR 0xC0000082U

◆ X86_MTRR_DEF_TYPE_MSR

#define X86_MTRR_DEF_TYPE_MSR 0x000002ff

◆ X86_MTRR_DEF_TYPE_MSR_ENABLE

#define X86_MTRR_DEF_TYPE_MSR_ENABLE BIT(11)

◆ X86_SPEC_CTRL_MSR

#define X86_SPEC_CTRL_MSR 0x00000048

◆ X86_SPEC_CTRL_MSR_IBRS

#define X86_SPEC_CTRL_MSR_IBRS BIT(0)

◆ X86_SPEC_CTRL_MSR_SSBD

#define X86_SPEC_CTRL_MSR_SSBD BIT(2)

◆ X86_STAR_MSR

#define X86_STAR_MSR 0xC0000081U

◆ X86_TIME_STAMP_COUNTER_MSR

#define X86_TIME_STAMP_COUNTER_MSR 0x00000010

◆ X86_X2APIC_BASE_MSR

#define X86_X2APIC_BASE_MSR 0x00000800 /* .. thru 0x00000BFF */

Macros