stm32h7_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_SRC_HSE   (STM32_SRC_LSI + 1)
	Domain clocks.
#define	STM32_SRC_HSI48   (STM32_SRC_HSE + 1)
#define	STM32_SRC_HSI_KER   (STM32_SRC_HSI48 + 1) /* HSI + HSIKERON */
#define	STM32_SRC_CSI_KER   (STM32_SRC_HSI_KER + 1) /* CSI + CSIKERON */
#define	STM32_SRC_PLL1_P   (STM32_SRC_CSI_KER + 1)
	PLL outputs.
#define	STM32_SRC_PLL1_Q   (STM32_SRC_PLL1_P + 1)
#define	STM32_SRC_PLL1_R   (STM32_SRC_PLL1_Q + 1)
#define	STM32_SRC_PLL2_P   (STM32_SRC_PLL1_R + 1)
#define	STM32_SRC_PLL2_Q   (STM32_SRC_PLL2_P + 1)
#define	STM32_SRC_PLL2_R   (STM32_SRC_PLL2_Q + 1)
#define	STM32_SRC_PLL3_P   (STM32_SRC_PLL2_R + 1)
#define	STM32_SRC_PLL3_Q   (STM32_SRC_PLL3_P + 1)
#define	STM32_SRC_PLL3_R   (STM32_SRC_PLL3_Q + 1)
#define	STM32_SRC_CKPER   (STM32_SRC_PLL3_R + 1)
	Clock muxes.
#define	STM32_CLOCK_BUS_AHB3   0x0D4
	Others: Not yet supported.
#define	STM32_CLOCK_BUS_AHB1   0x0D8
#define	STM32_CLOCK_BUS_AHB2   0x0DC
#define	STM32_CLOCK_BUS_AHB4   0x0E0
#define	STM32_CLOCK_BUS_APB3   0x0E4
#define	STM32_CLOCK_BUS_APB1   0x0E8
#define	STM32_CLOCK_BUS_APB1_2   0x0EC
#define	STM32_CLOCK_BUS_APB2   0x0F0
#define	STM32_CLOCK_BUS_APB4   0x0F4
#define	STM32_SRC_PCLK1   STM32_CLOCK_BUS_APB1
	Alias D1/2/3 domains clocks.
#define	STM32_SRC_PCLK2   STM32_CLOCK_BUS_APB2
#define	STM32_SRC_HCLK3   STM32_CLOCK_BUS_AHB3
#define	STM32_SRC_PCLK3   STM32_CLOCK_BUS_APB3
#define	STM32_SRC_PCLK4   STM32_CLOCK_BUS_APB4
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB3
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB4
#define	STM32_CLOCK_REG_MASK   0xFFU
#define	STM32_CLOCK_REG_SHIFT   0U
#define	STM32_CLOCK_SHIFT_MASK   0x1FU
#define	STM32_CLOCK_SHIFT_SHIFT   8U
#define	STM32_CLOCK_MASK_MASK   0x7U
#define	STM32_CLOCK_MASK_SHIFT   13U
#define	STM32_CLOCK_VAL_MASK   0x7U
#define	STM32_CLOCK_VAL_SHIFT   16U
#define	STM32_DOMAIN_CLOCK(val, mask, shift, reg)
	STM32H7 clock configuration bit field.
#define	D1CCIPR_REG   0x4C
	RCC_DxCCIP register offset (RM0399.pdf)
#define	D2CCIP1R_REG   0x50
#define	D2CCIP2R_REG   0x54
#define	D3CCIPR_REG   0x58
#define	BDCR_REG   0x70
	RCC_BDCR register offset.
#define	CFGR_REG   0x10
	RCC_CFGRx register offset.
#define	FMC_SEL(val)
	Device domain clocks selection helpers (RM0399.pdf)
#define	QSPI_SEL(val)
#define	DSI_SEL(val)
#define	SDMMC_SEL(val)
#define	CKPER_SEL(val)
#define	OSPI_SEL(val)
#define	SAI1_SEL(val)
	D2CCIP1R devices.
#define	SAI23_SEL(val)
#define	SPI123_SEL(val)
#define	SPI45_SEL(val)
#define	SPDIF_SEL(val)
#define	DFSDM1_SEL(val)
#define	FDCAN_SEL(val)
#define	SWP_SEL(val)
#define	USART2345678_SEL(val)
	D2CCIP2R devices.
#define	USART16_SEL(val)
#define	RNG_SEL(val)
#define	I2C123_SEL(val)
#define	USB_SEL(val)
#define	CEC_SEL(val)
#define	LPTIM1_SEL(val)
#define	LPUART1_SEL(val)
	D3CCIPR devices.
#define	I2C4_SEL(val)
#define	LPTIM2_SEL(val)
#define	LPTIM345_SEL(val)
#define	ADC_SEL(val)
#define	SAI4A_SEL(val)
#define	SAI4B_SEL(val)
#define	SPI6_SEL(val)
#define	RTC_SEL(val)
	BDCR devices.
#define	MCO1_SEL(val)
	CFGR devices.
#define	MCO1_PRE(val)
#define	MCO2_SEL(val)
#define	MCO2_PRE(val)

Macro Definition Documentation

ADC_SEL

#define ADC_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 16, D3CCIPR_REG)

BDCR_REG

#define BDCR_REG   0x70

RCC_BDCR register offset.

CEC_SEL

#define CEC_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 22, D2CCIP2R_REG)

CFGR_REG

#define CFGR_REG   0x10

RCC_CFGRx register offset.

CKPER_SEL

#define CKPER_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG)

D1CCIPR_REG

#define D1CCIPR_REG   0x4C

RCC_DxCCIP register offset (RM0399.pdf)

D2CCIP1R_REG

#define D2CCIP1R_REG   0x50

D2CCIP2R_REG

#define D2CCIP2R_REG   0x54

D3CCIPR_REG

#define D3CCIPR_REG   0x58

DFSDM1_SEL

#define DFSDM1_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 1, 24, D2CCIP1R_REG)

DSI_SEL

#define DSI_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 1, 8, D1CCIPR_REG)

FDCAN_SEL

#define FDCAN_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 28, D2CCIP1R_REG)

FMC_SEL

#define FMC_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG)

Device domain clocks selection helpers (RM0399.pdf)

D1CCIPR devices

I2C123_SEL

#define I2C123_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 12, D2CCIP2R_REG)

I2C4_SEL

#define I2C4_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 8, D3CCIPR_REG)

LPTIM1_SEL

#define LPTIM1_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 7, 28, D2CCIP2R_REG)

LPTIM2_SEL

#define LPTIM2_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 7, 10, D3CCIPR_REG)

LPTIM345_SEL

#define LPTIM345_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 7, 13, D3CCIPR_REG)

LPUART1_SEL

#define LPUART1_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 7, 0, D3CCIPR_REG)

D3CCIPR devices.

MCO1_PRE

#define MCO1_PRE

(

val

)

Value:

STM32_MCO_CFGR(val, 0x7, 18, CFGR_REG)

MCO1_SEL

#define MCO1_SEL

(

val

)

Value:

STM32_MCO_CFGR(val, 0xF, 22, CFGR_REG)

CFGR devices.

MCO2_PRE

#define MCO2_PRE

(

val

)

Value:

STM32_MCO_CFGR(val, 0x7, 25, CFGR_REG)

MCO2_SEL

#define MCO2_SEL

(

val

)

Value:

STM32_MCO_CFGR(val, 0xF, 29, CFGR_REG)

OSPI_SEL

#define OSPI_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)

QSPI_SEL

#define QSPI_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)

RNG_SEL

#define RNG_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 8, D2CCIP2R_REG)

RTC_SEL

#define RTC_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)

BDCR devices.

SAI1_SEL

#define SAI1_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP1R_REG)

D2CCIP1R devices.

SAI23_SEL

#define SAI23_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 7, 6, D2CCIP1R_REG)

SAI4A_SEL

#define SAI4A_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 7, 21, D3CCIPR_REG)

SAI4B_SEL

#define SAI4B_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 7, 24, D3CCIPR_REG)

SDMMC_SEL

#define SDMMC_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 1, 16, D1CCIPR_REG)

SPDIF_SEL

#define SPDIF_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 20, D2CCIP1R_REG)

SPI123_SEL

#define SPI123_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 7, 12, D2CCIP1R_REG)

SPI45_SEL

#define SPI45_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 7, 16, D2CCIP1R_REG)

SPI6_SEL

#define SPI6_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 7, 28, D3CCIPR_REG)

STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x0D8

STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2   0x0DC

STM32_CLOCK_BUS_AHB3

#define STM32_CLOCK_BUS_AHB3   0x0D4

Others: Not yet supported.

Bus clocks

STM32_CLOCK_BUS_AHB4

#define STM32_CLOCK_BUS_AHB4   0x0E0

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x0E8

STM32_CLOCK_BUS_APB1_2

#define STM32_CLOCK_BUS_APB1_2   0x0EC

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x0F0

STM32_CLOCK_BUS_APB3

#define STM32_CLOCK_BUS_APB3   0x0E4

STM32_CLOCK_BUS_APB4

#define STM32_CLOCK_BUS_APB4   0x0F4

STM32_CLOCK_MASK_MASK

#define STM32_CLOCK_MASK_MASK   0x7U

STM32_CLOCK_MASK_SHIFT

#define STM32_CLOCK_MASK_SHIFT   13U

STM32_CLOCK_REG_MASK

#define STM32_CLOCK_REG_MASK   0xFFU

STM32_CLOCK_REG_SHIFT

#define STM32_CLOCK_REG_SHIFT   0U

STM32_CLOCK_SHIFT_MASK

#define STM32_CLOCK_SHIFT_MASK   0x1FU

STM32_CLOCK_SHIFT_SHIFT

#define STM32_CLOCK_SHIFT_SHIFT   8U

STM32_CLOCK_VAL_MASK

#define STM32_CLOCK_VAL_MASK   0x7U

STM32_CLOCK_VAL_SHIFT

#define STM32_CLOCK_VAL_SHIFT   16U

STM32_DOMAIN_CLOCK

#define STM32_DOMAIN_CLOCK	(		val,
			mask,
			shift,
			reg )

Value:

        ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |    \
         (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |      \
         (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
         (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))

STM32H7 clock configuration bit field.

• reg (0/1) [ 0 : 7 ]
• shift (0..31) [ 8 : 12 ]
• mask (0x1, 0x3, 0x7) [ 13 : 15 ]
• val (0..3) [ 16 : 18 ]

Parameters

reg	RCC_DxCCIP register offset
shift	Position within RCC_DxCCIP.
mask	Mask for the RCC_DxCCIP field.
val	Clock value (0, 1, 2 or 3).

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB4

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB3

STM32_SRC_CKPER

#define STM32_SRC_CKPER   (STM32_SRC_PLL3_R + 1)

Clock muxes.

STM32_SRC_CSI_KER

#define STM32_SRC_CSI_KER   (STM32_SRC_HSI_KER + 1) /* CSI + CSIKERON */

STM32_SRC_HCLK3

#define STM32_SRC_HCLK3   STM32_CLOCK_BUS_AHB3

STM32_SRC_HSE

#define STM32_SRC_HSE   (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

STM32_SRC_HSI48

#define STM32_SRC_HSI48   (STM32_SRC_HSE + 1)

STM32_SRC_HSI_KER

#define STM32_SRC_HSI_KER   (STM32_SRC_HSI48 + 1) /* HSI + HSIKERON */

STM32_SRC_PCLK1

#define STM32_SRC_PCLK1   STM32_CLOCK_BUS_APB1

Alias D1/2/3 domains clocks.

STM32_SRC_PCLK2

#define STM32_SRC_PCLK2   STM32_CLOCK_BUS_APB2

STM32_SRC_PCLK3

#define STM32_SRC_PCLK3   STM32_CLOCK_BUS_APB3

STM32_SRC_PCLK4

#define STM32_SRC_PCLK4   STM32_CLOCK_BUS_APB4

STM32_SRC_PLL1_P

#define STM32_SRC_PLL1_P   (STM32_SRC_CSI_KER + 1)

PLL outputs.

STM32_SRC_PLL1_Q

#define STM32_SRC_PLL1_Q   (STM32_SRC_PLL1_P + 1)

STM32_SRC_PLL1_R

#define STM32_SRC_PLL1_R   (STM32_SRC_PLL1_Q + 1)

STM32_SRC_PLL2_P

#define STM32_SRC_PLL2_P   (STM32_SRC_PLL1_R + 1)

STM32_SRC_PLL2_Q

#define STM32_SRC_PLL2_Q   (STM32_SRC_PLL2_P + 1)

STM32_SRC_PLL2_R

#define STM32_SRC_PLL2_R   (STM32_SRC_PLL2_Q + 1)

STM32_SRC_PLL3_P

#define STM32_SRC_PLL3_P   (STM32_SRC_PLL2_R + 1)

STM32_SRC_PLL3_Q

#define STM32_SRC_PLL3_Q   (STM32_SRC_PLL3_P + 1)

STM32_SRC_PLL3_R

#define STM32_SRC_PLL3_R   (STM32_SRC_PLL3_Q + 1)

SWP_SEL

#define SWP_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 1, 31, D2CCIP1R_REG)

USART16_SEL

#define USART16_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 7, 3, D2CCIP2R_REG)

USART2345678_SEL

#define USART2345678_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP2R_REG)

D2CCIP2R devices.

USB_SEL

#define USB_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 20, D2CCIP2R_REG)