Zephyr API Documentation 3.7.99
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
aux_regs.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2014 Wind River Systems, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
15#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_AUX_REGS_H_
16#define ZEPHYR_INCLUDE_ARCH_ARC_V2_AUX_REGS_H_
17
19
20#define _ARC_V2_LP_START 0x002
21#define _ARC_V2_LP_END 0x003
22#define _ARC_V2_IDENTITY 0x004
23#define _ARC_V2_SEC_STAT 0x09
24#define _ARC_V2_STATUS32 0x00a
25#define _ARC_V2_STATUS32_P0 0x00b
26#define _ARC_V2_USER_SP 0x00d
27#define _ARC_V2_AUX_IRQ_CTRL 0x00e
28#define _ARC_V2_IC_IVIC 0x010
29#define _ARC_V2_IC_CTRL 0x011
30#define _ARC_V2_IC_LIL 0x013
31#define _ARC_V2_IC_IVIL 0x019
32#define _ARC_V2_IC_DATA 0x01d
33#define _ARC_V2_TMR0_COUNT 0x021
34#define _ARC_V2_TMR0_CONTROL 0x022
35#define _ARC_V2_TMR0_LIMIT 0x023
36#define _ARC_V2_IRQ_VECT_BASE 0x025
37#define _ARC_V2_IRQ_VECT_BASE_S 0x26
38#define _ARC_V2_KERNEL_SP 0x38
39#define _ARC_V2_SEC_U_SP 0x39
40#define _ARC_V2_SEC_K_SP 0x3a
41#define _ARC_V2_AUX_IRQ_ACT 0x043
42#define _ARC_V2_DC_IVDC 0x047
43#define _ARC_V2_DC_CTRL 0x048
44#define _ARC_V2_DC_LDL 0x049
45#define _ARC_V2_DC_IVDL 0x04a
46#define _ARC_V2_DC_FLSH 0x04b
47#define _ARC_V2_DC_FLDL 0x04c
48#define _ARC_V2_EA_BUILD 0x065
49#define _ARC_V2_VECBASE_AC_BUILD 0x068
50#define _ARC_V2_FP_BUILD 0x06b
51#define _ARC_V2_DPFP_BUILD 0x06c
52#define _ARC_V2_MPU_BUILD 0x06d
53#define _ARC_V2_RF_BUILD 0x06e
54#define _ARC_V2_MMU_BUILD 0x06f
55#define _ARC_V2_VECBASE_BUILD 0x071
56#define _ARC_V2_D_CACHE_BUILD 0x072
57#define _ARC_V2_DCCM_BUILD 0x074
58#define _ARC_V2_TIMER_BUILD 0x075
59#define _ARC_V2_AP_BUILD 0x076
60#define _ARC_V2_I_CACHE_BUILD 0x077
61#define _ARC_V2_ICCM_BUILD 0x078
62#define _ARC_V2_MULTIPLY_BUILD 0x07b
63#define _ARC_V2_SWAP_BUILD 0x07c
64#define _ARC_V2_NORM_BUILD 0x07d
65#define _ARC_V2_MINMAX_BUILD 0x07e
66#define _ARC_V2_BARREL_BUILD 0x07f
67#define _ARC_V2_ISA_CONFIG 0x0c1
68#define _ARC_V2_SEP_BUILD 0x0c7
69#define _ARC_V2_LPB_BUILD 0x0e9
70#define _ARC_V2_LPB_CTRL 0x488
71#define _ARC_V2_IRQ_BUILD 0x0f3
72#define _ARC_V2_PCT_BUILD 0x0f5
73#define _ARC_V2_CC_BUILD 0x0f6
74#define _ARC_V2_TMR1_COUNT 0x100
75#define _ARC_V2_TMR1_CONTROL 0x101
76#define _ARC_V2_TMR1_LIMIT 0x102
77#define _ARC_V2_S_TMR0_COUNT 0x106
78#define _ARC_V2_S_TMR0_CONTROL 0x107
79#define _ARC_V2_S_TMR0_LIMIT 0x108
80#define _ARC_V2_S_TMR1_COUNT 0x109
81#define _ARC_V2_S_TMR1_CONTROL 0x10a
82#define _ARC_V2_S_TMR1_LIMIT 0x10b
83#define _ARC_V2_IRQ_PRIO_PEND 0x200
84#define _ARC_V2_AUX_IRQ_HINT 0x201
85#define _ARC_V2_IRQ_PRIORITY 0x206
86#define _ARC_V2_USTACK_TOP 0x260
87#define _ARC_V2_USTACK_BASE 0x261
88#define _ARC_V2_S_USTACK_TOP 0x262
89#define _ARC_V2_S_USTACK_BASE 0x263
90#define _ARC_V2_KSTACK_TOP 0x264
91#define _ARC_V2_KSTACK_BASE 0x265
92#define _ARC_V2_S_KSTACK_TOP 0x266
93#define _ARC_V2_S_KSTACK_BASE 0x267
94#define _ARC_V2_NSC_TABLE_TOP 0x268
95#define _ARC_V2_NSC_TABLE_BASE 0x269
96#define _ARC_V2_JLI_BASE 0x290
97#define _ARC_V2_LDI_BASE 0x291
98#define _ARC_V2_EI_BASE 0x292
99#define _ARC_V2_ERET 0x400
100#define _ARC_V2_ERSTATUS 0x402
101#define _ARC_V2_ECR 0x403
102#define _ARC_V2_EFA 0x404
103#define _ARC_V2_ERSEC_STAT 0x406
104#define _ARC_V2_ICAUSE 0x40a
105#define _ARC_V2_IRQ_SELECT 0x40b
106#define _ARC_V2_IRQ_ENABLE 0x40c
107#define _ARC_V2_IRQ_TRIGGER 0x40d
108#define _ARC_V2_IRQ_STATUS 0x40f
109#define _ARC_V2_IRQ_PULSE_CANCEL 0x415
110#define _ARC_V2_IRQ_PENDING 0x416
111#define _ARC_V2_FPU_CTRL 0x300
112#define _ARC_V2_FPU_STATUS 0x301
113#define _ARC_V2_FPU_DPFP1L 0x302
114#define _ARC_V2_FPU_DPFP1H 0x303
115#define _ARC_V2_FPU_DPFP2L 0x304
116#define _ARC_V2_FPU_DPFP2H 0x305
117#define _ARC_V2_MPU_EN 0x409
118#define _ARC_V2_MPU_RDB0 0x422
119#define _ARC_V2_MPU_RDP0 0x423
120#define _ARC_V2_MPU_INDEX 0x448
121#define _ARC_V2_MPU_RSTART 0x449
122#define _ARC_V2_MPU_REND 0x44A
123#define _ARC_V2_MPU_RPER 0x44B
124#define _ARC_V2_MPU_PROBE 0x44C
125#define _ARC_V2_ACC0_GHI 0x583
126#define _ARC_V2_ACC0_HI 0x582
127#define _ARC_V2_ACC0_GLO 0x581
128#define _ARC_V2_ACC0_LO 0x580
129#define _ARC_V2_DSP_BUILD 0x7A
130#define _ARC_V2_DSP_CTRL 0x59f
131#define _ARC_V2_DSP_BFLY0 0x598
132#define _ARC_V2_DSP_FFT_CTRL 0x59e
133#define _ARC_V2_AGU_BUILD 0xcc
134#define _ARC_V2_AGU_AP0 0x5c0
135#define _ARC_V2_AGU_AP1 0x5c1
136#define _ARC_V2_AGU_AP2 0x5c2
137#define _ARC_V2_AGU_AP3 0x5c3
138#define _ARC_V2_AGU_AP4 0x5c4
139#define _ARC_V2_AGU_AP5 0x5c5
140#define _ARC_V2_AGU_AP6 0x5c6
141#define _ARC_V2_AGU_AP7 0x5c7
142#define _ARC_V2_AGU_AP8 0x5c8
143#define _ARC_V2_AGU_AP9 0x5c9
144#define _ARC_V2_AGU_AP10 0x5ca
145#define _ARC_V2_AGU_AP11 0x5cb
146#define _ARC_V2_AGU_OS0 0x5d0
147#define _ARC_V2_AGU_OS1 0x5d1
148#define _ARC_V2_AGU_OS2 0x5d2
149#define _ARC_V2_AGU_OS3 0x5d3
150#define _ARC_V2_AGU_OS4 0x5d4
151#define _ARC_V2_AGU_OS5 0x5d5
152#define _ARC_V2_AGU_OS6 0x5d6
153#define _ARC_V2_AGU_OS7 0x5d7
154#define _ARC_V2_AGU_MOD0 0x5e0
155#define _ARC_V2_AGU_MOD1 0x5e1
156#define _ARC_V2_AGU_MOD2 0x5e2
157#define _ARC_V2_AGU_MOD3 0x5e3
158#define _ARC_V2_AGU_MOD4 0x5e4
159#define _ARC_V2_AGU_MOD5 0x5e5
160#define _ARC_V2_AGU_MOD6 0x5e6
161#define _ARC_V2_AGU_MOD7 0x5e7
162#define _ARC_V2_AGU_MOD8 0x5e8
163#define _ARC_V2_AGU_MOD9 0x5e9
164#define _ARC_V2_AGU_MOD10 0x5ea
165#define _ARC_V2_AGU_MOD11 0x5eb
166#define _ARC_V2_AGU_MOD12 0x5ec
167#define _ARC_V2_AGU_MOD13 0x5ed
168#define _ARC_V2_AGU_MOD14 0x5ee
169#define _ARC_V2_AGU_MOD15 0x5ef
170#define _ARC_V2_AGU_MOD16 0x5f0
171#define _ARC_V2_AGU_MOD17 0x5f1
172#define _ARC_V2_AGU_MOD18 0x5f2
173#define _ARC_V2_AGU_MOD19 0x5f3
174#define _ARC_V2_AGU_MOD20 0x5f4
175#define _ARC_V2_AGU_MOD21 0x5f5
176#define _ARC_V2_AGU_MOD22 0x5f6
177#define _ARC_V2_AGU_MOD23 0x5f7
178#define _ARC_HW_PF_BUILD 0xf70
179#define _ARC_HW_PF_CTRL 0x4f
180
181/* _ARC_HW_PF_CTRL bits */
182#define _ARC_HW_PF_CTRL_ENABLE BIT(0)
183
184/* STATUS32/STATUS32_P0 bits */
185#define _ARC_V2_STATUS32_H (1 << 0)
186#define Z_ARC_V2_STATUS32_E(x) ((x) << 1)
187#define _ARC_V2_STATUS32_AE_BIT 5
188#define _ARC_V2_STATUS32_AE (1 << _ARC_V2_STATUS32_AE_BIT)
189#define _ARC_V2_STATUS32_DE (1 << 6)
190#define _ARC_V2_STATUS32_U_BIT 7
191#define _ARC_V2_STATUS32_U (1 << _ARC_V2_STATUS32_U_BIT)
192#define _ARC_V2_STATUS32_V (1 << 8)
193#define _ARC_V2_STATUS32_C (1 << 9)
194#define _ARC_V2_STATUS32_N (1 << 10)
195#define _ARC_V2_STATUS32_Z (1 << 11)
196#define _ARC_V2_STATUS32_L (1 << 12)
197#define _ARC_V2_STATUS32_DZ_BIT 13
198#define _ARC_V2_STATUS32_DZ (1 << _ARC_V2_STATUS32_DZ_BIT)
199#define _ARC_V2_STATUS32_SC_BIT 14
200#define _ARC_V2_STATUS32_SC (1 << _ARC_V2_STATUS32_SC_BIT)
201#define _ARC_V2_STATUS32_ES (1 << 15)
202#define _ARC_V2_STATUS32_RB(x) ((x) << 16)
203#define _ARC_V2_STATUS32_AD_BIT 19
204#define _ARC_V2_STATUS32_AD (1 << _ARC_V2_STATUS32_AD_BIT)
205#define _ARC_V2_STATUS32_US_BIT 20
206#define _ARC_V2_STATUS32_US (1 << _ARC_V2_STATUS32_US_BIT)
207#define _ARC_V2_STATUS32_S_BIT 21
208#define _ARC_V2_STATUS32_S (1 << _ARC_V2_STATUS32_US_BIT)
209#define _ARC_V2_STATUS32_IE (1 << 31)
210
211/* SEC_STAT bits */
212#define _ARC_V2_SEC_STAT_SSC_BIT 0
213#define _ARC_V2_SEC_STAT_SSC (1 << _ARC_V2_SEC_STAT_SSC_BIT)
214#define _ARC_V2_SEC_STAT_NSRT_BIT 1
215#define _ARC_V2_SEC_STAT_NSRT (1 << _ARC_V2_SEC_STAT_NSRT_BIT)
216#define _ARC_V2_SEC_STAT_NSRU_BIT 2
217#define _ARC_V2_SEC_STAT_NSRU (1 << _ARC_V2_SEC_STAT_NSRU_BIT)
218#define _ARC_V2_SEC_STAT_IRM_BIT 3
219#define _ARC_V2_SEC_STAT_IRM (1 << _ARC_V2_SEC_STAT_IRM_BIT)
220#define _ARC_V2_SEC_STAT_SUE_BIT 4
221#define _ARC_V2_SEC_STAT_SUE (1 << _ARC_V2_SEC_STAT_SUE_BIT)
222#define _ARC_V2_SEC_STAT_NIC_BIT 5
223#define _ARC_V2_SEC_STAT_NIC (1 << _ARC_V2_SEC_STAT_NIC_BIT)
224
225/* interrupt related bits */
226#define _ARC_V2_IRQ_PRIORITY_SECURE 0x100
227
228/* exception cause register masks */
229#define Z_ARC_V2_ECR_VECTOR(X) ((X & 0xff0000) >> 16)
230#define Z_ARC_V2_ECR_CODE(X) ((X & 0xff00) >> 8)
231#define Z_ARC_V2_ECR_PARAMETER(X) (X & 0xff)
232
233#ifndef _ASMLANGUAGE
234
235#include <zephyr/types.h>
236#if defined(__CCAC__)
237
238#define z_arc_v2_aux_reg_read(reg) _lr((volatile uint32_t)reg)
239#define z_arc_v2_aux_reg_write(reg, val) \
240 _sr((unsigned int)val, (volatile uint32_t)reg)
241
242#else /* ! __CCAC__ */
243
244#define z_arc_v2_aux_reg_read(reg) __builtin_arc_lr((volatile uint32_t)reg)
245#define z_arc_v2_aux_reg_write(reg, val) \
246 __builtin_arc_sr((unsigned int)val, (volatile uint32_t)reg)
247
248#endif /* __CCAC__ */
249#endif /* _ASMLANGUAGE */
250
251#define z_arc_v2_core_id() \
252 ({ \
253 unsigned int __ret; \
254 __asm__ __volatile__("lr %0, [%1]\n" \
255 "xbfu %0, %0, 0xe8\n" \
256 : "=r"(__ret) \
257 : "i"(_ARC_V2_IDENTITY)); \
258 __ret; \
259 })
260
261#endif /* ZEPHYR_INCLUDE_ARCH_ARC_V2_AUX_REGS_H_ */
Macro utilities.