ch32v003-dma.h File Reference

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Macros
#define	CH32V003_ADC1_DMA   0
#define	CH32V003_SPI1_RX_DMA   1
#define	CH32V003_SPI1_TX_DMA   2
#define	CH32V003_USART1_RX_DMA   4
#define	CH32V003_USART1_TX_DMA   3
#define	CH32V003_I2C1_RX_DMA   6
#define	CH32V003_I2C1_TX_DMA   5
#define	CH32V003_TIM1_CH1_DMA   1
#define	CH32V003_TIM1_CH2_DMA   2
#define	CH32V003_TIM1_CH3_DMA   5
#define	CH32V003_TIM1_CH4_DMA   3
#define	CH32V003_TIM1_TRIG   3
#define	CH32V003_TIM1_COM   3
#define	CH32V003_TIM1_UP   4
#define	CH32V003_TIM2_CH1_DMA   4
#define	CH32V003_TIM2_CH2_DMA   6
#define	CH32V003_TIM2_CH3_DMA   0
#define	CH32V003_TIM2_CH4_DMA   6
#define	CH32V003_TIM2_UP   1

Macro Definition Documentation

CH32V003_ADC1_DMA

#define CH32V003_ADC1_DMA   0

CH32V003_I2C1_RX_DMA

#define CH32V003_I2C1_RX_DMA   6

CH32V003_I2C1_TX_DMA

#define CH32V003_I2C1_TX_DMA   5

CH32V003_SPI1_RX_DMA

#define CH32V003_SPI1_RX_DMA   1

CH32V003_SPI1_TX_DMA

#define CH32V003_SPI1_TX_DMA   2

CH32V003_TIM1_CH1_DMA

#define CH32V003_TIM1_CH1_DMA   1

CH32V003_TIM1_CH2_DMA

#define CH32V003_TIM1_CH2_DMA   2

CH32V003_TIM1_CH3_DMA

#define CH32V003_TIM1_CH3_DMA   5

CH32V003_TIM1_CH4_DMA

#define CH32V003_TIM1_CH4_DMA   3

CH32V003_TIM1_COM

#define CH32V003_TIM1_COM   3

CH32V003_TIM1_TRIG

#define CH32V003_TIM1_TRIG   3

CH32V003_TIM1_UP

#define CH32V003_TIM1_UP   4

CH32V003_TIM2_CH1_DMA

#define CH32V003_TIM2_CH1_DMA   4

CH32V003_TIM2_CH2_DMA

#define CH32V003_TIM2_CH2_DMA   6

CH32V003_TIM2_CH3_DMA

#define CH32V003_TIM2_CH3_DMA   0

CH32V003_TIM2_CH4_DMA

#define CH32V003_TIM2_CH4_DMA   6

CH32V003_TIM2_UP

#define CH32V003_TIM2_UP   1

CH32V003_USART1_RX_DMA

#define CH32V003_USART1_RX_DMA   4

CH32V003_USART1_TX_DMA

#define CH32V003_USART1_TX_DMA   3