gd32e50x-clocks.h File Reference

#include "gd32-clocks-common.h"

Go to the source code of this file.

Macros
Register offsets
#define	GD32_AHBEN_OFFSET   0x14U
#define	GD32_APB1EN_OFFSET   0x1CU
#define	GD32_APB2EN_OFFSET   0x18U
#define	GD32_ADDAPB1EN_OFFSET   0xE4U
Clock enable/disable definitions for peripherals
#define	GD32_CLOCK_DMA0   GD32_CLOCK_CONFIG(AHBEN, 0U)
#define	GD32_CLOCK_DMA1   GD32_CLOCK_CONFIG(AHBEN, 1U)
#define	GD32_CLOCK_SRAMSP   GD32_CLOCK_CONFIG(AHBEN, 2U)
#define	GD32_CLOCK_FMCSP   GD32_CLOCK_CONFIG(AHBEN, 4U)
#define	GD32_CLOCK_CRC   GD32_CLOCK_CONFIG(AHBEN, 6U)
#define	GD32_CLOCK_EXMC   GD32_CLOCK_CONFIG(AHBEN, 8U)
#define	GD32_CLOCK_USBHS   GD32_CLOCK_CONFIG(AHBEN, 12U)
#define	GD32_CLOCK_ULPI   GD32_CLOCK_CONFIG(AHBEN, 13U)
#define	GD32_CLOCK_ENET   GD32_CLOCK_CONFIG(AHBEN, 14U)
#define	GD32_CLOCK_ENETTX   GD32_CLOCK_CONFIG(AHBEN, 15U)
#define	GD32_CLOCK_ENETRX   GD32_CLOCK_CONFIG(AHBEN, 16U)
#define	GD32_CLOCK_TMU   GD32_CLOCK_CONFIG(AHBEN, 30U)
#define	GD32_CLOCK_SQPI   GD32_CLOCK_CONFIG(AHBEN, 31U)
#define	GD32_CLOCK_TIMER1   GD32_CLOCK_CONFIG(APB1EN, 0U)
#define	GD32_CLOCK_TIMER2   GD32_CLOCK_CONFIG(APB1EN, 1U)
#define	GD32_CLOCK_TIMER3   GD32_CLOCK_CONFIG(APB1EN, 2U)
#define	GD32_CLOCK_TIMER4   GD32_CLOCK_CONFIG(APB1EN, 3U)
#define	GD32_CLOCK_TIMER5   GD32_CLOCK_CONFIG(APB1EN, 4U)
#define	GD32_CLOCK_TIMER6   GD32_CLOCK_CONFIG(APB1EN, 5U)
#define	GD32_CLOCK_TIMER11   GD32_CLOCK_CONFIG(APB1EN, 6U)
#define	GD32_CLOCK_TIMER12   GD32_CLOCK_CONFIG(APB1EN, 7U)
#define	GD32_CLOCK_TIMER13   GD32_CLOCK_CONFIG(APB1EN, 8U)
#define	GD32_CLOCK_WWDGT   GD32_CLOCK_CONFIG(APB1EN, 11U)
#define	GD32_CLOCK_SPI1   GD32_CLOCK_CONFIG(APB1EN, 14U)
#define	GD32_CLOCK_SPI2   GD32_CLOCK_CONFIG(APB1EN, 15U)
#define	GD32_CLOCK_USART1   GD32_CLOCK_CONFIG(APB1EN, 17U)
#define	GD32_CLOCK_USART2   GD32_CLOCK_CONFIG(APB1EN, 18U)
#define	GD32_CLOCK_UART3   GD32_CLOCK_CONFIG(APB1EN, 19U)
#define	GD32_CLOCK_UART4   GD32_CLOCK_CONFIG(APB1EN, 20U)
#define	GD32_CLOCK_I2C0   GD32_CLOCK_CONFIG(APB1EN, 21U)
#define	GD32_CLOCK_I2C1   GD32_CLOCK_CONFIG(APB1EN, 22U)
#define	GD32_CLOCK_I2C2   GD32_CLOCK_CONFIG(APB1EN, 24U)
#define	GD32_CLOCK_CAN0   GD32_CLOCK_CONFIG(APB1EN, 25U)
#define	GD32_CLOCK_CAN1   GD32_CLOCK_CONFIG(APB1EN, 26U)
#define	GD32_CLOCK_BKPI   GD32_CLOCK_CONFIG(APB1EN, 27U)
#define	GD32_CLOCK_PMU   GD32_CLOCK_CONFIG(APB1EN, 28U)
#define	GD32_CLOCK_DAC   GD32_CLOCK_CONFIG(APB1EN, 29U)
#define	GD32_CLOCK_AFIO   GD32_CLOCK_CONFIG(APB2EN, 0U)
#define	GD32_CLOCK_GPIOA   GD32_CLOCK_CONFIG(APB2EN, 2U)
#define	GD32_CLOCK_GPIOB   GD32_CLOCK_CONFIG(APB2EN, 3U)
#define	GD32_CLOCK_GPIOC   GD32_CLOCK_CONFIG(APB2EN, 4U)
#define	GD32_CLOCK_GPIOD   GD32_CLOCK_CONFIG(APB2EN, 5U)
#define	GD32_CLOCK_GPIOE   GD32_CLOCK_CONFIG(APB2EN, 6U)
#define	GD32_CLOCK_GPIOF   GD32_CLOCK_CONFIG(APB2EN, 7U)
#define	GD32_CLOCK_GPIOG   GD32_CLOCK_CONFIG(APB2EN, 8U)
#define	GD32_CLOCK_ADC0   GD32_CLOCK_CONFIG(APB2EN, 9U)
#define	GD32_CLOCK_ADC1   GD32_CLOCK_CONFIG(APB2EN, 10U)
#define	GD32_CLOCK_TIMER0   GD32_CLOCK_CONFIG(APB2EN, 11U)
#define	GD32_CLOCK_SPI0   GD32_CLOCK_CONFIG(APB2EN, 12U)
#define	GD32_CLOCK_TIMER7   GD32_CLOCK_CONFIG(APB2EN, 13U)
#define	GD32_CLOCK_USART0   GD32_CLOCK_CONFIG(APB2EN, 14U)
#define	GD32_CLOCK_ADC2   GD32_CLOCK_CONFIG(APB2EN, 15U)
#define	GD32_CLOCK_TIMER8   GD32_CLOCK_CONFIG(APB2EN, 19U)
#define	GD32_CLOCK_TIMER9   GD32_CLOCK_CONFIG(APB2EN, 20U)
#define	GD32_CLOCK_TIMER10   GD32_CLOCK_CONFIG(APB2EN, 21U)
#define	GD32_CLOCK_USART5   GD32_CLOCK_CONFIG(APB2EN, 28U)
#define	GD32_CLOCK_SHRTIMER   GD32_CLOCK_CONFIG(APB2EN, 29U)
#define	GD32_CLOCK_CMP   GD32_CLOCK_CONFIG(APB2EN, 31U)
#define	GD32_CLOCK_CTC   GD32_CLOCK_CONFIG(ADDAPB1EN, 27U)
#define	GD32_CLOCK_CAN2   GD32_CLOCK_CONFIG(ADDAPB1EN, 31U)

Macro Definition Documentation

GD32_ADDAPB1EN_OFFSET

#define GD32_ADDAPB1EN_OFFSET   0xE4U

GD32_AHBEN_OFFSET

#define GD32_AHBEN_OFFSET   0x14U

GD32_APB1EN_OFFSET

#define GD32_APB1EN_OFFSET   0x1CU

GD32_APB2EN_OFFSET

#define GD32_APB2EN_OFFSET   0x18U

GD32_CLOCK_ADC0

#define GD32_CLOCK_ADC0   GD32_CLOCK_CONFIG(APB2EN, 9U)

GD32_CLOCK_ADC1

#define GD32_CLOCK_ADC1   GD32_CLOCK_CONFIG(APB2EN, 10U)

GD32_CLOCK_ADC2

#define GD32_CLOCK_ADC2   GD32_CLOCK_CONFIG(APB2EN, 15U)

GD32_CLOCK_AFIO

#define GD32_CLOCK_AFIO   GD32_CLOCK_CONFIG(APB2EN, 0U)

GD32_CLOCK_BKPI

#define GD32_CLOCK_BKPI   GD32_CLOCK_CONFIG(APB1EN, 27U)

GD32_CLOCK_CAN0

#define GD32_CLOCK_CAN0   GD32_CLOCK_CONFIG(APB1EN, 25U)

GD32_CLOCK_CAN1

#define GD32_CLOCK_CAN1   GD32_CLOCK_CONFIG(APB1EN, 26U)

GD32_CLOCK_CAN2

#define GD32_CLOCK_CAN2   GD32_CLOCK_CONFIG(ADDAPB1EN, 31U)

GD32_CLOCK_CMP

#define GD32_CLOCK_CMP   GD32_CLOCK_CONFIG(APB2EN, 31U)

GD32_CLOCK_CRC

#define GD32_CLOCK_CRC   GD32_CLOCK_CONFIG(AHBEN, 6U)

GD32_CLOCK_CTC

#define GD32_CLOCK_CTC   GD32_CLOCK_CONFIG(ADDAPB1EN, 27U)

GD32_CLOCK_DAC

#define GD32_CLOCK_DAC   GD32_CLOCK_CONFIG(APB1EN, 29U)

GD32_CLOCK_DMA0

#define GD32_CLOCK_DMA0   GD32_CLOCK_CONFIG(AHBEN, 0U)

GD32_CLOCK_DMA1

#define GD32_CLOCK_DMA1   GD32_CLOCK_CONFIG(AHBEN, 1U)

GD32_CLOCK_ENET

#define GD32_CLOCK_ENET   GD32_CLOCK_CONFIG(AHBEN, 14U)

GD32_CLOCK_ENETRX

#define GD32_CLOCK_ENETRX   GD32_CLOCK_CONFIG(AHBEN, 16U)

GD32_CLOCK_ENETTX

#define GD32_CLOCK_ENETTX   GD32_CLOCK_CONFIG(AHBEN, 15U)

GD32_CLOCK_EXMC

#define GD32_CLOCK_EXMC   GD32_CLOCK_CONFIG(AHBEN, 8U)

GD32_CLOCK_FMCSP

#define GD32_CLOCK_FMCSP   GD32_CLOCK_CONFIG(AHBEN, 4U)

GD32_CLOCK_GPIOA

#define GD32_CLOCK_GPIOA   GD32_CLOCK_CONFIG(APB2EN, 2U)

GD32_CLOCK_GPIOB

#define GD32_CLOCK_GPIOB   GD32_CLOCK_CONFIG(APB2EN, 3U)

GD32_CLOCK_GPIOC

#define GD32_CLOCK_GPIOC   GD32_CLOCK_CONFIG(APB2EN, 4U)

GD32_CLOCK_GPIOD

#define GD32_CLOCK_GPIOD   GD32_CLOCK_CONFIG(APB2EN, 5U)

GD32_CLOCK_GPIOE

#define GD32_CLOCK_GPIOE   GD32_CLOCK_CONFIG(APB2EN, 6U)

GD32_CLOCK_GPIOF

#define GD32_CLOCK_GPIOF   GD32_CLOCK_CONFIG(APB2EN, 7U)

GD32_CLOCK_GPIOG

#define GD32_CLOCK_GPIOG   GD32_CLOCK_CONFIG(APB2EN, 8U)

GD32_CLOCK_I2C0

#define GD32_CLOCK_I2C0   GD32_CLOCK_CONFIG(APB1EN, 21U)

GD32_CLOCK_I2C1

#define GD32_CLOCK_I2C1   GD32_CLOCK_CONFIG(APB1EN, 22U)

GD32_CLOCK_I2C2

#define GD32_CLOCK_I2C2   GD32_CLOCK_CONFIG(APB1EN, 24U)

GD32_CLOCK_PMU

#define GD32_CLOCK_PMU   GD32_CLOCK_CONFIG(APB1EN, 28U)

GD32_CLOCK_SHRTIMER

#define GD32_CLOCK_SHRTIMER   GD32_CLOCK_CONFIG(APB2EN, 29U)

GD32_CLOCK_SPI0

#define GD32_CLOCK_SPI0   GD32_CLOCK_CONFIG(APB2EN, 12U)

GD32_CLOCK_SPI1

#define GD32_CLOCK_SPI1   GD32_CLOCK_CONFIG(APB1EN, 14U)

GD32_CLOCK_SPI2

#define GD32_CLOCK_SPI2   GD32_CLOCK_CONFIG(APB1EN, 15U)

GD32_CLOCK_SQPI

#define GD32_CLOCK_SQPI   GD32_CLOCK_CONFIG(AHBEN, 31U)

GD32_CLOCK_SRAMSP

#define GD32_CLOCK_SRAMSP   GD32_CLOCK_CONFIG(AHBEN, 2U)

GD32_CLOCK_TIMER0

#define GD32_CLOCK_TIMER0   GD32_CLOCK_CONFIG(APB2EN, 11U)

GD32_CLOCK_TIMER1

#define GD32_CLOCK_TIMER1   GD32_CLOCK_CONFIG(APB1EN, 0U)

GD32_CLOCK_TIMER10

#define GD32_CLOCK_TIMER10   GD32_CLOCK_CONFIG(APB2EN, 21U)

GD32_CLOCK_TIMER11

#define GD32_CLOCK_TIMER11   GD32_CLOCK_CONFIG(APB1EN, 6U)

GD32_CLOCK_TIMER12

#define GD32_CLOCK_TIMER12   GD32_CLOCK_CONFIG(APB1EN, 7U)

GD32_CLOCK_TIMER13

#define GD32_CLOCK_TIMER13   GD32_CLOCK_CONFIG(APB1EN, 8U)

GD32_CLOCK_TIMER2

#define GD32_CLOCK_TIMER2   GD32_CLOCK_CONFIG(APB1EN, 1U)

GD32_CLOCK_TIMER3

#define GD32_CLOCK_TIMER3   GD32_CLOCK_CONFIG(APB1EN, 2U)

GD32_CLOCK_TIMER4

#define GD32_CLOCK_TIMER4   GD32_CLOCK_CONFIG(APB1EN, 3U)

GD32_CLOCK_TIMER5

#define GD32_CLOCK_TIMER5   GD32_CLOCK_CONFIG(APB1EN, 4U)

GD32_CLOCK_TIMER6

#define GD32_CLOCK_TIMER6   GD32_CLOCK_CONFIG(APB1EN, 5U)

GD32_CLOCK_TIMER7

#define GD32_CLOCK_TIMER7   GD32_CLOCK_CONFIG(APB2EN, 13U)

GD32_CLOCK_TIMER8

#define GD32_CLOCK_TIMER8   GD32_CLOCK_CONFIG(APB2EN, 19U)

GD32_CLOCK_TIMER9

#define GD32_CLOCK_TIMER9   GD32_CLOCK_CONFIG(APB2EN, 20U)

GD32_CLOCK_TMU

#define GD32_CLOCK_TMU   GD32_CLOCK_CONFIG(AHBEN, 30U)

GD32_CLOCK_UART3

#define GD32_CLOCK_UART3   GD32_CLOCK_CONFIG(APB1EN, 19U)

GD32_CLOCK_UART4

#define GD32_CLOCK_UART4   GD32_CLOCK_CONFIG(APB1EN, 20U)

GD32_CLOCK_ULPI

#define GD32_CLOCK_ULPI   GD32_CLOCK_CONFIG(AHBEN, 13U)

GD32_CLOCK_USART0

#define GD32_CLOCK_USART0   GD32_CLOCK_CONFIG(APB2EN, 14U)

GD32_CLOCK_USART1

#define GD32_CLOCK_USART1   GD32_CLOCK_CONFIG(APB1EN, 17U)

GD32_CLOCK_USART2

#define GD32_CLOCK_USART2   GD32_CLOCK_CONFIG(APB1EN, 18U)

GD32_CLOCK_USART5

#define GD32_CLOCK_USART5   GD32_CLOCK_CONFIG(APB2EN, 28U)

GD32_CLOCK_USBHS

#define GD32_CLOCK_USBHS   GD32_CLOCK_CONFIG(AHBEN, 12U)

GD32_CLOCK_WWDGT

#define GD32_CLOCK_WWDGT   GD32_CLOCK_CONFIG(APB1EN, 11U)