phy.h

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/*
 * Copyright (c) 2021 IP-Logix Inc.
 * Copyright 2022 NXP
 * Copyright (c) 2025 Aerlync Labs Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_DRIVERS_PHY_H_
#define ZEPHYR_INCLUDE_DRIVERS_PHY_H_
 
#include <zephyr/types.h>
#include <zephyr/device.h>
#include <errno.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
enum phy_link_speed {
        LINK_HALF_10BASE_T = BIT(0),
        LINK_FULL_10BASE_T = BIT(1),
        LINK_HALF_100BASE_T = BIT(2),
        LINK_FULL_100BASE_T = BIT(3),
        LINK_HALF_1000BASE_T = BIT(4),
        LINK_FULL_1000BASE_T = BIT(5),
        LINK_FULL_2500BASE_T = BIT(6),
        LINK_FULL_5000BASE_T = BIT(7),
};
 
#define PHY_LINK_IS_FULL_DUPLEX(x) (x & (BIT(1) | BIT(3) | BIT(5) | BIT(6) | BIT(7)))
 
#define PHY_LINK_IS_SPEED_1000M(x) (x & (BIT(4) | BIT(5)))
 
#define PHY_LINK_IS_SPEED_100M(x) (x & (BIT(2) | BIT(3)))
 
struct phy_link_state {
        enum phy_link_speed speed;
        bool is_up;
};
 
struct phy_plca_cfg {
        uint8_t version;
        bool enable;
        uint8_t node_id;
        uint8_t node_count;
        uint8_t burst_count;
        uint8_t burst_timer;
        uint8_t to_timer;
};
 
int genphy_get_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg);
 
int genphy_set_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg);
 
int genphy_get_plca_sts(const struct device *dev, bool *plca_status);
 
typedef void (*phy_callback_t)(const struct device *dev, struct phy_link_state *state,
                               void *user_data);
 
__subsystem struct ethphy_driver_api {
        int (*get_link)(const struct device *dev, struct phy_link_state *state);
 
        int (*cfg_link)(const struct device *dev, enum phy_link_speed adv_speeds);
 
        int (*link_cb_set)(const struct device *dev, phy_callback_t cb, void *user_data);
 
        int (*read)(const struct device *dev, uint16_t reg_addr, uint32_t *data);
 
        int (*write)(const struct device *dev, uint16_t reg_addr, uint32_t data);
 
        int (*read_c45)(const struct device *dev, uint8_t devad, uint16_t regad, uint16_t *data);
 
        int (*write_c45)(const struct device *dev, uint8_t devad, uint16_t regad, uint16_t data);
 
        /* Set PLCA settings */
        int (*set_plca_cfg)(const struct device *dev, struct phy_plca_cfg *plca_cfg);
 
        /* Get PLCA settings */
        int (*get_plca_cfg)(const struct device *dev, struct phy_plca_cfg *plca_cfg);
 
        /* Get PLCA status */
        int (*get_plca_sts)(const struct device *dev, bool *plca_sts);
};
static inline int phy_configure_link(const struct device *dev, enum phy_link_speed speeds)
{
        const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
 
        if (api->cfg_link == NULL) {
                return -ENOSYS;
        }
 
        return api->cfg_link(dev, speeds);
}
 
static inline int phy_get_link_state(const struct device *dev, struct phy_link_state *state)
{
        const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
 
        if (api->get_link == NULL) {
                return -ENOSYS;
        }
 
        return api->get_link(dev, state);
}
 
static inline int phy_link_callback_set(const struct device *dev, phy_callback_t callback,
                                        void *user_data)
{
        const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
 
        if (api->link_cb_set == NULL) {
                return -ENOSYS;
        }
 
        return api->link_cb_set(dev, callback, user_data);
}
 
static inline int phy_read(const struct device *dev, uint16_t reg_addr, uint32_t *value)
{
        const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
 
        if (api->read == NULL) {
                return -ENOSYS;
        }
 
        return api->read(dev, reg_addr, value);
}
 
static inline int phy_write(const struct device *dev, uint16_t reg_addr, uint32_t value)
{
        const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
 
        if (api->write == NULL) {
                return -ENOSYS;
        }
 
        return api->write(dev, reg_addr, value);
}
 
static inline int phy_read_c45(const struct device *dev, uint8_t devad, uint16_t regad,
                               uint16_t *data)
{
        const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
 
        if (api->read_c45 == NULL) {
                return -ENOSYS;
        }
 
        return api->read_c45(dev, devad, regad, data);
}
 
static inline int phy_write_c45(const struct device *dev, uint8_t devad, uint16_t regad,
                                uint16_t data)
{
        const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
 
        if (api->write_c45 == NULL) {
                return -ENOSYS;
        }
 
        return api->write_c45(dev, devad, regad, data);
}
 
static inline int phy_set_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg)
{
        const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
 
        if (api->set_plca_cfg == NULL) {
                return -ENOSYS;
        }
 
        return api->set_plca_cfg(dev, plca_cfg);
}
 
static inline int phy_get_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg)
{
        const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
 
        if (api->get_plca_cfg == NULL) {
                return -ENOSYS;
        }
 
        return api->get_plca_cfg(dev, plca_cfg);
}
 
static inline int phy_get_plca_sts(const struct device *dev, bool *plca_status)
{
        const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
 
        if (api->get_plca_sts == NULL) {
                return -ENOSYS;
        }
 
        return api->get_plca_sts(dev, plca_status);
}
 
#ifdef __cplusplus
}
#endif
 
#endif /* ZEPHYR_INCLUDE_DRIVERS_PHY_H_ */