Macros
#define	SDRAM_TRAS_1CYCLES (1)

#define	SDRAM_TRAS_2CYCLES (2)

#define	SDRAM_TRAS_3CYCLES (3)

#define	SDRAM_TRAS_4CYCLES (4)

#define	SDRAM_TRAS_5CYCLES (5)

#define	SDRAM_TRAS_6CYCLES (6)

#define	SDRAM_TRAS_7CYCLES (7)

#define	SDRAM_TRCD_1CYCLES (1)

#define	SDRAM_TRCD_2CYCLES (2)

#define	SDRAM_TRCD_3CYCLES (3)

#define	SDRAM_TRCD_4CYCLES (4)

#define	SDRAM_TRP_1CYCLES (1)

#define	SDRAM_TRP_2CYCLES (2)

#define	SDRAM_TRP_3CYCLES (3)

#define	SDRAM_TRP_4CYCLES (4)

#define	SDRAM_TRP_5CYCLES (5)

#define	SDRAM_TRP_6CYCLES (6)

#define	SDRAM_TRP_7CYCLES (7)

#define	SDRAM_TRP_8CYCLES (8)

#define	SDRAM_TWR_1CYCLES (1)

#define	SDRAM_TWR_2CYCLES (2)

#define	SDRAM_TCL_1CYCLES (1)

#define	SDRAM_TCL_2CYCLES (2)

#define	SDRAM_TCL_3CYCLES (3)

#define	SDRAM_TREFW_1CYCLES (1)

#define	SDRAM_TREFW_2CYCLES (2)

#define	SDRAM_TREFW_3CYCLES (3)

#define	SDRAM_TREFW_4CYCLES (4)

#define	SDRAM_TREFW_5CYCLES (5)

#define	SDRAM_TREFW_6CYCLES (6)

#define	SDRAM_TREFW_7CYCLES (7)

#define	SDRAM_TREFW_8CYCLES (8)

#define	SDRAM_TREFW_9CYCLES (9)

#define	SDRAM_TREFW_10CYCLES (10)

#define	SDRAM_TREFW_11CYCLES (11)

#define	SDRAM_TREFW_12CYCLES (12)

#define	SDRAM_TREFW_13CYCLES (13)

#define	SDRAM_TREFW_14CYCLES (14)

#define	SDRAM_TREFW_15CYCLES (15)

#define	SDRAM_TREFW_16CYCLES (16)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_3CYCLES (3)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_4CYCLES (4)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_5CYCLES (5)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_6CYCLES (6)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_7CYCLES (7)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_8CYCLES (8)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_9CYCLES (9)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_10CYCLES (10)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_11CYCLES (11)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_12CYCLES (12)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_13CYCLES (13)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_14CYCLES (14)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_15CYCLES (15)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_16CYCLES (16)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_17CYCLES (17)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_18CYCLES (18)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_19CYCLES (19)

#define	SDRAM_AUTO_REFREDSH_INTERVEL_20CYCLES (20)

#define	SDRAM_AUTO_REFREDSH_COUNT_1TIMES (1)

#define	SDRAM_AUTO_REFREDSH_COUNT_2TIMES (2)

#define	SDRAM_AUTO_REFREDSH_COUNT_3TIMES (3)

#define	SDRAM_AUTO_REFREDSH_COUNT_4TIMES (4)

#define	SDRAM_AUTO_REFREDSH_COUNT_5TIMES (5)

#define	SDRAM_AUTO_REFREDSH_COUNT_6TIMES (6)

#define	SDRAM_AUTO_REFREDSH_COUNT_7TIMES (7)

#define	SDRAM_AUTO_REFREDSH_COUNT_8TIMES (8)

#define	SDRAM_AUTO_REFREDSH_COUNT_9TIMES (9)

#define	SDRAM_AUTO_REFREDSH_COUNT_10TIMES (10)

#define	SDRAM_AUTO_REFREDSH_COUNT_11TIMES (11)

#define	SDRAM_AUTO_REFREDSH_COUNT_12TIMES (12)

#define	SDRAM_AUTO_REFREDSH_COUNT_13TIMES (13)

#define	SDRAM_AUTO_REFREDSH_COUNT_14TIMES (14)

#define	SDRAM_AUTO_REFREDSH_COUNT_15TIMES (15)

#define	SDRAM_AUTO_PRECHARGE_CYCLE_3CYCLES (3)

#define	SDRAM_AUTO_PRECHARGE_CYCLE_4CYCLES (4)

#define	SDRAM_AUTO_PRECHARGE_CYCLE_5CYCLES (5)

#define	SDRAM_AUTO_PRECHARGE_CYCLE_6CYCLES (6)

#define	SDRAM_AUTO_PRECHARGE_CYCLE_7CYCLES (7)

#define	SDRAM_AUTO_PRECHARGE_CYCLE_8CYCLES (8)

#define	SDRAM_AUTO_PRECHARGE_CYCLE_9CYCLES (9)

#define	SDRAM_AUTO_PRECHARGE_CYCLE_10CYCLES (10)

Macro Definition Documentation

◆ SDRAM_AUTO_PRECHARGE_CYCLE_10CYCLES

#define SDRAM_AUTO_PRECHARGE_CYCLE_10CYCLES (10)

◆ SDRAM_AUTO_PRECHARGE_CYCLE_3CYCLES

#define SDRAM_AUTO_PRECHARGE_CYCLE_3CYCLES (3)

◆ SDRAM_AUTO_PRECHARGE_CYCLE_4CYCLES

#define SDRAM_AUTO_PRECHARGE_CYCLE_4CYCLES (4)

◆ SDRAM_AUTO_PRECHARGE_CYCLE_5CYCLES

#define SDRAM_AUTO_PRECHARGE_CYCLE_5CYCLES (5)

◆ SDRAM_AUTO_PRECHARGE_CYCLE_6CYCLES

#define SDRAM_AUTO_PRECHARGE_CYCLE_6CYCLES (6)

◆ SDRAM_AUTO_PRECHARGE_CYCLE_7CYCLES

#define SDRAM_AUTO_PRECHARGE_CYCLE_7CYCLES (7)

◆ SDRAM_AUTO_PRECHARGE_CYCLE_8CYCLES

#define SDRAM_AUTO_PRECHARGE_CYCLE_8CYCLES (8)

◆ SDRAM_AUTO_PRECHARGE_CYCLE_9CYCLES

#define SDRAM_AUTO_PRECHARGE_CYCLE_9CYCLES (9)

◆ SDRAM_AUTO_REFREDSH_COUNT_10TIMES

#define SDRAM_AUTO_REFREDSH_COUNT_10TIMES (10)

◆ SDRAM_AUTO_REFREDSH_COUNT_11TIMES

#define SDRAM_AUTO_REFREDSH_COUNT_11TIMES (11)

◆ SDRAM_AUTO_REFREDSH_COUNT_12TIMES

#define SDRAM_AUTO_REFREDSH_COUNT_12TIMES (12)

◆ SDRAM_AUTO_REFREDSH_COUNT_13TIMES

#define SDRAM_AUTO_REFREDSH_COUNT_13TIMES (13)

◆ SDRAM_AUTO_REFREDSH_COUNT_14TIMES

#define SDRAM_AUTO_REFREDSH_COUNT_14TIMES (14)

◆ SDRAM_AUTO_REFREDSH_COUNT_15TIMES

#define SDRAM_AUTO_REFREDSH_COUNT_15TIMES (15)

◆ SDRAM_AUTO_REFREDSH_COUNT_1TIMES

#define SDRAM_AUTO_REFREDSH_COUNT_1TIMES (1)

◆ SDRAM_AUTO_REFREDSH_COUNT_2TIMES

#define SDRAM_AUTO_REFREDSH_COUNT_2TIMES (2)

◆ SDRAM_AUTO_REFREDSH_COUNT_3TIMES

#define SDRAM_AUTO_REFREDSH_COUNT_3TIMES (3)

◆ SDRAM_AUTO_REFREDSH_COUNT_4TIMES

#define SDRAM_AUTO_REFREDSH_COUNT_4TIMES (4)

◆ SDRAM_AUTO_REFREDSH_COUNT_5TIMES

#define SDRAM_AUTO_REFREDSH_COUNT_5TIMES (5)

◆ SDRAM_AUTO_REFREDSH_COUNT_6TIMES

#define SDRAM_AUTO_REFREDSH_COUNT_6TIMES (6)

◆ SDRAM_AUTO_REFREDSH_COUNT_7TIMES

#define SDRAM_AUTO_REFREDSH_COUNT_7TIMES (7)

◆ SDRAM_AUTO_REFREDSH_COUNT_8TIMES

#define SDRAM_AUTO_REFREDSH_COUNT_8TIMES (8)

◆ SDRAM_AUTO_REFREDSH_COUNT_9TIMES

#define SDRAM_AUTO_REFREDSH_COUNT_9TIMES (9)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_10CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_10CYCLES (10)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_11CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_11CYCLES (11)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_12CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_12CYCLES (12)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_13CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_13CYCLES (13)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_14CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_14CYCLES (14)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_15CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_15CYCLES (15)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_16CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_16CYCLES (16)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_17CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_17CYCLES (17)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_18CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_18CYCLES (18)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_19CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_19CYCLES (19)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_20CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_20CYCLES (20)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_3CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_3CYCLES (3)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_4CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_4CYCLES (4)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_5CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_5CYCLES (5)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_6CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_6CYCLES (6)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_7CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_7CYCLES (7)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_8CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_8CYCLES (8)

◆ SDRAM_AUTO_REFREDSH_INTERVEL_9CYCLES

#define SDRAM_AUTO_REFREDSH_INTERVEL_9CYCLES (9)

◆ SDRAM_TCL_1CYCLES

#define SDRAM_TCL_1CYCLES (1)

◆ SDRAM_TCL_2CYCLES

#define SDRAM_TCL_2CYCLES (2)

◆ SDRAM_TCL_3CYCLES

#define SDRAM_TCL_3CYCLES (3)

◆ SDRAM_TRAS_1CYCLES

#define SDRAM_TRAS_1CYCLES (1)

◆ SDRAM_TRAS_2CYCLES

#define SDRAM_TRAS_2CYCLES (2)

◆ SDRAM_TRAS_3CYCLES

#define SDRAM_TRAS_3CYCLES (3)

◆ SDRAM_TRAS_4CYCLES

#define SDRAM_TRAS_4CYCLES (4)

◆ SDRAM_TRAS_5CYCLES

#define SDRAM_TRAS_5CYCLES (5)

◆ SDRAM_TRAS_6CYCLES

#define SDRAM_TRAS_6CYCLES (6)

◆ SDRAM_TRAS_7CYCLES

#define SDRAM_TRAS_7CYCLES (7)

◆ SDRAM_TRCD_1CYCLES

#define SDRAM_TRCD_1CYCLES (1)

◆ SDRAM_TRCD_2CYCLES

#define SDRAM_TRCD_2CYCLES (2)

◆ SDRAM_TRCD_3CYCLES

#define SDRAM_TRCD_3CYCLES (3)

◆ SDRAM_TRCD_4CYCLES

#define SDRAM_TRCD_4CYCLES (4)

◆ SDRAM_TREFW_10CYCLES

#define SDRAM_TREFW_10CYCLES (10)

◆ SDRAM_TREFW_11CYCLES

#define SDRAM_TREFW_11CYCLES (11)

◆ SDRAM_TREFW_12CYCLES

#define SDRAM_TREFW_12CYCLES (12)

◆ SDRAM_TREFW_13CYCLES

#define SDRAM_TREFW_13CYCLES (13)

◆ SDRAM_TREFW_14CYCLES

#define SDRAM_TREFW_14CYCLES (14)

◆ SDRAM_TREFW_15CYCLES

#define SDRAM_TREFW_15CYCLES (15)

◆ SDRAM_TREFW_16CYCLES

#define SDRAM_TREFW_16CYCLES (16)

◆ SDRAM_TREFW_1CYCLES

#define SDRAM_TREFW_1CYCLES (1)

◆ SDRAM_TREFW_2CYCLES

#define SDRAM_TREFW_2CYCLES (2)

◆ SDRAM_TREFW_3CYCLES

#define SDRAM_TREFW_3CYCLES (3)

◆ SDRAM_TREFW_4CYCLES

#define SDRAM_TREFW_4CYCLES (4)

◆ SDRAM_TREFW_5CYCLES

#define SDRAM_TREFW_5CYCLES (5)

◆ SDRAM_TREFW_6CYCLES

#define SDRAM_TREFW_6CYCLES (6)

◆ SDRAM_TREFW_7CYCLES

#define SDRAM_TREFW_7CYCLES (7)

◆ SDRAM_TREFW_8CYCLES

#define SDRAM_TREFW_8CYCLES (8)

◆ SDRAM_TREFW_9CYCLES

#define SDRAM_TREFW_9CYCLES (9)

◆ SDRAM_TRP_1CYCLES

#define SDRAM_TRP_1CYCLES (1)

◆ SDRAM_TRP_2CYCLES

#define SDRAM_TRP_2CYCLES (2)

◆ SDRAM_TRP_3CYCLES

#define SDRAM_TRP_3CYCLES (3)

◆ SDRAM_TRP_4CYCLES

#define SDRAM_TRP_4CYCLES (4)

◆ SDRAM_TRP_5CYCLES

#define SDRAM_TRP_5CYCLES (5)

◆ SDRAM_TRP_6CYCLES

#define SDRAM_TRP_6CYCLES (6)

◆ SDRAM_TRP_7CYCLES

#define SDRAM_TRP_7CYCLES (7)

◆ SDRAM_TRP_8CYCLES

#define SDRAM_TRP_8CYCLES (8)

◆ SDRAM_TWR_1CYCLES

#define SDRAM_TWR_1CYCLES (1)

◆ SDRAM_TWR_2CYCLES

#define SDRAM_TWR_2CYCLES (2)

Macros