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◆ SF32LB52X_DMA_REQ_ATIM1_CC1
#define SF32LB52X_DMA_REQ_ATIM1_CC1 18U |
◆ SF32LB52X_DMA_REQ_ATIM1_CC2
#define SF32LB52X_DMA_REQ_ATIM1_CC2 19U |
◆ SF32LB52X_DMA_REQ_ATIM1_CC3
#define SF32LB52X_DMA_REQ_ATIM1_CC3 20U |
◆ SF32LB52X_DMA_REQ_ATIM1_CC4
#define SF32LB52X_DMA_REQ_ATIM1_CC4 21U |
◆ SF32LB52X_DMA_REQ_ATIM1_COM
#define SF32LB52X_DMA_REQ_ATIM1_COM 25U |
◆ SF32LB52X_DMA_REQ_ATIM1_TRIGGER
#define SF32LB52X_DMA_REQ_ATIM1_TRIGGER 17U |
◆ SF32LB52X_DMA_REQ_ATIM1_UPDATE
#define SF32LB52X_DMA_REQ_ATIM1_UPDATE 16U |
◆ SF32LB52X_DMA_REQ_AUDAC_CH0
#define SF32LB52X_DMA_REQ_AUDAC_CH0 41U |
◆ SF32LB52X_DMA_REQ_AUDAC_CH1
#define SF32LB52X_DMA_REQ_AUDAC_CH1 42U |
◆ SF32LB52X_DMA_REQ_AUDADC_CH0
#define SF32LB52X_DMA_REQ_AUDADC_CH0 39U |
◆ SF32LB52X_DMA_REQ_AUDADC_CH1
#define SF32LB52X_DMA_REQ_AUDADC_CH1 40U |
◆ SF32LB52X_DMA_REQ_AUDPRC_RX_CH0
#define SF32LB52X_DMA_REQ_AUDPRC_RX_CH0 53U |
◆ SF32LB52X_DMA_REQ_AUDPRC_RX_CH1
#define SF32LB52X_DMA_REQ_AUDPRC_RX_CH1 52U |
◆ SF32LB52X_DMA_REQ_AUDPRC_TX_CH0
#define SF32LB52X_DMA_REQ_AUDPRC_TX_CH0 51U |
◆ SF32LB52X_DMA_REQ_AUDPRC_TX_CH1
#define SF32LB52X_DMA_REQ_AUDPRC_TX_CH1 50U |
◆ SF32LB52X_DMA_REQ_AUDPRC_TX_CH2
#define SF32LB52X_DMA_REQ_AUDPRC_TX_CH2 49U |
◆ SF32LB52X_DMA_REQ_AUDPRC_TX_CH3
#define SF32LB52X_DMA_REQ_AUDPRC_TX_CH3 48U |
◆ SF32LB52X_DMA_REQ_AUDPRC_TX_OUT_CH0
#define SF32LB52X_DMA_REQ_AUDPRC_TX_OUT_CH0 47U |
◆ SF32LB52X_DMA_REQ_AUDPRC_TX_OUT_CH1
#define SF32LB52X_DMA_REQ_AUDPRC_TX_OUT_CH1 46U |
◆ SF32LB52X_DMA_REQ_BTIM1
#define SF32LB52X_DMA_REQ_BTIM1 14U |
◆ SF32LB52X_DMA_REQ_BTIM2
#define SF32LB52X_DMA_REQ_BTIM2 15U |
◆ SF32LB52X_DMA_REQ_GPADC
#define SF32LB52X_DMA_REQ_GPADC 38U |
◆ SF32LB52X_DMA_REQ_GPTIM1_CC1
#define SF32LB52X_DMA_REQ_GPTIM1_CC1 10U |
◆ SF32LB52X_DMA_REQ_GPTIM1_CC2
#define SF32LB52X_DMA_REQ_GPTIM1_CC2 11U |
◆ SF32LB52X_DMA_REQ_GPTIM1_CC3
#define SF32LB52X_DMA_REQ_GPTIM1_CC3 12U |
◆ SF32LB52X_DMA_REQ_GPTIM1_CC4
#define SF32LB52X_DMA_REQ_GPTIM1_CC4 13U |
◆ SF32LB52X_DMA_REQ_GPTIM1_TRIGGER
#define SF32LB52X_DMA_REQ_GPTIM1_TRIGGER 9U |
◆ SF32LB52X_DMA_REQ_GPTIM1_UPDATE
#define SF32LB52X_DMA_REQ_GPTIM1_UPDATE 8U |
◆ SF32LB52X_DMA_REQ_GPTIM2_CC1
#define SF32LB52X_DMA_REQ_GPTIM2_CC1 45U |
◆ SF32LB52X_DMA_REQ_GPTIM2_CC2
#define SF32LB52X_DMA_REQ_GPTIM2_CC2 54U |
◆ SF32LB52X_DMA_REQ_GPTIM2_CC3
#define SF32LB52X_DMA_REQ_GPTIM2_CC3 55U |
◆ SF32LB52X_DMA_REQ_GPTIM2_CC4
#define SF32LB52X_DMA_REQ_GPTIM2_CC4 56U |
◆ SF32LB52X_DMA_REQ_GPTIM2_TRIGGER
#define SF32LB52X_DMA_REQ_GPTIM2_TRIGGER 44U |
◆ SF32LB52X_DMA_REQ_GPTIM2_UPDATE
#define SF32LB52X_DMA_REQ_GPTIM2_UPDATE 43U |
◆ SF32LB52X_DMA_REQ_I2C1
#define SF32LB52X_DMA_REQ_I2C1 22U |
◆ SF32LB52X_DMA_REQ_I2C2
#define SF32LB52X_DMA_REQ_I2C2 23U |
◆ SF32LB52X_DMA_REQ_I2C3
#define SF32LB52X_DMA_REQ_I2C3 24U |
◆ SF32LB52X_DMA_REQ_I2C4
#define SF32LB52X_DMA_REQ_I2C4 3U |
◆ SF32LB52X_DMA_REQ_I2S1_RX
#define SF32LB52X_DMA_REQ_I2S1_RX 33U |
◆ SF32LB52X_DMA_REQ_I2S1_TX
#define SF32LB52X_DMA_REQ_I2S1_TX 32U |
◆ SF32LB52X_DMA_REQ_MPI1
#define SF32LB52X_DMA_REQ_MPI1 0U |
◆ SF32LB52X_DMA_REQ_MPI2
#define SF32LB52X_DMA_REQ_MPI2 1U |
◆ SF32LB52X_DMA_REQ_PDM1_L
#define SF32LB52X_DMA_REQ_PDM1_L 36U |
◆ SF32LB52X_DMA_REQ_PDM1_R
#define SF32LB52X_DMA_REQ_PDM1_R 37U |
◆ SF32LB52X_DMA_REQ_SDMMC1
#define SF32LB52X_DMA_REQ_SDMMC1 57U |
◆ SF32LB52X_DMA_REQ_SPI1_RX
#define SF32LB52X_DMA_REQ_SPI1_RX 29U |
◆ SF32LB52X_DMA_REQ_SPI1_TX
#define SF32LB52X_DMA_REQ_SPI1_TX 28U |
◆ SF32LB52X_DMA_REQ_SPI2_RX
#define SF32LB52X_DMA_REQ_SPI2_RX 31U |
◆ SF32LB52X_DMA_REQ_SPI2_TX
#define SF32LB52X_DMA_REQ_SPI2_TX 30U |
◆ SF32LB52X_DMA_REQ_USART1_RX
#define SF32LB52X_DMA_REQ_USART1_RX 5U |
◆ SF32LB52X_DMA_REQ_USART1_TX
#define SF32LB52X_DMA_REQ_USART1_TX 4U |
◆ SF32LB52X_DMA_REQ_USART2_RX
#define SF32LB52X_DMA_REQ_USART2_RX 7U |
◆ SF32LB52X_DMA_REQ_USART2_TX
#define SF32LB52X_DMA_REQ_USART2_TX 6U |
◆ SF32LB52X_DMA_REQ_USART3_RX
#define SF32LB52X_DMA_REQ_USART3_RX 27U |
◆ SF32LB52X_DMA_REQ_USART3_TX
#define SF32LB52X_DMA_REQ_USART3_TX 26U |