stm32wb0_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_SRC_CLKSLOWMUX   (STM32_SRC_LSI + 1)
	Define system & low-speed clocks.
#define	STM32_SRC_CLK16MHZ   (STM32_SRC_CLKSLOWMUX + 1)
#define	STM32_SRC_CLK32MHZ   (STM32_SRC_CLK16MHZ + 1)
#define	STM32_CLOCK_BUS_AHB0   0x50
	Bus clocks.
#define	STM32_CLOCK_BUS_APB0   0x54
#define	STM32_CLOCK_BUS_APB1   0x58
#define	STM32_CLOCK_BUS_APB2   0x60
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB0
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB2
#define	CFGR_REG   0x08
	RCC_CFGR register offset.
#define	APB2ENR_REG   0x60
	RCC_APB2ENR register offset.
#define	LPUART1_SEL(val)
	Device clk sources selection helpers.
#define	SPI2_I2S2_SEL(val)
#define	SPI3_I2S3_SEL(val)

Macro Definition Documentation

APB2ENR_REG

#define APB2ENR_REG   0x60

RCC_APB2ENR register offset.

CFGR_REG

#define CFGR_REG   0x08

RCC_CFGR register offset.

LPUART1_SEL

#define LPUART1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 1, 13, CFGR_REG)

Device clk sources selection helpers.

SPI2_I2S2_SEL

#define SPI2_I2S2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 1, 22, CFGR_REG)

SPI3_I2S3_SEL

#define SPI3_I2S3_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 3, 22, CFGR_REG)

STM32_CLOCK_BUS_AHB0

#define STM32_CLOCK_BUS_AHB0   0x50

Bus clocks.

STM32_CLOCK_BUS_APB0

#define STM32_CLOCK_BUS_APB0   0x54

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x58

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x60

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB2

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB0

STM32_SRC_CLK16MHZ

#define STM32_SRC_CLK16MHZ   (STM32_SRC_CLKSLOWMUX + 1)

STM32_SRC_CLK32MHZ

#define STM32_SRC_CLK32MHZ   (STM32_SRC_CLK16MHZ + 1)

STM32_SRC_CLKSLOWMUX

#define STM32_SRC_CLKSLOWMUX   (STM32_SRC_LSI + 1)

Define system & low-speed clocks.

Other fixed clocks.

• CLKSLOWMUX: used to query slow clock tree frequency
• CLK16MHZ: secondary clock for LPUART, SPI3/I2S and BLE
• CLK32MHZ: secondary clock for SPI3/I2S and BLE