xtensa_mpu_entry Struct Reference

Foreground MPU Entry. More...

#include <mpu.h>

Data Fields
union {
uint32_t   raw
	Raw value. More...
struct {
uint32_t   enable:1
	Enable bit for this entry. More...
uint32_t   lock:1
	Lock bit for this entry. More...
uint32_t   mbz:3
	Must be zero. More...
uint32_t   start_addr:27
	Start address of this MPU entry. More...
}   p
	Individual parts. More...
}	as
	Content of as register for WPTLB.
union {
uint32_t   raw
	Raw value. More...
struct {
uint32_t   segment:5
	The segment number of this MPU entry. More...
uint32_t   mbz1:3
	Must be zero (part 1). More...
uint32_t   access_rights:4
	Access rights associated with this MPU entry. More...
uint32_t   memory_type:9
	Memory type associated with this MPU entry. More...
uint32_t   mbz2:11
	Must be zero (part 2). More...
}   p
	Individual parts. More...
}	at
	Content of at register for WPTLB.

Detailed Description

Foreground MPU Entry.

This holds the as, at register values for one MPU entry which can be used directly by WPTLB.

Field Documentation

access_rights

uint32_t xtensa_mpu_entry::access_rights

Access rights associated with this MPU entry.

This dictates the access right from the start address of this entry, to the start address of next entry.

Refer to XTENSA_MPU_ACCESS_* macros for available rights.

[union]

union { ... } xtensa_mpu_entry::as

Content of as register for WPTLB.

This contains the start address, the enable bit, and the lock bit.

[union]

union { ... } xtensa_mpu_entry::at

Content of at register for WPTLB.

This contains the memory type, access rights, and the segment number.

enable

uint32_t xtensa_mpu_entry::enable

Enable bit for this entry.

Modifying this will also modify the corresponding bit of the MPUENB register.

lock

uint32_t xtensa_mpu_entry::lock

Lock bit for this entry.

Usable only if MPULOCKABLE parameter is enabled in processor configuration.

Once set:

• This cannot be cleared until reset.
• This entry can no longer be modified.
• The start address of the next entry also cannot be modified.

mbz

uint32_t xtensa_mpu_entry::mbz

Must be zero.

mbz1

uint32_t xtensa_mpu_entry::mbz1

Must be zero (part 1).

mbz2

uint32_t xtensa_mpu_entry::mbz2

Must be zero (part 2).

memory_type

uint32_t xtensa_mpu_entry::memory_type

Memory type associated with this MPU entry.

This dictates the memory type from the start address of this entry, to the start address of next entry.

This affects how the hardware treats the memory, for example, cacheable vs non-cacheable, shareable vs non-shareable. Refer to the Xtensa Instruction Set Architecture (ISA) manual for general description, and the processor manual for processor specific information.

[struct] [1/2]

struct { ... } xtensa_mpu_entry::p

Individual parts.

[struct] [2/2]

struct { ... } xtensa_mpu_entry::p

Individual parts.

raw

uint32_t xtensa_mpu_entry::raw

Raw value.

segment

uint32_t xtensa_mpu_entry::segment

The segment number of this MPU entry.

start_addr

uint32_t xtensa_mpu_entry::start_addr

Start address of this MPU entry.

Effective bits in this portion are affected by the minimum segment size of each MPU entry, ranging from 32 bytes to 4GB.

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The documentation for this struct was generated from the following file:

• zephyr/arch/xtensa/mpu.h