This is the documentation for the latest (main) development branch of Zephyr. If you are looking for the documentation of previous releases, use the drop-down menu on the left and select the desired version.

st,stm32f3-rcc

Vendor: STMicroelectronics

Description

STM32F3 Reset and Clock controller node.
Adds the STM32F3 ADC prescaler to the standard generic STM32 RCC.
For more description confere st,stm32-rcc.yaml

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

Number of items to expect in a Clock specifier

This property is required.

Constant value: 2

clock-frequency

int

default frequency in Hz for clock output

This property is required.

ahb-prescaler

int

AHB prescaler. Defines actual core clock frequency (HCLK)
based on system frequency input.
The HCLK clocks CPU, AHB, memories and DMA.

This property is required.

Legal values: 1, 2, 4, 8, 16, 64, 128, 256, 512

apb1-prescaler

int

This property is required.

Legal values: 1, 2, 4, 8, 16

apb2-prescaler

int

This property is required.

Legal values: 1, 2, 4, 8, 16

undershoot-prevention

boolean

On some parts, it could be required to set up highest core frequencies
(>80MHz) in two steps in order to prevent undershoot.
This is done by applying an intermediate AHB prescaler before switching
System Clock source to PLL. Once done, prescaler is set back to expected
value.

adc12-prescaler

int

ADC 1 and 2 prescaler
- 0: Disables the clock so the ADC can use AHB clock (synchronous mode)
- Other values n: The ADC can use the PLL clock divided by n
On STM32F37x, only 2/4/6/8 are allowed.

Legal values: 0, 1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256

adc34-prescaler

int

ADC 3 and 4 prescaler
- 0: Disables the clock so the ADC can use AHB clock (synchronous mode)
- Other values n: The ADC can use the PLL clock divided by n
Check RefMan for availability.

Legal values: 0, 1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256

Specifier cell names

  • clock cells: bus, bits