st,stm32n6-pll-clock

Vendor: STMicroelectronics

Description

PLL node binding for STM32N6 devices

It can be used to describe 4 different PLLs: PLL1, PLL2, PLL3 and PLL4.

These PLLs can take one of clk_hse, clk_hsi or clk_msi as input clock, with
an input frequency from 5 to 50 MHz. PLLM factor is used to set the input
clock in this acceptable range.

Each PLL has one output clock whose frequency can be computed with the
following formula:

  f(PLL_P) = f(VCO clock) / (PLLP1 × PLLP2)

    with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

Note: To reduce the power consumption, it is recommended to configure the VCOx
      clock output to the lowest frequency.

The PLL output frequency must not exceed 3200 MHz.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

Number of items to expect in a Clock specifier

This property is required.

div-m

int

Prescaler for PLLx
input clock
Valid range: 1 - 63

This property is required.

mul-n

int

PLLx multiplication factor for VCO
Valid range: 16 - 2500

This property is required.

div-p1

int

PLLx DIVP1 division factor
Valid range: 1 - 7

div-p2

int

PLLx DIVP2 division factor
Valid range: 1 - 7