This is the documentation for the latest (main) development branch of Zephyr. If you are looking for the documentation of previous releases, use the drop-down menu on the left and select the desired version.

st,stm32u5-pll-clock

Vendor: STMicroelectronics

Description

PLL node binding for STM32U5 devices

It can be used to describe 3 different PLLs: PLL1, PLL2 and PLL3.

These PLLs could take one of clk_hse, clk_hsi or clk_msis as input clock, with
an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.

Each PLL can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formulae:

  f(PLL_P) = f(VCO clock) / PLLP
  f(PLL_Q) = f(VCO clock) / PLLQ
  f(PLL_R) = f(VCO clock) / PLLR

    with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

Note: To reduce the power consumption, it is recommended to configure the VCOx
      clock output to the lowest frequency.

The PLL output frequency must not exceed 160 MHz.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

Number of items to expect in a Clock specifier

This property is required.

div-m

int

Prescaler for PLLx
input clock
Valid range: 1 - 16

This property is required.

mul-n

int

PLLx multiplication factor for VCO
Valid range: 4 - 512

This property is required.

div-p

int

PLLx DIVP division factor
Valid range: 1 - 128

div-q

int

PLLx DIVQ division factor
Valid range: 1 - 128

div-r

int

PLLx DIVR division factor
On PLL1, only division by 1 and even division values are allowed.
No restrictions for PLL2 and PLL3
Valid range: 1 - 128

This property is required.