st,stm32wb0-rcc

Vendor: STMicroelectronics

Description

STM32WB0 Reset and Clock controller node for STM32WB0 devices
This node is in charge of the system clock ('SYSCLK') source
selection and generation.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.

Constant value: 2

clock-frequency

int

 
default frequency in Hz for clock output

This property is required.

slow-clock

phandle

 
Slow clock source selection.
On STM32WB0, all slow clock devices are clocked from the same
slow clock source, which is selected by this property.

The slow clock can be either clk_lsi, clk_lse, or clk_16mhz_div512.

clksys-prescaler

int

 
CLK_SYS prescaler. Defines actual core clock frequency (CLK_SYS) based
on system frequency input (SYSCLK).
The CLK_SYS is used to clock the CPU, AHB, APB, memories and PKA.

NOTE: if the 32MHz HSE is used as SYSCLK source, the prescaler cannot
be set to 64.

This property is required.

Legal values: 1, 2, 4, 8, 16, 32, 64

Specifier cell names

  • clock cells: bus, bits