andestech,atcdmac300

Note

An implementation of a driver matching this compatible is available in drivers/dma/dma_andes_atcdmac300.c.

Description

These nodes are “dma” bus nodes.

Andes DMA controller
channel: a phandle to the DMA controller plus the following four integer cells:
  1. channel: the dma channel
  2. slot: DMA peripheral request ID
  3. channel-config: A 32bit mask specifying the DMA channel configuration
  which is device dependent:
      -bit 0-1 : Direction  (see dma.h)
             0x0: MEM to MEM
             0x1: MEM to PERIPH
             0x2: PERIPH to MEM
             0x3: reserved for PERIPH to PERIPH
      -bit 2 : Peripheral Increment Address
             0x0: no address increment between transfers
             0x1: increment address between transfers
      -bit 3 : Memory Increment Address
             0x0: no address increment between transfers
             0x1: increment address between transfers
      -bit 4-6 : Peripheral data size
             0x0: Byte (8 bits)
             0x1: Half-word (16 bits)
             0x2: Word (32 bits)
             0x3: Double word (64 bits)
             0x4: Quad word (128 bits)
             0x5: Eight word (256 bits)
             0x6-0x7: reserved
      -bit 7-9 : Memory data size
             0x0: Byte (8 bits)
             0x1: Half-word (16 bits)
             0x2: Word (32 bits)
             0x3: Double word (64 bits)
             0x4: Quad word (128 bits)
             0x5: Eight word (256 bits)
             0x6-0x7: reserved
      -bit 10 : Priority level
             0x0: lower priority
             0x1: higher priority

  examples for andes_v5_ae350 DMA instance
   dma0: dma0@f0c00000 {
       compatible = "andestech,atcdmac300";
       ...
       dma-channels = <8>;
       dma-requests = <16>;
       status = "disabled";
       label = "DMA_0";
      };

For the client part, example for andes_ae350 DMA instance
  Tx using channel 2, slot 0
  Rx using channel 3, slot 1
  spi1: spi@f0f00000 {
   compatible = "andestech,atcspi200"
   dmas = <&dma0 2 0 0x0129>,
          <&dma0 3 1 0x012A>;
   dma-names = "tx", "rx";
   };

Properties

Properties not inherited from the base binding file.

Name	Type	Details
`chain-transfer`	`int`
`#dma-cells`	`int`	Number of items to expect in a DMA specifier This property is required. Constant value: `3`
`dma-channel-mask`	`int`	Bitmask of available DMA channels in ascending order that are not reserved by firmware and are available to the kernel. i.e. first channel corresponds to LSB.
`dma-channels`	`int`	Number of DMA channels supported by the controller
`dma-requests`	`int`	Number of DMA request signals supported by the controller.
`dma-buf-addr-alignment`	`int`	Memory address alignment requirement for DMA buffers used by the controller.
`dma-buf-size-alignment`	`int`	Memory size alignment requirement for DMA buffers used by the controller.
`dma-copy-alignment`	`int`	Minimal chunk of data possible to be copied by the controller.

Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “andestech,atcdmac300” compatible.

Name	Type	Details
`reg`	`array`	register space This property is required. See Important properties for more information.
`interrupts`	`array`	interrupts for device This property is required. See Important properties for more information.
`status`	`string`	indicates the operational status of a device Legal values: `'ok'`, `'okay'`, `'disabled'`, `'reserved'`, `'fail'`, `'fail-sss'` See Important properties for more information.
`compatible`	`string-array`	compatible strings This property is required. See Important properties for more information.
`reg-names`	`string-array`	name of each register space
`interrupts-extended`	`compound`	extended interrupt specifier for device
`interrupt-names`	`string-array`	name of each interrupt
`interrupt-parent`	`phandle`	phandle to interrupt controller node
`label`	`string`	No description provided for this label See Important properties for more information.
`clocks`	`phandle-array`	Clock gate information
`clock-names`	`string-array`	name of each clock
`#address-cells`	`int`	number of address cells in reg property
`#size-cells`	`int`	number of size cells in reg property
`dmas`	`phandle-array`	DMA channels specifiers
`dma-names`	`string-array`	Provided names of DMA channel specifiers
`io-channels`	`phandle-array`	IO channels specifiers
`io-channel-names`	`string-array`	Provided names of IO channel specifiers
`mboxes`	`phandle-array`	mailbox / IPM channels specifiers
`mbox-names`	`string-array`	Provided names of mailbox / IPM channel specifiers
`power-domains`	`phandle-array`	Power domain specifiers
`power-domain-names`	`string-array`	Provided names of power domain specifiers
`#power-domain-cells`	`int`	Number of cells in power-domains property
`zephyr,deferred-init`	`boolean`	Do not initialize device automatically on boot. Device should be manually initialized using device_init().
`wakeup-source`	`boolean`	Property to identify that a device can be used as wake up source. When this property is provided a specific flag is set into the device that tells the system that the device is capable of wake up the system. Wake up capable devices are disabled (interruptions will not wake up the system) by default but they can be enabled at runtime if necessary.
`zephyr,pm-device-runtime-auto`	`boolean`	Automatically configure the device for runtime power management after the init function runs.
`zephyr,disabling-power-states`	`phandles`	List of power states that will disable this device power.

Specifier cell names

dma cells: channel, slot, channel-config