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nxp,mcux-edma-v4

Vendor: NXP Semiconductors

Description

These nodes are “dma” bus nodes.

NXP MCUX EDMA version 4 controller

Properties

Properties not inherited from the base binding file.

Name

Type

Details

no-error-irq

boolean

If the SoCs don't have a separate interrupt id for error IRQ.

dma-channels

int

Number of DMA channels supported by the controller

This property is required.

dma-requests

int

Number of DMA request signals supported by the controller.

This property is required.

dmamux-reg-offset

int

The offset value for obtaining DMAMUX register index from DMAMUX channel. Default value means DMAMUX channel is identical with DMAMUX register index

channel-gap

array

On some platforms, there may be a gap in the channels and
this array specifies the start and end of a single gap

nxp,mem2mem

boolean

If the DMA controller supports memory to memory transfer

nxp,a_on

boolean

If the DMA controller supports always on

irq-shared-offset

int

Describes an offset between two channels share the same interrupt entry.
Default value means each channel has separate interrupt entry.

#dma-cells

int

Number of items to expect in a DMAMUX specifier

This property is required.

dma-channel-mask

int

Bitmask of available DMA channels in ascending order that are
not reserved by firmware and are available to the
kernel. i.e. first channel corresponds to LSB.

dma-buf-addr-alignment

int

Memory address alignment requirement for DMA buffers used by the controller.

dma-buf-size-alignment

int

Memory size alignment requirement for DMA buffers used by the controller.

dma-copy-alignment

int

Minimal chunk of data possible to be copied by the controller.

Specifier cell names

  • dma cells: mux, source