xlnx,eth-dma

Vendor: Xilinx

Note

An implementation of a driver matching this compatible is available in drivers/dma/dma_xilinx_axi_dma.c.

Description

These nodes are “dma” bus nodes.

Xilinx AXI DMA LogiCORE IP controller with compatibility string
generated in use with the AXI Ethernet subsystem.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

clock-frequency

int

xlnx,addrwidth

int

DMA address width (64 or 32 bit)

This property is required.

Legal values: 32, 64

axistream-connected

phandle

Handle to connected node, e.g., AXI Ethernet controller.
The axistream-connected and axistream-control-connected properties can easily cause circular
dependencies, if they are provided at the second device as well.
In this case, the python device tree script fails to assign ordinals, causing build failure.
I suggest you do not provide them at the DMA.

axistream-control-connected

phandle

Handle to connected control node, e.g., AXI Ethernet controller

xlnx,include-dre

boolean

Data realignment engine activated. This enables unaligned DMA transfers.

xlnx,num-queues

int

Number of queues per channel.

#dma-cells

int

Number of items to expect in a DMA specifier

This property is required.

dma-channel-mask

int

Bitmask of available DMA channels in ascending order that are
not reserved by firmware and are available to the
kernel. i.e. first channel corresponds to LSB.

dma-channels

int

Number of DMA channels supported by the controller

dma-requests

int

Number of DMA request signals supported by the controller.

dma-buf-addr-alignment

int

Memory address alignment requirement for DMA buffers used by the controller.

dma-buf-size-alignment

int

Memory size alignment requirement for DMA buffers used by the controller.

dma-copy-alignment

int

Minimal chunk of data possible to be copied by the controller.