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st,stm32-ospi-nor (on ospi bus)

Vendor: STMicroelectronics


STM32 OSPI Flash controller supporting the JEDEC CFI interface

Representation of a serial flash on a octospi bus:

    mx25lm51245: ospi-nor-flash@0 {
            compatible = "st,stm32-ospi-nor";
            reg = <0>;
            data-mode = <OSPI_OPI_MODE>; /* access on 8 data lines */
            data-rate = <OSPI_DTR_TRANSFER>; /* access in DTR */
            ospi-max-frequency = <DT_FREQ_M(50)>;
            size = <DT_SIZE_M(64*8)>; /* 512 Mbit */
            status = "okay";


Properties not inherited from the base binding file.






Maximum clock frequency of device's OSPI interface in Hz

This property is required.



Flash Memory size in bits

This property is required.



RESETn pin



The width of (Octo)SPI bus to which flash memory is connected.

Possible values are :
 - OSPI_SPI_MODE  <1> = SPI mode on 1 data line
 - OSPI_DUAL_MODE <2> = Dual mode on 2 data lines
 - OSPI_QUAD_MODE <4> = Quad mode on 4 data lines
 - OSPI_OPI_MODE  <8> = Octo mode on 8 data lines

This property is required.

Legal values: 1, 2, 4, 8



The SPI data Rate is STR or DTR

Possible values are :
 - OSPI_STR_TRANSFER <1> = Single Rate Transfer
 - OSPI_DTR_TRANSFER <2> = Dual Rate Transfer (only with OSPI_OPI_MODE)

This property is required.

Legal values: 1, 2



The value encodes number of I/O lines used for the opcode,
address, and data.

There is no info about quad page program opcodes in the SFDP
tables, hence it has been assumed that NOR flash memory
supporting 1-4-4 mode also would support fast page programming.

Intended for modes other than OSPI_OPI_MODE.

If absent, then program page opcode is determined by the

* OSPI_SPI_MODE -> PP 1-1-1 (0x02)
* OSPI_DUAL_MODE -> PP 1-1-2 (0xA2)
* OSPI_QUAD_MODE -> PP 1-4-4 (0x38)

Legal values: 'PP', 'PP_1_1_2', 'PP_1_1_4', 'PP_1_4_4'



Some NOR-Flash ICs use different opcodes when operating in
4 byte addressing mode.

When enabled, then 3 byte opcodes will be converted to
4 byte opcodes.

* PP 1-1-1 (0x02) -> PP 1-1-1 4B (0x12)
* PP 1-1-4 (0x32) -> PP 1-1-4 4B (0x34)
* PP 1-4-4 (0x38) -> PP 1-4-4 4B (0x3E)

* READ 1-1-1 (0x03) -> READ 1-1-1 4B (0x13)
* READ FAST 1-1-1 (0x0B) -> READ FAST 1-1-1 4B (0x0C)
* DREAD 1-1-2 (0x3B) -> DREAD 1-1-2 4B (0x3C)
* 2READ 1-2-2 (0xBB) -> 2READ 1-2-2 4B (0xBC)
* QREAD 1-1-4 (0x6B) -> QREAD 1-1-4 4B (0x6C)
* 4READ 1-4-4 (0xEB) -> 4READ 1-4-4 4B (0xEC)



JEDEC ID as manufacturer ID, memory type, memory density



Contains the 32-bit words in little-endian byte order from the
JESD216 Serial Flash Discoverable Parameters Basic Flash
Parameters table.  This provides flash-specific configuration
information in cases were runtime retrieval of SFDP data
is not desired.



Quad Enable Requirements value from JESD216 BFP DW15.

Use NONE if the device detects 1-1-4 and 1-4-4 modes by the
instruction.  Use S1B6 if QE is bit 6 of the first status register
byte, and can be configured by reading then writing one byte with
RDSR and WRSR.  For other fields see the specification.

Legal values: 'NONE', 'S2B1v1', 'S1B6', 'S2B7', 'S2B1v4', 'S2B1v5', 'S2B1v6'



Enter 4-Byte Addressing value from JESD216 BFP DW16

This property is ignored if the device is configured to use SFDP data
from the sfdp-bfp property (CONFIG_SPI_NOR_SFDP_DEVICETREE) or to read
SFDP properties at runtime (CONFIG_SPI_NOR_SFDP_RUNTIME).

For CONFIG_SPI_NOR_SFDP_MINIMAL this is the 8-bit value from bits 31:24
of DW16 identifying ways a device can be placed into 4-byte addressing
mode.  If provided as a non-zero value the driver assumes that 4-byte
addressing is require to access the full address range, and
automatically puts the device into 4-byte address mode when the device
is initialized.