ite,enhance-i2c

Description

These nodes are “i2c” bus nodes.

ITE enhance I2C

Properties

Properties not inherited from the base binding file.

Name

Type

Details

prescale-scl-low

int

This option is used to configure the I2C speed prescaler for
the SCL low period. When set to >= 1, it will increase the
low period of the SCL clock and so reduce the signal frequency.
The resulting SCL cycle time is given by the following formula:
SCL cycle = 2 * (psr + prescale_tweak + 2) *
            SMBus clock cycle

data-hold-time

int

This option is used to configure the data hold time of the I2C.
The unit is number of SMB clock cycles.  The time calculation
is (data-hold-time / smb_clk) seconds.

Default value: 3

Legal values: 3, 4, 5, 6, 7, 8, 9, 10

target-enable

boolean

This option is used when the I2C target is enabled. It is
necessary to prevent the target port from being configured
with I2C host related initialization.

target-pio-mode

boolean

This option is used when the I2C target is enabled and it can
support PIO mode for I2C target transfer.

scl-sda-low-timeout

int

This option is used to configure the SCL/SDA low hardware timeout.
The timeout value specifies the number of 1024 kHz clock periods
to wait, which roughly translates to milliseconds of delay.
If this property is not specified, the driver defaults to the longest
possible SCL/SDA low timeout of 255 (which is 249 ms).

The ITE enhance driver also supports a software timeout using the
zephyr,transfer-timeout-ms property (or CONFIG_I2C_TRANSFER_TIMEOUT_MS).

The shorter timeout value (hardware or software) configures the maximum
clock stretch time supported on this I2C bus.

To support I2C targets that clock stretch longer than 249ms, set
scl-sda-low-timeout-ms to 0 to disable the hardware timer. The maximum
clock stretch time is then configured using the software timeout property
zephyr,transfer-timeout-ms.

Value range: 0 to 255

port-num

int

Ordinal identifying the port 0 = SMB_CHANNEL_A, 1 = SMB_CHANNEL_B, 2 = SMB_CHANNEL_C, 3 = I2C_CHANNEL_D, 4 = I2C_CHANNEL_E, 5 = I2C_CHANNEL_F,

This property is required.

Legal values: 0, 1, 2, 3, 4, 5

channel-switch-sel

int

The default setting is as described below
0 = I2C_CHA_LOCATE: Channel A is located at SMCLK0/SMDAT0
1 = I2C_CHB_LOCATE: Channel B is located at SMCLK1/SMDAT1
2 = I2C_CHC_LOCATE: Channel C is located at SMCLK2/SMDAT2
3 = I2C_CHD_LOCATE: Channel D is located at SMCLK3/SMDAT3
4 = I2C_CHE_LOCATE: Channel E is located at SMCLK4/SMDAT4
5 = I2C_CHF_LOCATE: Channel F is located at SMCLK5/SMDAT5

The following is an example of the 'channel-switch-sel' property
being swapped between node &i2c0 and &i2c2 in the application:
Note: The property of 'port-num' cannot be changed in the
      application.

Channel C is located at SMCLK0/SMDAT0:
&i2c0 {
       channel-switch-sel = <I2C_CHC_LOCATE>;
       pinctrl-0 = <&i2c2_clk_gpf6_default
                    &i2c2_data_gpf7_default>;
       pinctrl-names = "default";
       scl-gpios = <&gpiof 6 0>;
       sda-gpios = <&gpiof 7 0>;
};

Channel A is located at SMCLK2/SMDAT2:
&i2c2 {
       channel-switch-sel = <I2C_CHA_LOCATE>;
       pinctrl-0 = <&i2c0_clk_gpb3_default
                    &i2c0_data_gpb4_default>;
       pinctrl-names = "default";
       scl-gpios = <&gpiob 3 0>;
       sda-gpios = <&gpiob 4 0>;
};

If the property of 'channel-switch-sel' is changed, the pinctrl
setting and recovery pin in &i2c0 and &i2c2 nodes must also be
modified accordingly.

This property is required.

Legal values: 0, 1, 2, 3, 4, 5

scl-gpios

phandle-array

The SCL pin for the selected port.

This property is required.

sda-gpios

phandle-array

The SDA pin for the selected port.

This property is required.

clock-gate-offset

int

The clock gate offsets combine the register offset from
ECPM_BASE and the mask within that register into one value.

This property is required.

pinctrl-0

phandles

Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

This property is required.

pinctrl-names

string-array

Names for the provided states. The number of names needs to match the
number of states.

This property is required.

push-pull-recovery

boolean

This property is enabled when selecting the push-pull GPIO output
type to drive the I2C recovery. The default is open-drain.

clock-frequency

int

Initial clock frequency in Hz

sq-size

int

Size of the submission queue for blocking requests

Default value: 4

cq-size

int

Size of the completion queue for blocking requests

Default value: 4

zephyr,transfer-timeout-ms

int

Maximum time to wait for an I2C transfer to complete, in milliseconds.
When absent, the default value is CONFIG_I2C_TRANSFER_TIMEOUT_MS.

pinctrl-1

phandles

Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

Pin configuration/s for the fifth state. See pinctrl-0.