st,stm32wl-subghz-radio (on spi bus)

Vendor: STMicroelectronics

Note

An implementation of a driver matching this compatible is available in drivers/lora.

Description

STM32WL SUBGHZ Radio

Properties

Properties not inherited from the base binding file.

Name

Type

Details

supply-gpios

phandle-array

GPIO specifier that controls power to the device.

This property should be provided when the device has a dedicated
switch that controls power to the device.  The supply state is
entirely the responsibility of the device driver.

Contrast with vin-supply.

vin-supply

phandle

Reference to the regulator that controls power to the device.
The referenced devicetree node must have a regulator compatible.

This property should be provided when device power is supplied
by a shared regulator.  The supply state is dependent on the
request status of all devices fed by the regulator.

Contrast with supply-gpios.  If both properties are provided
then the regulator must be requested before the supply GPIOS is
set to an active state, and the supply GPIOS must be set to an
inactive state before releasing the regulator.

spi-max-frequency

int

Maximum clock frequency of device's SPI interface in Hz

This property is required.

duplex

int

Duplex mode, full or half. By default it's always full duplex thus 0
as this is, by far, the most common mode.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
  0    SPI_FULL_DUPLEX
  2048 SPI_HALF_DUPLEX

Legal values: 0, 2048

frame-format

int

Motorola or TI frame format. By default it's always Motorola's,
thus 0 as this is, by far, the most common format.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
  0     SPI_FRAME_FORMAT_MOTOROLA
  32768 SPI_FRAME_FORMAT_TI

Legal values: 0, 32768

spi-cpol

boolean

SPI clock polarity which indicates the clock idle state.
If it is used, the clock idle state is logic high; otherwise, low.

spi-cpha

boolean

SPI clock phase that indicates on which edge data is sampled.
If it is used, data is sampled on the second edge; otherwise, on the first edge.

spi-hold-cs

boolean

In some cases, it is necessary for the master to manage SPI chip select
under software control, so that multiple spi transactions can be performed
without releasing it. A typical use case is variable length SPI packets
where the first spi transaction reads the length and the second spi transaction
reads length bytes.

reset-gpios

phandle-array

GPIO connected to the modem's NRESET signal.

This signal is open-drain, active-low as interpreted by the
modem.

busy-gpios

phandle-array

GPIO connected to the modem's BUSY signal.

antenna-enable-gpios

phandle-array

Antenna power enable pin.

tx-enable-gpios

phandle-array

Antenna switch TX enable GPIO. If set, the driver tracks the
state of the radio and controls the RF switch.

rx-enable-gpios

phandle-array

Antenna switch RX enable GPIO. If set, the driver tracks the
state of the radio and controls the RF switch.

dio1-gpios

phandle-array

GPIO connected to DIO1. This GPIO will be used as a generic
IRQ line from the chip.

dio2-tx-enable

boolean

Use DIO2 to drive an RF switch selecting between the TX and RX
paths. When enabled, DIO2 goes high when the chip is
transmitting.

dio3-tcxo-voltage

int

TCXO supply voltage controlled by DIO3 if present.

See constants in dt-bindings/lora/sx126x.h.

tcxo-power-startup-delay-ms

int

Startup delay to let the TCXO stabilize after TCXO power on.

power-amplifier-output

string

Selects between the low- and high-power power amplifier output pin.

This property is required.

Legal values: 'rfo-lp', 'rfo-hp'

rfo-lp-max-power

int

Maximum design power for the board's RFO_LP output matching network.

The default setting of +14 dBm is a prevalent board configuration;
however, for optimal performance, it is advisable to align the value with
the board's RF design.

See ST application note AN5457, chapter 5.1.2 for more information.

Default value: 14

Legal values: 10, 14, 15

rfo-hp-max-power

int

Maximum design power for the board's RFO_HP output matching network.

The default setting of +22 dBm is a prevalent board configuration;
however, for optimal performance, it is advisable to align the value with
the board's RF design.

See ST application note AN5457, chapter 5.1.2 for more information.

Default value: 22

Legal values: 14, 17, 20, 22