renesas,ra-sdram

Vendor: Renesas Electronics Corporation

Note

An implementation of a driver matching this compatible is available in drivers/memc/memc_renesas_ra_sdram.c.

Description

Renesas RA SDRAM controller.
sdram {
    pinctrl-0 = <&sdram_default>;
    pinctrl-names = "default";
    status = "okay";
    auto-refresh-interval = <10>;
    auto-refresh-count = <8>;
    precharge-cycle-count = <3>;
    multiplex-addr-shift = "10-bit";
    edian-mode = "little-endian";
    continuous-access;
    bus-width = "16-bit";
    bank@0 {
      reg = <0>;
      renesas,ra-sdram-timing = <RENESAS_RA_SDRAM_TRAS_6CYCLES
                RENESAS_RA_SDRAM_TRCD_3CYCLES
                RENESAS_RA_SDRAM_TRP_3CYCLES
                RENESAS_RA_SDRAM_TWR_2CYCLES
                RENESAS_RA_SDRAM_TCL_3CYCLES
                937
                RENESAS_RA_SDRAM_TREFW_8CYCLES>;
    };

Note that you will find definitions for the renesas,ra-sdram-control field at
dt-bindings/memory-controller/renesas,ra-sdram.h. This file is already included
in the SoC DeviceTree files.

Finally, in order to make the memory available you will need to define new
memory device/s in DeviceTree:

sdram1: sdram@68000000 {
    compatible = "zephyr,memory-region", "mmio-sram";
    device_type = "memory";
    reg = <0x68000000 DT_SIZE_M(X)>;
    zephyr,memory-region = "SDRAM";
};

Properties

Top level properties

These property descriptions apply to “renesas,ra-sdram” nodes themselves. This page also describes child node properties in the following sections.

Node specific propertiesDeprecated node specific propertiesBase properties

Properties not inherited from the base binding file.

Name	Type	Details
pinctrl-0	phandles	Pin configuration/s for the first state. Content is specific to the selected pin controller driver implementation. This property is required.
pinctrl-names	string-array	Names for the provided states. The number of names needs to match the number of states. This property is required.
auto-refresh-interval	int	Number of auto-refresh-interval. Default value: 10
auto-refresh-count	int	Number of auto-refresh-count. Default value: 8
precharge-cycle-count	int	Number of precharge-cycle-count. Default value: 3
multiplex-addr-shift	string	Select the size of the shift towards the lower half of the row address in row address/column address multiplexing. Default value: 10-bit Legal values: '8-bit', '9-bit', '10-bit', '11-bit'
edian-mode	string	Specifies the endianness for the SDRAM address space. Default value: little-endian Legal values: 'little-endian', 'big-endian'
continuous-access	boolean	Enables or disables continuous access to the SDRAM access space.
bus-width	string	Specify the data bus width for SDRAM Default value: 16-bit Legal values: '16-bit', '32-bit', '8-bit'
pinctrl-1	phandles	Pin configuration/s for the second state. See pinctrl-0.
pinctrl-2	phandles	Pin configuration/s for the third state. See pinctrl-0.
pinctrl-3	phandles	Pin configuration/s for the fourth state. See pinctrl-0.
pinctrl-4	phandles	Pin configuration/s for the fifth state. See pinctrl-0.

Child node properties

Name	Type	Details
reg	int	This property is required. See Important properties for more information.
renesas,ra-sdram-timing	array	SDRAM timing configuration. Expected fields, in order, are, - TRAS: Row active interval. The effective value from 1 to 7 cycles - TRCD: Row column latency. The effective value from 1 to 4 cycles - TRP: Row precharge interval. The effective value from 1 to 8 cycles - TWR: Write recovery interval. The effective value from 1 to 2 cycles - TCL: Column latency. The effective value from 1 to 3 cycles - TRFC: Auto-Refresh Request Interval Setting. - TREFW: Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count Setting. The effective value from 1 to 16 cycles This property is required.