nxp,s32-emios
Vendor: NXP Semiconductors
Note
An implementation of a driver matching this compatible is available in drivers/misc/nxp_s32_emios/nxp_s32_emios.c.
Description
NXP S32 Enhanced Modular IO SubSystem (eMIOS) node for S32 SoCs.
eMIOS provides independent unified channels (UCs), some of channels
have internal counter that either can be used independently or used
as a reference timebase (master bus) for other channels.
Properties
Top level properties
These property descriptions apply to “nxp,s32-emios” nodes themselves. This page also describes child node properties in the following sections.
Properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
|
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Clock divider value for the global prescaler. Could be in range [1 ... 256]
This property is required. |
|
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A mask for channels that have internal counter, lsb is channel 0.
This property is required. |
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “nxp,s32-emios” compatible.
Name |
Type |
Details |
|---|---|---|
|
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register space
This property is required. See Important properties for more information. |
|
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interrupts for device
This property is required. See Important properties for more information. |
|
|
name of each interrupt
This property is required. |
|
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Clock gate information
This property is required. |
|
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indicates the operational status of a device
Legal values: See Important properties for more information. |
|
|
compatible strings
This property is required. See Important properties for more information. |
|
|
name of each register space
|
|
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extended interrupt specifier for device
|
|
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phandle to interrupt controller node
|
|
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No description provided for this label
See Important properties for more information. |
|
|
name of each clock
|
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number of address cells in reg property
|
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number of size cells in reg property
|
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DMA channels specifiers
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Provided names of DMA channel specifiers
|
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IO channels specifiers
|
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Provided names of IO channel specifiers
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mailbox / IPM channels specifiers
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Provided names of mailbox / IPM channel specifiers
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Power domain specifiers
|
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Provided names of power domain specifiers
|
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Number of cells in power-domains property
|
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
|
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
|
|
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
|
Grandchild node properties
Name |
Type |
Details |
|---|---|---|
|
|
Channel identifier for the master bus.
This property is required. |
|
|
A channel mask for channels that by hardware design can use this master bus
as timebase for the operation, lsb is channel 0. The mask bit for this master bus
must always 0 because a master bus should not do other thing than a base timer.
This property is required. |
|
|
Clock divider value for internal UC prescaler.
Clock for internal counter = (eMIOS clock / global prescaler) / internal prescaler.
This property is required. Legal values: |
|
|
Master bus type.
This property is required. Legal values: |
|
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Master bus mode.
This property is required. Legal values: |
|
|
Default period (in ticks) for master bus at boot time. This determines PWM period
for channels use this bus as reference timebase. Could be in range [2 ... 65535]
This property is required. |
|
|
Freeze internal counter when the chip enters Debug mode.
|