nuvoton,numaker-pinctrl
Vendor: Nuvoton Technology Corporation
Note
An implementation of a driver matching this compatible is available in drivers/pinctrl/pinctrl_numaker.c.
Description
Pin controller is responsible for controlling pin function
selection and pin properties. For example, for example you can
use this node to set UART0 RX as pin PB12 to fulfill SYS_GPB_MFP3_PB12MFP_UART0_RXD.
The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this:
&pinctrl {
/* your modifications go here */
};
All device pin configurations should be placed in child nodes of the
'pinctrl' node, as shown in this example:
&pinctrl {
/* configuration for the uart0 "default" state */
uart0_default: uart0_default {
/* configure PB13 as UART0 TX and PB12 as UART0 RX */
group0 {
pinmux = <PB12MFP_UART0_RXD>, <PB13MFP_UART0_TXD>;
};
};
};
To link pin configurations with a device, use a pinctrl-N property for some
number N, like this example you could place in your board's DTS file:
#include "board-pinctrl.dtsi"
&uart0 {
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
Properties
Top level properties
These property descriptions apply to “nuvoton,numaker-pinctrl” nodes themselves. This page also describes child node properties in the following sections.
Properties not inherited from the base binding file.
(None)
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “nuvoton,numaker-pinctrl” compatible.
Name |
Type |
Details |
|---|---|---|
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register space
This property is required. See Important properties for more information. |
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indicates the operational status of a device
Legal values: See Important properties for more information. |
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compatible strings
This property is required. See Important properties for more information. |
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name of each register space
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interrupts for device
See Important properties for more information. |
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extended interrupt specifier for device
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name of each interrupt
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phandle to interrupt controller node
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No description provided for this label
See Important properties for more information. |
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Clock gate information
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name of each clock
|
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number of address cells in reg property
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number of size cells in reg property
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
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mailbox / IPM channels specifiers
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Provided names of mailbox / IPM channel specifiers
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Power domain specifiers
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Provided names of power domain specifiers
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Number of cells in power-domains property
|
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
|
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
|
Grandchild node properties
Name |
Type |
Details |
|---|---|---|
|
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An array of pins sharing the same group properties. The pins should
be defined using pre-defined macros or, alternatively, using NVT_PINMUX
macros depending on the pinmux model used by the SoC series.
This property is required. |
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Set the driving strength of a pin. Hardware default configuration is low and
it's enough to drive most components, like as LED, CAN transceiver and so on.
Default value: Legal values: |
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Set the speed of a pin. This setting effectively limits the
slew rate of the output signal. Hardware default configuration is low.
Fast slew rate could support fast speed pins, like as SPI CLK up to 50MHz.
Default value: Legal values: |
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disable digital path on a pin.
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drive with open drain (hardware AND)
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enable schmitt-trigger mode
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